drivers/dma/stm32-dma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for STM32 DMA controller
   4  *
   5  * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   6  *
   7  * Copyright (C) M'boumba Cedric Madianga 2015
   8  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   9  *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/init.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30
  31 #include "virt-dma.h"
  32
  33 #define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  34 #define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  35 #define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  36 #define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  37 #define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  38 #define STM32_DMA_HTI                   BIT(4) /* Half Transfer Interrupt */
  39 #define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  40 #define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  41 #define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  42 #define STM32_DMA_MASKI                 (STM32_DMA_TCI \
  43                                          | STM32_DMA_TEI \
  44                                          | STM32_DMA_DMEI \
  45                                          | STM32_DMA_FEI)
  46
  47 /* DMA Stream x Configuration Register */
  48 #define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  49 #define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  50 #define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  51 #define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  52 #define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  53 #define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  54 #define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  55 #define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  56 #define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  57 #define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  58 #define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  59 #define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  60 #define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  61 #define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  62 #define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  63 #define STM32_DMA_SCR_TRBUFF            BIT(20) /* Bufferable transfer for USART/UART */
  64 #define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  65 #define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  66 #define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  67 #define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  68 #define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  69 #define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  70 #define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  71 #define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Complete Int Enable
  72                                                 */
  73 #define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  74 #define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  75 #define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  76 #define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  77                                         | STM32_DMA_SCR_MINC \
  78                                         | STM32_DMA_SCR_PINCOS \
  79                                         | STM32_DMA_SCR_PL_MASK)
  80 #define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  81                                         | STM32_DMA_SCR_TEIE \
  82                                         | STM32_DMA_SCR_DMEIE)
  83
  84 /* DMA Stream x number of data register */
  85 #define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  86
  87 /* DMA stream peripheral address register */
  88 #define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  89
  90 /* DMA stream x memory 0 address register */
  91 #define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  92
  93 /* DMA stream x memory 1 address register */
  94 #define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  95
  96 /* DMA stream x FIFO control register */
  97 #define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  98 #define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  99 #define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
 100 #define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
 101 #define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
 102 #define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
 103                                         | STM32_DMA_SFCR_DMDIS)
 104
 105 /* DMA direction */
 106 #define STM32_DMA_DEV_TO_MEM            0x00
 107 #define STM32_DMA_MEM_TO_DEV            0x01
 108 #define STM32_DMA_MEM_TO_MEM            0x02
 109
 110 /* DMA priority level */
 111 #define STM32_DMA_PRIORITY_LOW          0x00
 112 #define STM32_DMA_PRIORITY_MEDIUM       0x01
 113 #define STM32_DMA_PRIORITY_HIGH         0x02
 114 #define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 115
 116 /* DMA FIFO threshold selection */
 117 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 118 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 119 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 120 #define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 121 #define STM32_DMA_FIFO_THRESHOLD_NONE                   0x04
 122
 123 #define STM32_DMA_MAX_DATA_ITEMS        0xffff
 124 /*
 125  * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
 126  * gather at boundary. Thus it's safer to round down this value on FIFO
 127  * size (16 Bytes)
 128  */
 129 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS        \
 130         ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
 131 #define STM32_DMA_MAX_CHANNELS          0x08
 132 #define STM32_DMA_MAX_REQUEST_ID        0x08
 133 #define STM32_DMA_MAX_DATA_PARAM        0x03
 134 #define STM32_DMA_FIFO_SIZE             16      /* FIFO is 16 bytes */
 135 #define STM32_DMA_MIN_BURST             4
 136 #define STM32_DMA_MAX_BURST             16
 137
 138 /* DMA Features */
 139 #define STM32_DMA_THRESHOLD_FTR_MASK    GENMASK(1, 0)
 140 #define STM32_DMA_THRESHOLD_FTR_GET(n)  ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
 141 #define STM32_DMA_DIRECT_MODE_MASK      BIT(2)
 142 #define STM32_DMA_DIRECT_MODE_GET(n)    (((n) & STM32_DMA_DIRECT_MODE_MASK) >> 2)
 143 #define STM32_DMA_ALT_ACK_MODE_MASK     BIT(4)
 144 #define STM32_DMA_ALT_ACK_MODE_GET(n)   (((n) & STM32_DMA_ALT_ACK_MODE_MASK) >> 4)
 145
 146 enum stm32_dma_width {
 147         STM32_DMA_BYTE,
 148         STM32_DMA_HALF_WORD,
 149         STM32_DMA_WORD,
 150 };
 151
 152 enum stm32_dma_burst_size {
 153         STM32_DMA_BURST_SINGLE,
 154         STM32_DMA_BURST_INCR4,
 155         STM32_DMA_BURST_INCR8,
 156         STM32_DMA_BURST_INCR16,
 157 };
 158
 159 /**
 160  * struct stm32_dma_cfg - STM32 DMA custom configuration
 161  * @channel_id: channel ID
 162  * @request_line: DMA request
 163  * @stream_config: 32bit mask specifying the DMA channel configuration
 164  * @features: 32bit mask specifying the DMA Feature list
 165  */
 166 struct stm32_dma_cfg {
 167         u32 channel_id;
 168         u32 request_line;
 169         u32 stream_config;
 170         u32 features;
 171 };
 172
 173 struct stm32_dma_chan_reg {
 174         u32 dma_lisr;
 175         u32 dma_hisr;
 176         u32 dma_lifcr;
 177         u32 dma_hifcr;
 178         u32 dma_scr;
 179         u32 dma_sndtr;
 180         u32 dma_spar;
 181         u32 dma_sm0ar;
 182         u32 dma_sm1ar;
 183         u32 dma_sfcr;
 184 };
 185
 186 struct stm32_dma_sg_req {
 187         u32 len;
 188         struct stm32_dma_chan_reg chan_reg;
 189 };
 190
 191 struct stm32_dma_desc {
 192         struct virt_dma_desc vdesc;
 193         bool cyclic;
 194         u32 num_sgs;
 195         struct stm32_dma_sg_req sg_req[];
 196 };
 197
 198 struct stm32_dma_chan {
 199         struct virt_dma_chan vchan;
 200         bool config_init;
 201         bool busy;
 202         u32 id;
 203         u32 irq;
 204         struct stm32_dma_desc *desc;
 205         u32 next_sg;
 206         struct dma_slave_config dma_sconfig;
 207         struct stm32_dma_chan_reg chan_reg;
 208         u32 threshold;
 209         u32 mem_burst;
 210         u32 mem_width;
 211 };
 212
 213 struct stm32_dma_device {
 214         struct dma_device ddev;
 215         void __iomem *base;
 216         struct clk *clk;
 217         bool mem2mem;
 218         struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 219 };
 220
 221 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 222 {
 223         return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 224                             ddev);
 225 }
 226
 227 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 228 {
 229         return container_of(c, struct stm32_dma_chan, vchan.chan);
 230 }
 231
 232 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 233 {
 234         return container_of(vdesc, struct stm32_dma_desc, vdesc);
 235 }
 236
 237 static struct device *chan2dev(struct stm32_dma_chan *chan)
 238 {
 239         return &chan->vchan.chan.dev->device;
 240 }
 241
 242 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 243 {
 244         return readl_relaxed(dmadev->base + reg);
 245 }
 246
 247 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 248 {
 249         writel_relaxed(val, dmadev->base + reg);
 250 }
 251
 252 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 253                                enum dma_slave_buswidth width)
 254 {
 255         switch (width) {
 256         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 257                 return STM32_DMA_BYTE;
 258         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 259                 return STM32_DMA_HALF_WORD;
 260         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 261                 return STM32_DMA_WORD;
 262         default:
 263                 dev_err(chan2dev(chan), "Dma bus width not supported\n");
 264                 return -EINVAL;
 265         }
 266 }
 267
 268 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
 269                                                        dma_addr_t buf_addr,
 270                                                        u32 threshold)
 271 {
 272         enum dma_slave_buswidth max_width;
 273         u64 addr = buf_addr;
 274
 275         if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
 276                 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 277         else
 278                 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 279
 280         while ((buf_len < max_width  || buf_len % max_width) &&
 281                max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
 282                 max_width = max_width >> 1;
 283
 284         if (do_div(addr, max_width))
 285                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 286
 287         return max_width;
 288 }
 289
 290 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
 291                                                 enum dma_slave_buswidth width)
 292 {
 293         u32 remaining;
 294
 295         if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
 296                 return false;
 297
 298         if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 299                 if (burst != 0) {
 300                         /*
 301                          * If number of beats fit in several whole bursts
 302                          * this configuration is allowed.
 303                          */
 304                         remaining = ((STM32_DMA_FIFO_SIZE / width) *
 305                                      (threshold + 1) / 4) % burst;
 306
 307                         if (remaining == 0)
 308                                 return true;
 309                 } else {
 310                         return true;
 311                 }
 312         }
 313
 314         return false;
 315 }
 316
 317 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
 318 {
 319         /* If FIFO direct mode, burst is not possible */
 320         if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
 321                 return false;
 322
 323         /*
 324          * Buffer or period length has to be aligned on FIFO depth.
 325          * Otherwise bytes may be stuck within FIFO at buffer or period
 326          * length.
 327          */
 328         return ((buf_len % ((threshold + 1) * 4)) == 0);
 329 }
 330
 331 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
 332                                     enum dma_slave_buswidth width)
 333 {
 334         u32 best_burst = max_burst;
 335
 336         if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
 337                 return 0;
 338
 339         while ((buf_len < best_burst * width && best_burst > 1) ||
 340                !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
 341                                                     width)) {
 342                 if (best_burst > STM32_DMA_MIN_BURST)
 343                         best_burst = best_burst >> 1;
 344                 else
 345                         best_burst = 0;
 346         }
 347
 348         return best_burst;
 349 }
 350
 351 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 352 {
 353         switch (maxburst) {
 354         case 0:
 355         case 1:
 356                 return STM32_DMA_BURST_SINGLE;
 357         case 4:
 358                 return STM32_DMA_BURST_INCR4;
 359         case 8:
 360                 return STM32_DMA_BURST_INCR8;
 361         case 16:
 362                 return STM32_DMA_BURST_INCR16;
 363         default:
 364                 dev_err(chan2dev(chan), "Dma burst size not supported\n");
 365                 return -EINVAL;
 366         }
 367 }
 368
 369 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 370                                       u32 src_burst, u32 dst_burst)
 371 {
 372         chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 373         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 374
 375         if (!src_burst && !dst_burst) {
 376                 /* Using direct mode */
 377                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 378         } else {
 379                 /* Using FIFO mode */
 380                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 381         }
 382 }
 383
 384 static int stm32_dma_slave_config(struct dma_chan *c,
 385                                   struct dma_slave_config *config)
 386 {
 387         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 388
 389         memcpy(&chan->dma_sconfig, config, sizeof(*config));
 390
 391         chan->config_init = true;
 392
 393         return 0;
 394 }
 395
 396 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 397 {
 398         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 399         u32 flags, dma_isr;
 400
 401         /*
 402          * Read "flags" from DMA_xISR register corresponding to the selected
 403          * DMA channel at the correct bit offset inside that register.
 404          *
 405          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 406          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 407          */
 408
 409         if (chan->id & 4)
 410                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 411         else
 412                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 413
 414         flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 415
 416         return flags & STM32_DMA_MASKI;
 417 }
 418
 419 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 420 {
 421         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 422         u32 dma_ifcr;
 423
 424         /*
 425          * Write "flags" to the DMA_xIFCR register corresponding to the selected
 426          * DMA channel at the correct bit offset inside that register.
 427          *
 428          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 429          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 430          */
 431         flags &= STM32_DMA_MASKI;
 432         dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 433
 434         if (chan->id & 4)
 435                 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 436         else
 437                 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 438 }
 439
 440 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 441 {
 442         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 443         u32 dma_scr, id, reg;
 444
 445         id = chan->id;
 446         reg = STM32_DMA_SCR(id);
 447         dma_scr = stm32_dma_read(dmadev, reg);
 448
 449         if (dma_scr & STM32_DMA_SCR_EN) {
 450                 dma_scr &= ~STM32_DMA_SCR_EN;
 451                 stm32_dma_write(dmadev, reg, dma_scr);
 452
 453                 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
 454                                         dma_scr, !(dma_scr & STM32_DMA_SCR_EN),
 455                                         10, 1000000);
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void stm32_dma_stop(struct stm32_dma_chan *chan)
 462 {
 463         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 464         u32 dma_scr, dma_sfcr, status;
 465         int ret;
 466
 467         /* Disable interrupts */
 468         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 469         dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 470         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 471         dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 472         dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 473         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 474
 475         /* Disable DMA */
 476         ret = stm32_dma_disable_chan(chan);
 477         if (ret < 0)
 478                 return;
 479
 480         /* Clear interrupt status if it is there */
 481         status = stm32_dma_irq_status(chan);
 482         if (status) {
 483                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 484                         __func__, status);
 485                 stm32_dma_irq_clear(chan, status);
 486         }
 487
 488         chan->busy = false;
 489 }
 490
 491 static int stm32_dma_terminate_all(struct dma_chan *c)
 492 {
 493         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 494         unsigned long flags;
 495         LIST_HEAD(head);
 496
 497         spin_lock_irqsave(&chan->vchan.lock, flags);
 498
 499         if (chan->desc) {
 500                 vchan_terminate_vdesc(&chan->desc->vdesc);
 501                 if (chan->busy)
 502                         stm32_dma_stop(chan);
 503                 chan->desc = NULL;
 504         }
 505
 506         vchan_get_all_descriptors(&chan->vchan, &head);
 507         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 508         vchan_dma_desc_free_list(&chan->vchan, &head);
 509
 510         return 0;
 511 }
 512
 513 static void stm32_dma_synchronize(struct dma_chan *c)
 514 {
 515         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 516
 517         vchan_synchronize(&chan->vchan);
 518 }
 519
 520 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 521 {
 522         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 523         u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 524         u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 525         u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 526         u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 527         u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 528         u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 529
 530         dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 531         dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 532         dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 533         dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 534         dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 535         dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 536 }
 537
 538 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 539
 540 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 541 {
 542         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 543         struct virt_dma_desc *vdesc;
 544         struct stm32_dma_sg_req *sg_req;
 545         struct stm32_dma_chan_reg *reg;
 546         u32 status;
 547         int ret;
 548
 549         ret = stm32_dma_disable_chan(chan);
 550         if (ret < 0)
 551                 return;
 552
 553         if (!chan->desc) {
 554                 vdesc = vchan_next_desc(&chan->vchan);
 555                 if (!vdesc)
 556                         return;
 557
 558                 list_del(&vdesc->node);
 559
 560                 chan->desc = to_stm32_dma_desc(vdesc);
 561                 chan->next_sg = 0;
 562         }
 563
 564         if (chan->next_sg == chan->desc->num_sgs)
 565                 chan->next_sg = 0;
 566
 567         sg_req = &chan->desc->sg_req[chan->next_sg];
 568         reg = &sg_req->chan_reg;
 569
 570         reg->dma_scr &= ~STM32_DMA_SCR_EN;
 571         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 572         stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 573         stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 574         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 575         stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 576         stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 577
 578         chan->next_sg++;
 579
 580         /* Clear interrupt status if it is there */
 581         status = stm32_dma_irq_status(chan);
 582         if (status)
 583                 stm32_dma_irq_clear(chan, status);
 584
 585         if (chan->desc->cyclic)
 586                 stm32_dma_configure_next_sg(chan);
 587
 588         stm32_dma_dump_reg(chan);
 589
 590         /* Start DMA */
 591         reg->dma_scr |= STM32_DMA_SCR_EN;
 592         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 593
 594         chan->busy = true;
 595
 596         dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
 597 }
 598
 599 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 600 {
 601         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 602         struct stm32_dma_sg_req *sg_req;
 603         u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 604
 605         id = chan->id;
 606         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 607
 608         if (dma_scr & STM32_DMA_SCR_DBM) {
 609                 if (chan->next_sg == chan->desc->num_sgs)
 610                         chan->next_sg = 0;
 611
 612                 sg_req = &chan->desc->sg_req[chan->next_sg];
 613
 614                 if (dma_scr & STM32_DMA_SCR_CT) {
 615                         dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 616                         stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 617                         dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 618                                 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 619                 } else {
 620                         dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 621                         stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 622                         dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 623                                 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 624                 }
 625         }
 626 }
 627
 628 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 629 {
 630         if (chan->desc) {
 631                 if (chan->desc->cyclic) {
 632                         vchan_cyclic_callback(&chan->desc->vdesc);
 633                         chan->next_sg++;
 634                         stm32_dma_configure_next_sg(chan);
 635                 } else {
 636                         chan->busy = false;
 637                         if (chan->next_sg == chan->desc->num_sgs) {
 638                                 vchan_cookie_complete(&chan->desc->vdesc);
 639                                 chan->desc = NULL;
 640                         }
 641                         stm32_dma_start_transfer(chan);
 642                 }
 643         }
 644 }
 645
 646 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 647 {
 648         struct stm32_dma_chan *chan = devid;
 649         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 650         u32 status, scr, sfcr;
 651
 652         spin_lock(&chan->vchan.lock);
 653
 654         status = stm32_dma_irq_status(chan);
 655         scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 656         sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 657
 658         if (status & STM32_DMA_FEI) {
 659                 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
 660                 status &= ~STM32_DMA_FEI;
 661                 if (sfcr & STM32_DMA_SFCR_FEIE) {
 662                         if (!(scr & STM32_DMA_SCR_EN) &&
 663                             !(status & STM32_DMA_TCI))
 664                                 dev_err(chan2dev(chan), "FIFO Error\n");
 665                         else
 666                                 dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
 667                 }
 668         }
 669         if (status & STM32_DMA_DMEI) {
 670                 stm32_dma_irq_clear(chan, STM32_DMA_DMEI);
 671                 status &= ~STM32_DMA_DMEI;
 672                 if (sfcr & STM32_DMA_SCR_DMEIE)
 673                         dev_dbg(chan2dev(chan), "Direct mode overrun\n");
 674         }
 675
 676         if (status & STM32_DMA_TCI) {
 677                 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 678                 if (scr & STM32_DMA_SCR_TCIE)
 679                         stm32_dma_handle_chan_done(chan);
 680                 status &= ~STM32_DMA_TCI;
 681         }
 682
 683         if (status & STM32_DMA_HTI) {
 684                 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
 685                 status &= ~STM32_DMA_HTI;
 686         }
 687
 688         if (status) {
 689                 stm32_dma_irq_clear(chan, status);
 690                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 691                 if (!(scr & STM32_DMA_SCR_EN))
 692                         dev_err(chan2dev(chan), "chan disabled by HW\n");
 693         }
 694
 695         spin_unlock(&chan->vchan.lock);
 696
 697         return IRQ_HANDLED;
 698 }
 699
 700 static void stm32_dma_issue_pending(struct dma_chan *c)
 701 {
 702         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 703         unsigned long flags;
 704
 705         spin_lock_irqsave(&chan->vchan.lock, flags);
 706         if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 707                 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
 708                 stm32_dma_start_transfer(chan);
 709
 710         }
 711         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 712 }
 713
 714 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 715                                     enum dma_transfer_direction direction,
 716                                     enum dma_slave_buswidth *buswidth,
 717                                     u32 buf_len, dma_addr_t buf_addr)
 718 {
 719         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 720         int src_bus_width, dst_bus_width;
 721         int src_burst_size, dst_burst_size;
 722         u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 723         u32 dma_scr, fifoth;
 724
 725         src_addr_width = chan->dma_sconfig.src_addr_width;
 726         dst_addr_width = chan->dma_sconfig.dst_addr_width;
 727         src_maxburst = chan->dma_sconfig.src_maxburst;
 728         dst_maxburst = chan->dma_sconfig.dst_maxburst;
 729         fifoth = chan->threshold;
 730
 731         switch (direction) {
 732         case DMA_MEM_TO_DEV:
 733                 /* Set device data size */
 734                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 735                 if (dst_bus_width < 0)
 736                         return dst_bus_width;
 737
 738                 /* Set device burst size */
 739                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 740                                                           dst_maxburst,
 741                                                           fifoth,
 742                                                           dst_addr_width);
 743
 744                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 745                 if (dst_burst_size < 0)
 746                         return dst_burst_size;
 747
 748                 /* Set memory data size */
 749                 src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
 750                                                          fifoth);
 751                 chan->mem_width = src_addr_width;
 752                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 753                 if (src_bus_width < 0)
 754                         return src_bus_width;
 755
 756                 /* Set memory burst size */
 757                 src_maxburst = STM32_DMA_MAX_BURST;
 758                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 759                                                           src_maxburst,
 760                                                           fifoth,
 761                                                           src_addr_width);
 762                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 763                 if (src_burst_size < 0)
 764                         return src_burst_size;
 765
 766                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 767                         STM32_DMA_SCR_PSIZE(dst_bus_width) |
 768                         STM32_DMA_SCR_MSIZE(src_bus_width) |
 769                         STM32_DMA_SCR_PBURST(dst_burst_size) |
 770                         STM32_DMA_SCR_MBURST(src_burst_size);
 771
 772                 /* Set FIFO threshold */
 773                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 774                 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
 775                         chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
 776
 777                 /* Set peripheral address */
 778                 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 779                 *buswidth = dst_addr_width;
 780                 break;
 781
 782         case DMA_DEV_TO_MEM:
 783                 /* Set device data size */
 784                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 785                 if (src_bus_width < 0)
 786                         return src_bus_width;
 787
 788                 /* Set device burst size */
 789                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 790                                                           src_maxburst,
 791                                                           fifoth,
 792                                                           src_addr_width);
 793                 chan->mem_burst = src_best_burst;
 794                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 795                 if (src_burst_size < 0)
 796                         return src_burst_size;
 797
 798                 /* Set memory data size */
 799                 dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
 800                                                          fifoth);
 801                 chan->mem_width = dst_addr_width;
 802                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 803                 if (dst_bus_width < 0)
 804                         return dst_bus_width;
 805
 806                 /* Set memory burst size */
 807                 dst_maxburst = STM32_DMA_MAX_BURST;
 808                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 809                                                           dst_maxburst,
 810                                                           fifoth,
 811                                                           dst_addr_width);
 812                 chan->mem_burst = dst_best_burst;
 813                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 814                 if (dst_burst_size < 0)
 815                         return dst_burst_size;
 816
 817                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 818                         STM32_DMA_SCR_PSIZE(src_bus_width) |
 819                         STM32_DMA_SCR_MSIZE(dst_bus_width) |
 820                         STM32_DMA_SCR_PBURST(src_burst_size) |
 821                         STM32_DMA_SCR_MBURST(dst_burst_size);
 822
 823                 /* Set FIFO threshold */
 824                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 825                 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
 826                         chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth);
 827
 828                 /* Set peripheral address */
 829                 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 830                 *buswidth = chan->dma_sconfig.src_addr_width;
 831                 break;
 832
 833         default:
 834                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 835                 return -EINVAL;
 836         }
 837
 838         stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
 839
 840         /* Set DMA control register */
 841         chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 842                         STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 843                         STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 844         chan->chan_reg.dma_scr |= dma_scr;
 845
 846         return 0;
 847 }
 848
 849 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 850 {
 851         memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 852 }
 853
 854 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 855         struct dma_chan *c, struct scatterlist *sgl,
 856         u32 sg_len, enum dma_transfer_direction direction,
 857         unsigned long flags, void *context)
 858 {
 859         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 860         struct stm32_dma_desc *desc;
 861         struct scatterlist *sg;
 862         enum dma_slave_buswidth buswidth;
 863         u32 nb_data_items;
 864         int i, ret;
 865
 866         if (!chan->config_init) {
 867                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 868                 return NULL;
 869         }
 870
 871         if (sg_len < 1) {
 872                 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 873                 return NULL;
 874         }
 875
 876         desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
 877         if (!desc)
 878                 return NULL;
 879
 880         /* Set peripheral flow controller */
 881         if (chan->dma_sconfig.device_fc)
 882                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 883         else
 884                 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 885
 886         for_each_sg(sgl, sg, sg_len, i) {
 887                 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
 888                                                sg_dma_len(sg),
 889                                                sg_dma_address(sg));
 890                 if (ret < 0)
 891                         goto err;
 892
 893                 desc->sg_req[i].len = sg_dma_len(sg);
 894
 895                 nb_data_items = desc->sg_req[i].len / buswidth;
 896                 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 897                         dev_err(chan2dev(chan), "nb items not supported\n");
 898                         goto err;
 899                 }
 900
 901                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 902                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 903                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 904                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 905                 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 906                 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 907                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 908         }
 909
 910         desc->num_sgs = sg_len;
 911         desc->cyclic = false;
 912
 913         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 914
 915 err:
 916         kfree(desc);
 917         return NULL;
 918 }
 919
 920 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 921         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 922         size_t period_len, enum dma_transfer_direction direction,
 923         unsigned long flags)
 924 {
 925         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 926         struct stm32_dma_desc *desc;
 927         enum dma_slave_buswidth buswidth;
 928         u32 num_periods, nb_data_items;
 929         int i, ret;
 930
 931         if (!buf_len || !period_len) {
 932                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 933                 return NULL;
 934         }
 935
 936         if (!chan->config_init) {
 937                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 938                 return NULL;
 939         }
 940
 941         if (buf_len % period_len) {
 942                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 943                 return NULL;
 944         }
 945
 946         /*
 947          * We allow to take more number of requests till DMA is
 948          * not started. The driver will loop over all requests.
 949          * Once DMA is started then new requests can be queued only after
 950          * terminating the DMA.
 951          */
 952         if (chan->busy) {
 953                 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 954                 return NULL;
 955         }
 956
 957         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len,
 958                                        buf_addr);
 959         if (ret < 0)
 960                 return NULL;
 961
 962         nb_data_items = period_len / buswidth;
 963         if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 964                 dev_err(chan2dev(chan), "number of items not supported\n");
 965                 return NULL;
 966         }
 967
 968         /*  Enable Circular mode or double buffer mode */
 969         if (buf_len == period_len)
 970                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 971         else
 972                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 973
 974         /* Clear periph ctrl if client set it */
 975         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 976
 977         num_periods = buf_len / period_len;
 978
 979         desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT);
 980         if (!desc)
 981                 return NULL;
 982
 983         for (i = 0; i < num_periods; i++) {
 984                 desc->sg_req[i].len = period_len;
 985
 986                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 987                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 988                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 989                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 990                 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
 991                 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
 992                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 993                 buf_addr += period_len;
 994         }
 995
 996         desc->num_sgs = num_periods;
 997         desc->cyclic = true;
 998
 999         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1000 }
1001
1002 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
1003         struct dma_chan *c, dma_addr_t dest,
1004         dma_addr_t src, size_t len, unsigned long flags)
1005 {
1006         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1007         enum dma_slave_buswidth max_width;
1008         struct stm32_dma_desc *desc;
1009         size_t xfer_count, offset;
1010         u32 num_sgs, best_burst, dma_burst, threshold;
1011         int i;
1012
1013         num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1014         desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
1015         if (!desc)
1016                 return NULL;
1017
1018         threshold = chan->threshold;
1019
1020         for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
1021                 xfer_count = min_t(size_t, len - offset,
1022                                    STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1023
1024                 /* Compute best burst size */
1025                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1026                 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1027                                                       threshold, max_width);
1028                 dma_burst = stm32_dma_get_burst(chan, best_burst);
1029
1030                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1031                 desc->sg_req[i].chan_reg.dma_scr =
1032                         STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
1033                         STM32_DMA_SCR_PBURST(dma_burst) |
1034                         STM32_DMA_SCR_MBURST(dma_burst) |
1035                         STM32_DMA_SCR_MINC |
1036                         STM32_DMA_SCR_PINC |
1037                         STM32_DMA_SCR_TCIE |
1038                         STM32_DMA_SCR_TEIE;
1039                 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1040                 desc->sg_req[i].chan_reg.dma_sfcr |=
1041                         STM32_DMA_SFCR_FTH(threshold);
1042                 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1043                 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1044                 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1045                 desc->sg_req[i].len = xfer_count;
1046         }
1047
1048         desc->num_sgs = num_sgs;
1049         desc->cyclic = false;
1050
1051         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1052 }
1053
1054 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1055 {
1056         u32 dma_scr, width, ndtr;
1057         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1058
1059         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1060         width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1061         ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1062
1063         return ndtr << width;
1064 }
1065
1066 /**
1067  * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1068  * @chan: dma channel
1069  *
1070  * This function called when IRQ are disable, checks that the hardware has not
1071  * switched on the next transfer in double buffer mode. The test is done by
1072  * comparing the next_sg memory address with the hardware related register
1073  * (based on CT bit value).
1074  *
1075  * Returns true if expected current transfer is still running or double
1076  * buffer mode is not activated.
1077  */
1078 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
1079 {
1080         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1081         struct stm32_dma_sg_req *sg_req;
1082         u32 dma_scr, dma_smar, id;
1083
1084         id = chan->id;
1085         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1086
1087         if (!(dma_scr & STM32_DMA_SCR_DBM))
1088                 return true;
1089
1090         sg_req = &chan->desc->sg_req[chan->next_sg];
1091
1092         if (dma_scr & STM32_DMA_SCR_CT) {
1093                 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1094                 return (dma_smar == sg_req->chan_reg.dma_sm0ar);
1095         }
1096
1097         dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1098
1099         return (dma_smar == sg_req->chan_reg.dma_sm1ar);
1100 }
1101
1102 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1103                                      struct stm32_dma_desc *desc,
1104                                      u32 next_sg)
1105 {
1106         u32 modulo, burst_size;
1107         u32 residue;
1108         u32 n_sg = next_sg;
1109         struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
1110         int i;
1111
1112         /*
1113          * Calculate the residue means compute the descriptors
1114          * information:
1115          * - the sg_req currently transferred
1116          * - the Hardware remaining position in this sg (NDTR bits field).
1117          *
1118          * A race condition may occur if DMA is running in cyclic or double
1119          * buffer mode, since the DMA register are automatically reloaded at end
1120          * of period transfer. The hardware may have switched to the next
1121          * transfer (CT bit updated) just before the position (SxNDTR reg) is
1122          * read.
1123          * In this case the SxNDTR reg could (or not) correspond to the new
1124          * transfer position, and not the expected one.
1125          * The strategy implemented in the stm32 driver is to:
1126          *  - read the SxNDTR register
1127          *  - crosscheck that hardware is still in current transfer.
1128          * In case of switch, we can assume that the DMA is at the beginning of
1129          * the next transfer. So we approximate the residue in consequence, by
1130          * pointing on the beginning of next transfer.
1131          *
1132          * This race condition doesn't apply for none cyclic mode, as double
1133          * buffer is not used. In such situation registers are updated by the
1134          * software.
1135          */
1136
1137         residue = stm32_dma_get_remaining_bytes(chan);
1138
1139         if (!stm32_dma_is_current_sg(chan)) {
1140                 n_sg++;
1141                 if (n_sg == chan->desc->num_sgs)
1142                         n_sg = 0;
1143                 residue = sg_req->len;
1144         }
1145
1146         /*
1147          * In cyclic mode, for the last period, residue = remaining bytes
1148          * from NDTR,
1149          * else for all other periods in cyclic mode, and in sg mode,
1150          * residue = remaining bytes from NDTR + remaining
1151          * periods/sg to be transferred
1152          */
1153         if (!chan->desc->cyclic || n_sg != 0)
1154                 for (i = n_sg; i < desc->num_sgs; i++)
1155                         residue += desc->sg_req[i].len;
1156
1157         if (!chan->mem_burst)
1158                 return residue;
1159
1160         burst_size = chan->mem_burst * chan->mem_width;
1161         modulo = residue % burst_size;
1162         if (modulo)
1163                 residue = residue - modulo + burst_size;
1164
1165         return residue;
1166 }
1167
1168 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1169                                            dma_cookie_t cookie,
1170                                            struct dma_tx_state *state)
1171 {
1172         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1173         struct virt_dma_desc *vdesc;
1174         enum dma_status status;
1175         unsigned long flags;
1176         u32 residue = 0;
1177
1178         status = dma_cookie_status(c, cookie, state);
1179         if (status == DMA_COMPLETE || !state)
1180                 return status;
1181
1182         spin_lock_irqsave(&chan->vchan.lock, flags);
1183         vdesc = vchan_find_desc(&chan->vchan, cookie);
1184         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1185                 residue = stm32_dma_desc_residue(chan, chan->desc,
1186                                                  chan->next_sg);
1187         else if (vdesc)
1188                 residue = stm32_dma_desc_residue(chan,
1189                                                  to_stm32_dma_desc(vdesc), 0);
1190         dma_set_residue(state, residue);
1191
1192         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1193
1194         return status;
1195 }
1196
1197 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1198 {
1199         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1200         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1201         int ret;
1202
1203         chan->config_init = false;
1204
1205         ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1206         if (ret < 0)
1207                 return ret;
1208
1209         ret = stm32_dma_disable_chan(chan);
1210         if (ret < 0)
1211                 pm_runtime_put(dmadev->ddev.dev);
1212
1213         return ret;
1214 }
1215
1216 static void stm32_dma_free_chan_resources(struct dma_chan *c)
1217 {
1218         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1219         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1220         unsigned long flags;
1221
1222         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1223
1224         if (chan->busy) {
1225                 spin_lock_irqsave(&chan->vchan.lock, flags);
1226                 stm32_dma_stop(chan);
1227                 chan->desc = NULL;
1228                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1229         }
1230
1231         pm_runtime_put(dmadev->ddev.dev);
1232
1233         vchan_free_chan_resources(to_virt_chan(c));
1234         stm32_dma_clear_reg(&chan->chan_reg);
1235         chan->threshold = 0;
1236 }
1237
1238 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1239 {
1240         kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1241 }
1242
1243 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1244                                  struct stm32_dma_cfg *cfg)
1245 {
1246         stm32_dma_clear_reg(&chan->chan_reg);
1247
1248         chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1249         chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1250
1251         /* Enable Interrupts  */
1252         chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1253
1254         chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1255         if (STM32_DMA_DIRECT_MODE_GET(cfg->features))
1256                 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE;
1257         if (STM32_DMA_ALT_ACK_MODE_GET(cfg->features))
1258                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;
1259 }
1260
1261 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1262                                            struct of_dma *ofdma)
1263 {
1264         struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1265         struct device *dev = dmadev->ddev.dev;
1266         struct stm32_dma_cfg cfg;
1267         struct stm32_dma_chan *chan;
1268         struct dma_chan *c;
1269
1270         if (dma_spec->args_count < 4) {
1271                 dev_err(dev, "Bad number of cells\n");
1272                 return NULL;
1273         }
1274
1275         cfg.channel_id = dma_spec->args[0];
1276         cfg.request_line = dma_spec->args[1];
1277         cfg.stream_config = dma_spec->args[2];
1278         cfg.features = dma_spec->args[3];
1279
1280         if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1281             cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1282                 dev_err(dev, "Bad channel and/or request id\n");
1283                 return NULL;
1284         }
1285
1286         chan = &dmadev->chan[cfg.channel_id];
1287
1288         c = dma_get_slave_channel(&chan->vchan.chan);
1289         if (!c) {
1290                 dev_err(dev, "No more channels available\n");
1291                 return NULL;
1292         }
1293
1294         stm32_dma_set_config(chan, &cfg);
1295
1296         return c;
1297 }
1298
1299 static const struct of_device_id stm32_dma_of_match[] = {
1300         { .compatible = "st,stm32-dma", },
1301         { /* sentinel */ },
1302 };
1303 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1304
1305 static int stm32_dma_probe(struct platform_device *pdev)
1306 {
1307         struct stm32_dma_chan *chan;
1308         struct stm32_dma_device *dmadev;
1309         struct dma_device *dd;
1310         const struct of_device_id *match;
1311         struct resource *res;
1312         struct reset_control *rst;
1313         int i, ret;
1314
1315         match = of_match_device(stm32_dma_of_match, &pdev->dev);
1316         if (!match) {
1317                 dev_err(&pdev->dev, "Error: No device match found\n");
1318                 return -ENODEV;
1319         }
1320
1321         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1322         if (!dmadev)
1323                 return -ENOMEM;
1324
1325         dd = &dmadev->ddev;
1326
1327         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1328         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1329         if (IS_ERR(dmadev->base))
1330                 return PTR_ERR(dmadev->base);
1331
1332         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1333         if (IS_ERR(dmadev->clk))
1334                 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
1335
1336         ret = clk_prepare_enable(dmadev->clk);
1337         if (ret < 0) {
1338                 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1339                 return ret;
1340         }
1341
1342         dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1343                                                 "st,mem2mem");
1344
1345         rst = devm_reset_control_get(&pdev->dev, NULL);
1346         if (IS_ERR(rst)) {
1347                 ret = PTR_ERR(rst);
1348                 if (ret == -EPROBE_DEFER)
1349                         goto clk_free;
1350         } else {
1351                 reset_control_assert(rst);
1352                 udelay(2);
1353                 reset_control_deassert(rst);
1354         }
1355
1356         dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1357
1358         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1359         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1360         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1361         dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1362         dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1363         dd->device_tx_status = stm32_dma_tx_status;
1364         dd->device_issue_pending = stm32_dma_issue_pending;
1365         dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1366         dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1367         dd->device_config = stm32_dma_slave_config;
1368         dd->device_terminate_all = stm32_dma_terminate_all;
1369         dd->device_synchronize = stm32_dma_synchronize;
1370         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1371                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1372                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1373         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1374                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1375                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1376         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1377         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1378         dd->copy_align = DMAENGINE_ALIGN_32_BYTES;
1379         dd->max_burst = STM32_DMA_MAX_BURST;
1380         dd->descriptor_reuse = true;
1381         dd->dev = &pdev->dev;
1382         INIT_LIST_HEAD(&dd->channels);
1383
1384         if (dmadev->mem2mem) {
1385                 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1386                 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1387                 dd->directions |= BIT(DMA_MEM_TO_MEM);
1388         }
1389
1390         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1391                 chan = &dmadev->chan[i];
1392                 chan->id = i;
1393                 chan->vchan.desc_free = stm32_dma_desc_free;
1394                 vchan_init(&chan->vchan, dd);
1395         }
1396
1397         ret = dma_async_device_register(dd);
1398         if (ret)
1399                 goto clk_free;
1400
1401         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1402                 chan = &dmadev->chan[i];
1403                 ret = platform_get_irq(pdev, i);
1404                 if (ret < 0)
1405                         goto err_unregister;
1406                 chan->irq = ret;
1407
1408                 ret = devm_request_irq(&pdev->dev, chan->irq,
1409                                        stm32_dma_chan_irq, 0,
1410                                        dev_name(chan2dev(chan)), chan);
1411                 if (ret) {
1412                         dev_err(&pdev->dev,
1413                                 "request_irq failed with err %d channel %d\n",
1414                                 ret, i);
1415                         goto err_unregister;
1416                 }
1417         }
1418
1419         ret = of_dma_controller_register(pdev->dev.of_node,
1420                                          stm32_dma_of_xlate, dmadev);
1421         if (ret < 0) {
1422                 dev_err(&pdev->dev,
1423                         "STM32 DMA DMA OF registration failed %d\n", ret);
1424                 goto err_unregister;
1425         }
1426
1427         platform_set_drvdata(pdev, dmadev);
1428
1429         pm_runtime_set_active(&pdev->dev);
1430         pm_runtime_enable(&pdev->dev);
1431         pm_runtime_get_noresume(&pdev->dev);
1432         pm_runtime_put(&pdev->dev);
1433
1434         dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1435
1436         return 0;
1437
1438 err_unregister:
1439         dma_async_device_unregister(dd);
1440 clk_free:
1441         clk_disable_unprepare(dmadev->clk);
1442
1443         return ret;
1444 }
1445
1446 #ifdef CONFIG_PM
1447 static int stm32_dma_runtime_suspend(struct device *dev)
1448 {
1449         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1450
1451         clk_disable_unprepare(dmadev->clk);
1452
1453         return 0;
1454 }
1455
1456 static int stm32_dma_runtime_resume(struct device *dev)
1457 {
1458         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1459         int ret;
1460
1461         ret = clk_prepare_enable(dmadev->clk);
1462         if (ret) {
1463                 dev_err(dev, "failed to prepare_enable clock\n");
1464                 return ret;
1465         }
1466
1467         return 0;
1468 }
1469 #endif
1470
1471 #ifdef CONFIG_PM_SLEEP
1472 static int stm32_dma_suspend(struct device *dev)
1473 {
1474         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1475         int id, ret, scr;
1476
1477         ret = pm_runtime_resume_and_get(dev);
1478         if (ret < 0)
1479                 return ret;
1480
1481         for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) {
1482                 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1483                 if (scr & STM32_DMA_SCR_EN) {
1484                         dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
1485                         return -EBUSY;
1486                 }
1487         }
1488
1489         pm_runtime_put_sync(dev);
1490
1491         pm_runtime_force_suspend(dev);
1492
1493         return 0;
1494 }
1495
1496 static int stm32_dma_resume(struct device *dev)
1497 {
1498         return pm_runtime_force_resume(dev);
1499 }
1500 #endif
1501
1502 static const struct dev_pm_ops stm32_dma_pm_ops = {
1503         SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume)
1504         SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
1505                            stm32_dma_runtime_resume, NULL)
1506 };
1507
1508 static struct platform_driver stm32_dma_driver = {
1509         .driver = {
1510                 .name = "stm32-dma",
1511                 .of_match_table = stm32_dma_of_match,
1512                 .pm = &stm32_dma_pm_ops,
1513         },
1514         .probe = stm32_dma_probe,
1515 };
1516
1517 static int __init stm32_dma_init(void)
1518 {
1519         return platform_driver_register(&stm32_dma_driver);
1520 }
1521 subsys_initcall(stm32_dma_init);