2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
18 #define DMA_UID_SOFTWARE 0
20 #define CHN_PRIORITY_OFFSET 12
21 #define CHN_PRIORITY_MASK 0x3
22 #define LLIST_EN_OFFSET 4
24 #define SRC_DATAWIDTH_OFFSET 30
25 #define DES_DATAWIDTH_OFFSET 28
26 #define SWT_MODE_OFFSET 26
27 #define REQ_MODE_OFFSET 24
28 #define ADDR_WRAP_SEL_OFFSET 23
29 #define ADDR_WRAP_EN_OFFSET 22
30 #define ADDR_FIX_SEL_OFFSET 21
31 #define ADDR_FIX_SEL_EN 20
32 #define LLIST_END_OFFSET 19
33 #define BLK_LEN_REC_H_OFFSET 17
34 #define FRG_LEN_OFFSET 0
36 #define DEST_TRSF_STEP_OFFSET 16
37 #define SRC_TRSF_STEP_OFFSET 0
38 #define DEST_FRAG_STEP_OFFSET 16
39 #define SRC_FRAG_STEP_OFFSET 0
41 #define TRSF_STEP_MASK 0xffff
42 #define FRAG_STEP_MASK 0xffff
44 #define DATAWIDTH_MASK 0x3
45 #define SWT_MODE_MASK 0x3
46 #define REQ_MODE_MASK 0x3
47 #define ADDR_WRAP_SEL_MASK 0x1
48 #define ADDR_WRAP_EN_MASK 0x1
49 #define ADDR_FIX_SEL_MASK 0x1
50 #define ADDR_FIX_SEL_MASK 0x1
51 #define LLIST_END_MASK 0x1
52 #define BLK_LEN_REC_H_MASKT 0x3
53 #define FRG_LEN_MASK 0x1ffff
55 #define BLK_LEN_MASK 0x1ffff
56 #define TRSC_LEN_MASK 0xfffffff
95 struct sprd_dma_glb_reg {
108 struct sprd_dma_cfg {
109 unsigned long link_cfg_v;
110 unsigned long link_cfg_p;
112 dma_datawidth datawidth;
119 dma_request_mode req_mode;
120 dma_int_type irq_mode;
121 /*only full chn need following config*/
138 enum dma_filter_param {
139 AP_STANDARD_DMA = 0x11,
141 AON_STANDARD_DMA = 0x33,
143 NUM_REQUEST_DMA = 0x100,
146 enum dma_chn_status {
162 DMA_CFG_FLAG = BIT(0),
163 DMA_HARDWARE_FLAG = BIT(1),
164 DMA_SOFTWARE_FLAG = BIT(2),
173 SPRD_SRC_ADDR = 0x55,
174 SPRD_DST_ADDR = 0xAA,
177 #if defined(CONFIG_ARCH_SC8825) || defined(CONFIG_ARCH_SC7710)
180 #define DMA_UID_SOFTWARE 0
181 #define DMA_UART0_TX 1
182 #define DMA_UART0_RX 2
183 #define DMA_UART1_TX 3
184 #define DMA_UART1_RX 4
185 #define DMA_UART2_TX 5
186 #define DMA_UART2_RX 6
190 #define DMA_EPT_TX 10
191 #define DMA_VB_DA0 11
192 #define DMA_VB_DA1 12
193 #define DMA_VB_AD0 13
194 #define DMA_VB_AD1 14
195 #define DMA_SIM0_TX 15
196 #define DMA_SIM0_RX 16
197 #define DMA_SIM1_TX 17
198 #define DMA_SIM1_RX 18
199 #define DMA_SPI0_TX 19
200 #define DMA_SPI0_RX 20
202 #define DMA_SPI1_TX 22
203 #define DMA_SPI1_RX 23
204 #define DMA_IIS1_TX 24
205 #define DMA_IIS1_RX 25
206 #define DMA_NFC_TX 26
207 #define DMA_NFC_RX 27
208 #define DMA_DRM_RAW 29
209 #define DMA_DRM_CPT 30
211 #define DMA_UID_MIN 0
212 #define DMA_UID_MAX 32
217 #ifdef CONFIG_ARCH_SCX35
219 /*DMA Request ID def*/
222 #define DMA_IIS0_RX 3
223 #define DMA_IIS0_TX 4
224 #define DMA_IIS1_RX 5
225 #define DMA_IIS1_TX 6
226 #define DMA_IIS2_RX 7
227 #define DMA_IIS2_TX 8
228 #define DMA_IIS3_RX 9
229 #define DMA_IIS3_TX 10
230 #define DMA_SPI0_RX 11
231 #define DMA_SPI0_TX 12
232 #define DMA_SPI1_RX 13
233 #define DMA_SPI1_TX 14
234 #define DMA_SPI2_RX 15
235 #define DMA_SPI2_TX 16
236 #define DMA_UART0_RX 17
237 #define DMA_UART0_TX 18
238 #define DMA_UART1_RX 19
239 #define DMA_UART1_TX 20
240 #define DMA_UART2_RX 21
241 #define DMA_UART2_TX 22
242 #define DMA_UART3_RX 23
243 #define DMA_UART3_TX 24
244 #define DMA_UART4_RX 25
245 #define DMA_UART4_TX 26
246 #define DMA_DRM_CPT 27
247 #define DMA_DRM_RAW 28
248 #ifndef CONFIG_SND_SOC_SPRD_AUDIO_USE_AON_DMA
249 #define DMA_VB_DA0 29
250 #define DMA_VB_DA1 30
255 #define DMA_VB_AD0 31
256 #define DMA_VB_AD1 32
257 #define DMA_VB_AD2 33
258 #define DMA_VB_AD3 34
261 #ifdef CONFIG_ARCH_SCX30G
262 #define DMA_SDIO0_RD 36
263 #define DMA_SDIO0_WR 37
264 #define DMA_SDIO1_RD 38
265 #define DMA_SDIO1_WR 39
266 #define DMA_SDIO2_RD 40
267 #define DMA_SDIO2_WR 41
268 #define DMA_EMMC_RD 42
269 #define DMA_EMMC_WR 43
272 #define DMA_IIS_RX DMA_IIS0_RX
273 #define DMA_IIS_TX DMA_IIS0_TX
277 int sprd_dma_check_register(struct dma_chan *c);
278 bool sprd_dma_filter_fn(struct dma_chan *chan, void *filter_param);