drivers/dma/sh/shdmac.c

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * base is drivers/dma/flsdma.c
   5  *
   6  * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   8  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   9  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * - DMA of SuperH does not have Hardware DMA chain mode.
  17  * - MAX DMA size is 16MB.
  18  *
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/notifier.h>
  33 #include <linux/kdebug.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/rculist.h>
  36
  37 #include "../dmaengine.h"
  38 #include "shdma.h"
  39
  40 /* DMA registers */
  41 #define SAR     0x00    /* Source Address Register */
  42 #define DAR     0x04    /* Destination Address Register */
  43 #define TCR     0x08    /* Transfer Count Register */
  44 #define CHCR    0x0C    /* Channel Control Register */
  45 #define DMAOR   0x40    /* DMA Operation Register */
  46
  47 #define TEND    0x18 /* USB-DMAC */
  48
  49 #define SH_DMAE_DRV_NAME "sh-dma-engine"
  50
  51 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
  52 #define LOG2_DEFAULT_XFER_SIZE  2
  53 #define SH_DMA_SLAVE_NUMBER 256
  54 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
  55
  56 /*
  57  * Used for write-side mutual exclusion for the global device list,
  58  * read-side synchronization by way of RCU, and per-controller data.
  59  */
  60 static DEFINE_SPINLOCK(sh_dmae_lock);
  61 static LIST_HEAD(sh_dmae_devices);
  62
  63 /*
  64  * Different DMAC implementations provide different ways to clear DMA channels:
  65  * (1) none - no CHCLR registers are available
  66  * (2) one CHCLR register per channel - 0 has to be written to it to clear
  67  *     channel buffers
  68  * (3) one CHCLR per several channels - 1 has to be written to the bit,
  69  *     corresponding to the specific channel to reset it
  70  */
  71 static void channel_clear(struct sh_dmae_chan *sh_dc)
  72 {
  73         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
  74         const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
  75                 sh_dc->shdma_chan.id;
  76         u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
  77
  78         __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
  79 }
  80
  81 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
  82 {
  83         __raw_writel(data, sh_dc->base + reg);
  84 }
  85
  86 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
  87 {
  88         return __raw_readl(sh_dc->base + reg);
  89 }
  90
  91 static u16 dmaor_read(struct sh_dmae_device *shdev)
  92 {
  93         void __iomem *addr = shdev->chan_reg + DMAOR;
  94
  95         if (shdev->pdata->dmaor_is_32bit)
  96                 return __raw_readl(addr);
  97         else
  98                 return __raw_readw(addr);
  99 }
 100
 101 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
 102 {
 103         void __iomem *addr = shdev->chan_reg + DMAOR;
 104
 105         if (shdev->pdata->dmaor_is_32bit)
 106                 __raw_writel(data, addr);
 107         else
 108                 __raw_writew(data, addr);
 109 }
 110
 111 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
 112 {
 113         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 114
 115         __raw_writel(data, sh_dc->base + shdev->chcr_offset);
 116 }
 117
 118 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
 119 {
 120         struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
 121
 122         return __raw_readl(sh_dc->base + shdev->chcr_offset);
 123 }
 124
 125 /*
 126  * Reset DMA controller
 127  *
 128  * SH7780 has two DMAOR register
 129  */
 130 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
 131 {
 132         unsigned short dmaor;
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&sh_dmae_lock, flags);
 136
 137         dmaor = dmaor_read(shdev);
 138         dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
 139
 140         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 141 }
 142
 143 static int sh_dmae_rst(struct sh_dmae_device *shdev)
 144 {
 145         unsigned short dmaor;
 146         unsigned long flags;
 147
 148         spin_lock_irqsave(&sh_dmae_lock, flags);
 149
 150         dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
 151
 152         if (shdev->pdata->chclr_present) {
 153                 int i;
 154                 for (i = 0; i < shdev->pdata->channel_num; i++) {
 155                         struct sh_dmae_chan *sh_chan = shdev->chan[i];
 156                         if (sh_chan)
 157                                 channel_clear(sh_chan);
 158                 }
 159         }
 160
 161         dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
 162
 163         dmaor = dmaor_read(shdev);
 164
 165         spin_unlock_irqrestore(&sh_dmae_lock, flags);
 166
 167         if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
 168                 dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
 169                 return -EIO;
 170         }
 171         if (shdev->pdata->dmaor_init & ~dmaor)
 172                 dev_warn(shdev->shdma_dev.dma_dev.dev,
 173                          "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
 174                          dmaor, shdev->pdata->dmaor_init);
 175         return 0;
 176 }
 177
 178 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
 179 {
 180         u32 chcr = chcr_read(sh_chan);
 181
 182         if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
 183                 return true; /* working */
 184
 185         return false; /* waiting */
 186 }
 187
 188 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
 189 {
 190         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 191         const struct sh_dmae_pdata *pdata = shdev->pdata;
 192         int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
 193                 ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
 194
 195         if (cnt >= pdata->ts_shift_num)
 196                 cnt = 0;
 197
 198         return pdata->ts_shift[cnt];
 199 }
 200
 201 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
 202 {
 203         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 204         const struct sh_dmae_pdata *pdata = shdev->pdata;
 205         int i;
 206
 207         for (i = 0; i < pdata->ts_shift_num; i++)
 208                 if (pdata->ts_shift[i] == l2size)
 209                         break;
 210
 211         if (i == pdata->ts_shift_num)
 212                 i = 0;
 213
 214         return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
 215                 ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
 216 }
 217
 218 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
 219 {
 220         sh_dmae_writel(sh_chan, hw->sar, SAR);
 221         sh_dmae_writel(sh_chan, hw->dar, DAR);
 222         sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
 223 }
 224
 225 static void dmae_start(struct sh_dmae_chan *sh_chan)
 226 {
 227         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 228         u32 chcr = chcr_read(sh_chan);
 229
 230         if (shdev->pdata->needs_tend_set)
 231                 sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
 232
 233         chcr |= CHCR_DE | shdev->chcr_ie_bit;
 234         chcr_write(sh_chan, chcr & ~CHCR_TE);
 235 }
 236
 237 static void dmae_init(struct sh_dmae_chan *sh_chan)
 238 {
 239         /*
 240          * Default configuration for dual address memory-memory transfer.
 241          */
 242         u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
 243                                                    LOG2_DEFAULT_XFER_SIZE);
 244         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
 245         chcr_write(sh_chan, chcr);
 246 }
 247
 248 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
 249 {
 250         /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
 251         if (dmae_is_busy(sh_chan))
 252                 return -EBUSY;
 253
 254         sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
 255         chcr_write(sh_chan, val);
 256
 257         return 0;
 258 }
 259
 260 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
 261 {
 262         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 263         const struct sh_dmae_pdata *pdata = shdev->pdata;
 264         const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
 265         void __iomem *addr = shdev->dmars;
 266         unsigned int shift = chan_pdata->dmars_bit;
 267
 268         if (dmae_is_busy(sh_chan))
 269                 return -EBUSY;
 270
 271         if (pdata->no_dmars)
 272                 return 0;
 273
 274         /* in the case of a missing DMARS resource use first memory window */
 275         if (!addr)
 276                 addr = shdev->chan_reg;
 277         addr += chan_pdata->dmars;
 278
 279         __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
 280                      addr);
 281
 282         return 0;
 283 }
 284
 285 static void sh_dmae_start_xfer(struct shdma_chan *schan,
 286                                struct shdma_desc *sdesc)
 287 {
 288         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 289                                                     shdma_chan);
 290         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 291                                         struct sh_dmae_desc, shdma_desc);
 292         dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
 293                 sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
 294                 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
 295         /* Get the ld start address from ld_queue */
 296         dmae_set_reg(sh_chan, &sh_desc->hw);
 297         dmae_start(sh_chan);
 298 }
 299
 300 static bool sh_dmae_channel_busy(struct shdma_chan *schan)
 301 {
 302         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 303                                                     shdma_chan);
 304         return dmae_is_busy(sh_chan);
 305 }
 306
 307 static void sh_dmae_setup_xfer(struct shdma_chan *schan,
 308                                int slave_id)
 309 {
 310         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 311                                                     shdma_chan);
 312
 313         if (slave_id >= 0) {
 314                 const struct sh_dmae_slave_config *cfg =
 315                         sh_chan->config;
 316
 317                 dmae_set_dmars(sh_chan, cfg->mid_rid);
 318                 dmae_set_chcr(sh_chan, cfg->chcr);
 319         } else {
 320                 dmae_init(sh_chan);
 321         }
 322 }
 323
 324 /*
 325  * Find a slave channel configuration from the contoller list by either a slave
 326  * ID in the non-DT case, or by a MID/RID value in the DT case
 327  */
 328 static const struct sh_dmae_slave_config *dmae_find_slave(
 329         struct sh_dmae_chan *sh_chan, int match)
 330 {
 331         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 332         const struct sh_dmae_pdata *pdata = shdev->pdata;
 333         const struct sh_dmae_slave_config *cfg;
 334         int i;
 335
 336         if (!sh_chan->shdma_chan.dev->of_node) {
 337                 if (match >= SH_DMA_SLAVE_NUMBER)
 338                         return NULL;
 339
 340                 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
 341                         if (cfg->slave_id == match)
 342                                 return cfg;
 343         } else {
 344                 for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
 345                         if (cfg->mid_rid == match) {
 346                                 sh_chan->shdma_chan.slave_id = i;
 347                                 return cfg;
 348                         }
 349         }
 350
 351         return NULL;
 352 }
 353
 354 static int sh_dmae_set_slave(struct shdma_chan *schan,
 355                              int slave_id, dma_addr_t slave_addr, bool try)
 356 {
 357         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 358                                                     shdma_chan);
 359         const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
 360         if (!cfg)
 361                 return -ENXIO;
 362
 363         if (!try) {
 364                 sh_chan->config = cfg;
 365                 sh_chan->slave_addr = slave_addr ? : cfg->addr;
 366         }
 367
 368         return 0;
 369 }
 370
 371 static void dmae_halt(struct sh_dmae_chan *sh_chan)
 372 {
 373         struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
 374         u32 chcr = chcr_read(sh_chan);
 375
 376         chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
 377         chcr_write(sh_chan, chcr);
 378 }
 379
 380 static int sh_dmae_desc_setup(struct shdma_chan *schan,
 381                               struct shdma_desc *sdesc,
 382                               dma_addr_t src, dma_addr_t dst, size_t *len)
 383 {
 384         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 385                                         struct sh_dmae_desc, shdma_desc);
 386
 387         if (*len > schan->max_xfer_len)
 388                 *len = schan->max_xfer_len;
 389
 390         sh_desc->hw.sar = src;
 391         sh_desc->hw.dar = dst;
 392         sh_desc->hw.tcr = *len;
 393
 394         return 0;
 395 }
 396
 397 static void sh_dmae_halt(struct shdma_chan *schan)
 398 {
 399         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 400                                                     shdma_chan);
 401         dmae_halt(sh_chan);
 402 }
 403
 404 static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
 405 {
 406         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 407                                                     shdma_chan);
 408
 409         if (!(chcr_read(sh_chan) & CHCR_TE))
 410                 return false;
 411
 412         /* DMA stop */
 413         dmae_halt(sh_chan);
 414
 415         return true;
 416 }
 417
 418 static size_t sh_dmae_get_partial(struct shdma_chan *schan,
 419                                   struct shdma_desc *sdesc)
 420 {
 421         struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
 422                                                     shdma_chan);
 423         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 424                                         struct sh_dmae_desc, shdma_desc);
 425         return sh_desc->hw.tcr -
 426                 (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
 427 }
 428
 429 /* Called from error IRQ or NMI */
 430 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
 431 {
 432         bool ret;
 433
 434         /* halt the dma controller */
 435         sh_dmae_ctl_stop(shdev);
 436
 437         /* We cannot detect, which channel caused the error, have to reset all */
 438         ret = shdma_reset(&shdev->shdma_dev);
 439
 440         sh_dmae_rst(shdev);
 441
 442         return ret;
 443 }
 444
 445 static irqreturn_t sh_dmae_err(int irq, void *data)
 446 {
 447         struct sh_dmae_device *shdev = data;
 448
 449         if (!(dmaor_read(shdev) & DMAOR_AE))
 450                 return IRQ_NONE;
 451
 452         sh_dmae_reset(shdev);
 453         return IRQ_HANDLED;
 454 }
 455
 456 static bool sh_dmae_desc_completed(struct shdma_chan *schan,
 457                                    struct shdma_desc *sdesc)
 458 {
 459         struct sh_dmae_chan *sh_chan = container_of(schan,
 460                                         struct sh_dmae_chan, shdma_chan);
 461         struct sh_dmae_desc *sh_desc = container_of(sdesc,
 462                                         struct sh_dmae_desc, shdma_desc);
 463         u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
 464         u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
 465
 466         return  (sdesc->direction == DMA_DEV_TO_MEM &&
 467                  (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
 468                 (sdesc->direction != DMA_DEV_TO_MEM &&
 469                  (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
 470 }
 471
 472 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
 473 {
 474         /* Fast path out if NMIF is not asserted for this controller */
 475         if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
 476                 return false;
 477
 478         return sh_dmae_reset(shdev);
 479 }
 480
 481 static int sh_dmae_nmi_handler(struct notifier_block *self,
 482                                unsigned long cmd, void *data)
 483 {
 484         struct sh_dmae_device *shdev;
 485         int ret = NOTIFY_DONE;
 486         bool triggered;
 487
 488         /*
 489          * Only concern ourselves with NMI events.
 490          *
 491          * Normally we would check the die chain value, but as this needs
 492          * to be architecture independent, check for NMI context instead.
 493          */
 494         if (!in_nmi())
 495                 return NOTIFY_DONE;
 496
 497         rcu_read_lock();
 498         list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
 499                 /*
 500                  * Only stop if one of the controllers has NMIF asserted,
 501                  * we do not want to interfere with regular address error
 502                  * handling or NMI events that don't concern the DMACs.
 503                  */
 504                 triggered = sh_dmae_nmi_notify(shdev);
 505                 if (triggered == true)
 506                         ret = NOTIFY_OK;
 507         }
 508         rcu_read_unlock();
 509
 510         return ret;
 511 }
 512
 513 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
 514         .notifier_call  = sh_dmae_nmi_handler,
 515
 516         /* Run before NMI debug handler and KGDB */
 517         .priority       = 1,
 518 };
 519
 520 static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
 521                                         int irq, unsigned long flags)
 522 {
 523         const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
 524         struct shdma_dev *sdev = &shdev->shdma_dev;
 525         struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
 526         struct sh_dmae_chan *sh_chan;
 527         struct shdma_chan *schan;
 528         int err;
 529
 530         sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
 531                                GFP_KERNEL);
 532         if (!sh_chan) {
 533                 dev_err(sdev->dma_dev.dev,
 534                         "No free memory for allocating dma channels!\n");
 535                 return -ENOMEM;
 536         }
 537
 538         schan = &sh_chan->shdma_chan;
 539         schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
 540
 541         shdma_chan_probe(sdev, schan, id);
 542
 543         sh_chan->base = shdev->chan_reg + chan_pdata->offset;
 544
 545         /* set up channel irq */
 546         if (pdev->id >= 0)
 547                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 548                          "sh-dmae%d.%d", pdev->id, id);
 549         else
 550                 snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
 551                          "sh-dma%d", id);
 552
 553         err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
 554         if (err) {
 555                 dev_err(sdev->dma_dev.dev,
 556                         "DMA channel %d request_irq error %d\n",
 557                         id, err);
 558                 goto err_no_irq;
 559         }
 560
 561         shdev->chan[id] = sh_chan;
 562         return 0;
 563
 564 err_no_irq:
 565         /* remove from dmaengine device node */
 566         shdma_chan_remove(schan);
 567         return err;
 568 }
 569
 570 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
 571 {
 572         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 573         struct shdma_chan *schan;
 574         int i;
 575
 576         shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
 577                 BUG_ON(!schan);
 578
 579                 shdma_chan_remove(schan);
 580         }
 581         dma_dev->chancnt = 0;
 582 }
 583
 584 static void sh_dmae_shutdown(struct platform_device *pdev)
 585 {
 586         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 587         sh_dmae_ctl_stop(shdev);
 588 }
 589
 590 static int sh_dmae_runtime_suspend(struct device *dev)
 591 {
 592         return 0;
 593 }
 594
 595 static int sh_dmae_runtime_resume(struct device *dev)
 596 {
 597         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 598
 599         return sh_dmae_rst(shdev);
 600 }
 601
 602 #ifdef CONFIG_PM
 603 static int sh_dmae_suspend(struct device *dev)
 604 {
 605         return 0;
 606 }
 607
 608 static int sh_dmae_resume(struct device *dev)
 609 {
 610         struct sh_dmae_device *shdev = dev_get_drvdata(dev);
 611         int i, ret;
 612
 613         ret = sh_dmae_rst(shdev);
 614         if (ret < 0)
 615                 dev_err(dev, "Failed to reset!\n");
 616
 617         for (i = 0; i < shdev->pdata->channel_num; i++) {
 618                 struct sh_dmae_chan *sh_chan = shdev->chan[i];
 619
 620                 if (!sh_chan->shdma_chan.desc_num)
 621                         continue;
 622
 623                 if (sh_chan->shdma_chan.slave_id >= 0) {
 624                         const struct sh_dmae_slave_config *cfg = sh_chan->config;
 625                         dmae_set_dmars(sh_chan, cfg->mid_rid);
 626                         dmae_set_chcr(sh_chan, cfg->chcr);
 627                 } else {
 628                         dmae_init(sh_chan);
 629                 }
 630         }
 631
 632         return 0;
 633 }
 634 #else
 635 #define sh_dmae_suspend NULL
 636 #define sh_dmae_resume NULL
 637 #endif
 638
 639 const struct dev_pm_ops sh_dmae_pm = {
 640         .suspend                = sh_dmae_suspend,
 641         .resume                 = sh_dmae_resume,
 642         .runtime_suspend        = sh_dmae_runtime_suspend,
 643         .runtime_resume         = sh_dmae_runtime_resume,
 644 };
 645
 646 static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
 647 {
 648         struct sh_dmae_chan *sh_chan = container_of(schan,
 649                                         struct sh_dmae_chan, shdma_chan);
 650
 651         /*
 652          * Implicit BUG_ON(!sh_chan->config)
 653          * This is an exclusive slave DMA operation, may only be called after a
 654          * successful slave configuration.
 655          */
 656         return sh_chan->slave_addr;
 657 }
 658
 659 static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
 660 {
 661         return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
 662 }
 663
 664 static const struct shdma_ops sh_dmae_shdma_ops = {
 665         .desc_completed = sh_dmae_desc_completed,
 666         .halt_channel = sh_dmae_halt,
 667         .channel_busy = sh_dmae_channel_busy,
 668         .slave_addr = sh_dmae_slave_addr,
 669         .desc_setup = sh_dmae_desc_setup,
 670         .set_slave = sh_dmae_set_slave,
 671         .setup_xfer = sh_dmae_setup_xfer,
 672         .start_xfer = sh_dmae_start_xfer,
 673         .embedded_desc = sh_dmae_embedded_desc,
 674         .chan_irq = sh_dmae_chan_irq,
 675         .get_partial = sh_dmae_get_partial,
 676 };
 677
 678 static const struct of_device_id sh_dmae_of_match[] = {
 679         {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
 680         {}
 681 };
 682 MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
 683
 684 static int sh_dmae_probe(struct platform_device *pdev)
 685 {
 686         const struct sh_dmae_pdata *pdata;
 687         unsigned long irqflags = 0,
 688                 chan_flag[SH_DMAE_MAX_CHANNELS] = {};
 689         int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
 690         int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
 691         struct sh_dmae_device *shdev;
 692         struct dma_device *dma_dev;
 693         struct resource *chan, *dmars, *errirq_res, *chanirq_res;
 694
 695         if (pdev->dev.of_node)
 696                 pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
 697         else
 698                 pdata = dev_get_platdata(&pdev->dev);
 699
 700         /* get platform data */
 701         if (!pdata || !pdata->channel_num)
 702                 return -ENODEV;
 703
 704         chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 705         /* DMARS area is optional */
 706         dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 707         /*
 708          * IRQ resources:
 709          * 1. there always must be at least one IRQ IO-resource. On SH4 it is
 710          *    the error IRQ, in which case it is the only IRQ in this resource:
 711          *    start == end. If it is the only IRQ resource, all channels also
 712          *    use the same IRQ.
 713          * 2. DMA channel IRQ resources can be specified one per resource or in
 714          *    ranges (start != end)
 715          * 3. iff all events (channels and, optionally, error) on this
 716          *    controller use the same IRQ, only one IRQ resource can be
 717          *    specified, otherwise there must be one IRQ per channel, even if
 718          *    some of them are equal
 719          * 4. if all IRQs on this controller are equal or if some specific IRQs
 720          *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
 721          *    requested with the IRQF_SHARED flag
 722          */
 723         errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 724         if (!chan || !errirq_res)
 725                 return -ENODEV;
 726
 727         shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
 728                              GFP_KERNEL);
 729         if (!shdev) {
 730                 dev_err(&pdev->dev, "Not enough memory\n");
 731                 return -ENOMEM;
 732         }
 733
 734         dma_dev = &shdev->shdma_dev.dma_dev;
 735
 736         shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
 737         if (IS_ERR(shdev->chan_reg))
 738                 return PTR_ERR(shdev->chan_reg);
 739         if (dmars) {
 740                 shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
 741                 if (IS_ERR(shdev->dmars))
 742                         return PTR_ERR(shdev->dmars);
 743         }
 744
 745         if (!pdata->slave_only)
 746                 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
 747         if (pdata->slave && pdata->slave_num)
 748                 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
 749
 750         /* Default transfer size of 32 bytes requires 32-byte alignment */
 751         dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
 752
 753         shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
 754         shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
 755         err = shdma_init(&pdev->dev, &shdev->shdma_dev,
 756                               pdata->channel_num);
 757         if (err < 0)
 758                 goto eshdma;
 759
 760         /* platform data */
 761         shdev->pdata = pdata;
 762
 763         if (pdata->chcr_offset)
 764                 shdev->chcr_offset = pdata->chcr_offset;
 765         else
 766                 shdev->chcr_offset = CHCR;
 767
 768         if (pdata->chcr_ie_bit)
 769                 shdev->chcr_ie_bit = pdata->chcr_ie_bit;
 770         else
 771                 shdev->chcr_ie_bit = CHCR_IE;
 772
 773         platform_set_drvdata(pdev, shdev);
 774
 775         pm_runtime_enable(&pdev->dev);
 776         err = pm_runtime_get_sync(&pdev->dev);
 777         if (err < 0)
 778                 dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
 779
 780         spin_lock_irq(&sh_dmae_lock);
 781         list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
 782         spin_unlock_irq(&sh_dmae_lock);
 783
 784         /* reset dma controller - only needed as a test */
 785         err = sh_dmae_rst(shdev);
 786         if (err)
 787                 goto rst_err;
 788
 789 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 790         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 791
 792         if (!chanirq_res)
 793                 chanirq_res = errirq_res;
 794         else
 795                 irqres++;
 796
 797         if (chanirq_res == errirq_res ||
 798             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
 799                 irqflags = IRQF_SHARED;
 800
 801         errirq = errirq_res->start;
 802
 803         err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags,
 804                                "DMAC Address Error", shdev);
 805         if (err) {
 806                 dev_err(&pdev->dev,
 807                         "DMA failed requesting irq #%d, error %d\n",
 808                         errirq, err);
 809                 goto eirq_err;
 810         }
 811
 812 #else
 813         chanirq_res = errirq_res;
 814 #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */
 815
 816         if (chanirq_res->start == chanirq_res->end &&
 817             !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
 818                 /* Special case - all multiplexed */
 819                 for (; irq_cnt < pdata->channel_num; irq_cnt++) {
 820                         if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
 821                                 chan_irq[irq_cnt] = chanirq_res->start;
 822                                 chan_flag[irq_cnt] = IRQF_SHARED;
 823                         } else {
 824                                 irq_cap = 1;
 825                                 break;
 826                         }
 827                 }
 828         } else {
 829                 do {
 830                         for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
 831                                 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
 832                                         irq_cap = 1;
 833                                         break;
 834                                 }
 835
 836                                 if ((errirq_res->flags & IORESOURCE_BITS) ==
 837                                     IORESOURCE_IRQ_SHAREABLE)
 838                                         chan_flag[irq_cnt] = IRQF_SHARED;
 839                                 else
 840                                         chan_flag[irq_cnt] = 0;
 841                                 dev_dbg(&pdev->dev,
 842                                         "Found IRQ %d for channel %d\n",
 843                                         i, irq_cnt);
 844                                 chan_irq[irq_cnt++] = i;
 845                         }
 846
 847                         if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
 848                                 break;
 849
 850                         chanirq_res = platform_get_resource(pdev,
 851                                                 IORESOURCE_IRQ, ++irqres);
 852                 } while (irq_cnt < pdata->channel_num && chanirq_res);
 853         }
 854
 855         /* Create DMA Channel */
 856         for (i = 0; i < irq_cnt; i++) {
 857                 err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
 858                 if (err)
 859                         goto chan_probe_err;
 860         }
 861
 862         if (irq_cap)
 863                 dev_notice(&pdev->dev, "Attempting to register %d DMA "
 864                            "channels when a maximum of %d are supported.\n",
 865                            pdata->channel_num, SH_DMAE_MAX_CHANNELS);
 866
 867         pm_runtime_put(&pdev->dev);
 868
 869         err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
 870         if (err < 0)
 871                 goto edmadevreg;
 872
 873         return err;
 874
 875 edmadevreg:
 876         pm_runtime_get(&pdev->dev);
 877
 878 chan_probe_err:
 879         sh_dmae_chan_remove(shdev);
 880
 881 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 882 eirq_err:
 883 #endif
 884 rst_err:
 885         spin_lock_irq(&sh_dmae_lock);
 886         list_del_rcu(&shdev->node);
 887         spin_unlock_irq(&sh_dmae_lock);
 888
 889         pm_runtime_put(&pdev->dev);
 890         pm_runtime_disable(&pdev->dev);
 891
 892         shdma_cleanup(&shdev->shdma_dev);
 893 eshdma:
 894         synchronize_rcu();
 895
 896         return err;
 897 }
 898
 899 static int sh_dmae_remove(struct platform_device *pdev)
 900 {
 901         struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
 902         struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
 903
 904         dma_async_device_unregister(dma_dev);
 905
 906         spin_lock_irq(&sh_dmae_lock);
 907         list_del_rcu(&shdev->node);
 908         spin_unlock_irq(&sh_dmae_lock);
 909
 910         pm_runtime_disable(&pdev->dev);
 911
 912         sh_dmae_chan_remove(shdev);
 913         shdma_cleanup(&shdev->shdma_dev);
 914
 915         synchronize_rcu();
 916
 917         return 0;
 918 }
 919
 920 static struct platform_driver sh_dmae_driver = {
 921         .driver         = {
 922                 .owner  = THIS_MODULE,
 923                 .pm     = &sh_dmae_pm,
 924                 .name   = SH_DMAE_DRV_NAME,
 925                 .of_match_table = sh_dmae_of_match,
 926         },
 927         .remove         = sh_dmae_remove,
 928         .shutdown       = sh_dmae_shutdown,
 929 };
 930
 931 static int __init sh_dmae_init(void)
 932 {
 933         /* Wire up NMI handling */
 934         int err = register_die_notifier(&sh_dmae_nmi_notifier);
 935         if (err)
 936                 return err;
 937
 938         return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
 939 }
 940 module_init(sh_dmae_init);
 941
 942 static void __exit sh_dmae_exit(void)
 943 {
 944         platform_driver_unregister(&sh_dmae_driver);
 945
 946         unregister_die_notifier(&sh_dmae_nmi_notifier);
 947 }
 948 module_exit(sh_dmae_exit);
 949
 950 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
 951 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
 952 MODULE_LICENSE("GPL");
 953 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);