drivers/dma/qcom/hidma.h

   1 /*
   2  * Qualcomm Technologies HIDMA data structures
   3  *
   4  * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef QCOM_HIDMA_H
  17 #define QCOM_HIDMA_H
  18
  19 #include <linux/kfifo.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/dmaengine.h>
  22
  23 #define HIDMA_TRE_SIZE                  32 /* each TRE is 32 bytes  */
  24 #define HIDMA_TRE_CFG_IDX               0
  25 #define HIDMA_TRE_LEN_IDX               1
  26 #define HIDMA_TRE_SRC_LOW_IDX           2
  27 #define HIDMA_TRE_SRC_HI_IDX            3
  28 #define HIDMA_TRE_DEST_LOW_IDX          4
  29 #define HIDMA_TRE_DEST_HI_IDX           5
  30
  31 struct hidma_tre {
  32         atomic_t allocated;             /* if this channel is allocated     */
  33         bool queued;                    /* flag whether this is pending     */
  34         u16 status;                     /* status                           */
  35         u32 idx;                        /* index of the tre                 */
  36         u32 dma_sig;                    /* signature of the tre             */
  37         const char *dev_name;           /* name of the device               */
  38         void (*callback)(void *data);   /* requester callback               */
  39         void *data;                     /* Data associated with this channel*/
  40         struct hidma_lldev *lldev;      /* lldma device pointer             */
  41         u32 tre_local[HIDMA_TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy  */
  42         u32 tre_index;                  /* the offset where this was written*/
  43         u32 int_flags;                  /* interrupt flags                  */
  44         u8 err_info;                    /* error record in this transfer    */
  45         u8 err_code;                    /* completion code                  */
  46 };
  47
  48 struct hidma_lldev {
  49         bool initialized;               /* initialized flag               */
  50         u8 trch_state;                  /* trch_state of the device       */
  51         u8 evch_state;                  /* evch_state of the device       */
  52         u8 chidx;                       /* channel index in the core      */
  53         u32 nr_tres;                    /* max number of configs          */
  54         spinlock_t lock;                /* reentrancy                     */
  55         struct hidma_tre *trepool;      /* trepool of user configs */
  56         struct device *dev;             /* device                         */
  57         void __iomem *trca;             /* Transfer Channel address       */
  58         void __iomem *evca;             /* Event Channel address          */
  59         struct hidma_tre
  60                 **pending_tre_list;     /* Pointers to pending TREs       */
  61         s32 pending_tre_count;          /* Number of TREs pending         */
  62
  63         void *tre_ring;                 /* TRE ring                       */
  64         dma_addr_t tre_dma;             /* TRE ring to be shared with HW  */
  65         u32 tre_ring_size;              /* Byte size of the ring          */
  66         u32 tre_processed_off;          /* last processed TRE             */
  67
  68         void *evre_ring;                /* EVRE ring                       */
  69         dma_addr_t evre_dma;            /* EVRE ring to be shared with HW  */
  70         u32 evre_ring_size;             /* Byte size of the ring           */
  71         u32 evre_processed_off;         /* last processed EVRE             */
  72
  73         u32 tre_write_offset;           /* TRE write location              */
  74         struct tasklet_struct task;     /* task delivering notifications   */
  75         DECLARE_KFIFO_PTR(handoff_fifo,
  76                 struct hidma_tre *);    /* pending TREs FIFO               */
  77 };
  78
  79 struct hidma_desc {
  80         struct dma_async_tx_descriptor  desc;
  81         /* link list node for this channel*/
  82         struct list_head                node;
  83         u32                             tre_ch;
  84 };
  85
  86 struct hidma_chan {
  87         bool                            paused;
  88         bool                            allocated;
  89         char                            dbg_name[16];
  90         u32                             dma_sig;
  91         dma_cookie_t                    last_success;
  92
  93         /*
  94          * active descriptor on this channel
  95          * It is used by the DMA complete notification to
  96          * locate the descriptor that initiated the transfer.
  97          */
  98         struct dentry                   *debugfs;
  99         struct dentry                   *stats;
 100         struct hidma_dev                *dmadev;
 101         struct hidma_desc               *running;
 102
 103         struct dma_chan                 chan;
 104         struct list_head                free;
 105         struct list_head                prepared;
 106         struct list_head                active;
 107         struct list_head                completed;
 108
 109         /* Lock for this structure */
 110         spinlock_t                      lock;
 111 };
 112
 113 struct hidma_dev {
 114         int                             irq;
 115         int                             chidx;
 116         u32                             nr_descriptors;
 117
 118         struct hidma_lldev              *lldev;
 119         void                            __iomem *dev_trca;
 120         struct resource                 *trca_resource;
 121         void                            __iomem *dev_evca;
 122         struct resource                 *evca_resource;
 123
 124         /* used to protect the pending channel list*/
 125         spinlock_t                      lock;
 126         struct dma_device               ddev;
 127
 128         struct dentry                   *debugfs;
 129         struct dentry                   *stats;
 130
 131         /* Task delivering issue_pending */
 132         struct tasklet_struct           task;
 133 };
 134
 135 int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id,
 136                         const char *dev_name,
 137                         void (*callback)(void *data), void *data, u32 *tre_ch);
 138
 139 void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch);
 140 enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch);
 141 bool hidma_ll_isenabled(struct hidma_lldev *llhndl);
 142 void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch);
 143 void hidma_ll_start(struct hidma_lldev *llhndl);
 144 int hidma_ll_disable(struct hidma_lldev *lldev);
 145 int hidma_ll_enable(struct hidma_lldev *llhndl);
 146 void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch,
 147         dma_addr_t src, dma_addr_t dest, u32 len, u32 flags);
 148 int hidma_ll_setup(struct hidma_lldev *lldev);
 149 struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
 150                         void __iomem *trca, void __iomem *evca,
 151                         u8 chidx);
 152 int hidma_ll_uninit(struct hidma_lldev *llhndl);
 153 irqreturn_t hidma_ll_inthandler(int irq, void *arg);
 154 void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
 155                                 u8 err_code);
 156 int hidma_debug_init(struct hidma_dev *dmadev);
 157 void hidma_debug_uninit(struct hidma_dev *dmadev);
 158 #endif