drivers/dma/mv_xor.c

   1 /*
   2  * offload engine driver for the Marvell XOR engine
   3  * Copyright (C) 2007, 2008, Marvell International Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/memory.h>
  28 #include <linux/clk.h>
  29 #include <linux/of.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/irqdomain.h>
  32 #include <linux/platform_data/dma-mv_xor.h>
  33
  34 #include "dmaengine.h"
  35 #include "mv_xor.h"
  36
  37 static void mv_xor_issue_pending(struct dma_chan *chan);
  38
  39 #define to_mv_xor_chan(chan)            \
  40         container_of(chan, struct mv_xor_chan, dmachan)
  41
  42 #define to_mv_xor_slot(tx)              \
  43         container_of(tx, struct mv_xor_desc_slot, async_tx)
  44
  45 #define mv_chan_to_devp(chan)           \
  46         ((chan)->dmadev.dev)
  47
  48 static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags)
  49 {
  50         struct mv_xor_desc *hw_desc = desc->hw_desc;
  51
  52         hw_desc->status = (1 << 31);
  53         hw_desc->phy_next_desc = 0;
  54         hw_desc->desc_command = (1 << 31);
  55 }
  56
  57 static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc,
  58                                    u32 byte_count)
  59 {
  60         struct mv_xor_desc *hw_desc = desc->hw_desc;
  61         hw_desc->byte_count = byte_count;
  62 }
  63
  64 static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
  65                                   u32 next_desc_addr)
  66 {
  67         struct mv_xor_desc *hw_desc = desc->hw_desc;
  68         BUG_ON(hw_desc->phy_next_desc);
  69         hw_desc->phy_next_desc = next_desc_addr;
  70 }
  71
  72 static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc)
  73 {
  74         struct mv_xor_desc *hw_desc = desc->hw_desc;
  75         hw_desc->phy_next_desc = 0;
  76 }
  77
  78 static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc,
  79                                   dma_addr_t addr)
  80 {
  81         struct mv_xor_desc *hw_desc = desc->hw_desc;
  82         hw_desc->phy_dest_addr = addr;
  83 }
  84
  85 static int mv_chan_memset_slot_count(size_t len)
  86 {
  87         return 1;
  88 }
  89
  90 #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c)
  91
  92 static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
  93                                  int index, dma_addr_t addr)
  94 {
  95         struct mv_xor_desc *hw_desc = desc->hw_desc;
  96         hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
  97         if (desc->type == DMA_XOR)
  98                 hw_desc->desc_command |= (1 << index);
  99 }
 100
 101 static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
 102 {
 103         return readl_relaxed(XOR_CURR_DESC(chan));
 104 }
 105
 106 static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
 107                                         u32 next_desc_addr)
 108 {
 109         writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
 110 }
 111
 112 static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
 113 {
 114         u32 val = readl_relaxed(XOR_INTR_MASK(chan));
 115         val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
 116         writel_relaxed(val, XOR_INTR_MASK(chan));
 117 }
 118
 119 static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
 120 {
 121         u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
 122         intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
 123         return intr_cause;
 124 }
 125
 126 static int mv_is_err_intr(u32 intr_cause)
 127 {
 128         if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)))
 129                 return 1;
 130
 131         return 0;
 132 }
 133
 134 static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan)
 135 {
 136         u32 val = ~(1 << (chan->idx * 16));
 137         dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
 138         writel_relaxed(val, XOR_INTR_CAUSE(chan));
 139 }
 140
 141 static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan)
 142 {
 143         u32 val = 0xFFFF0000 >> (chan->idx * 16);
 144         writel_relaxed(val, XOR_INTR_CAUSE(chan));
 145 }
 146
 147 static int mv_can_chain(struct mv_xor_desc_slot *desc)
 148 {
 149         struct mv_xor_desc_slot *chain_old_tail = list_entry(
 150                 desc->chain_node.prev, struct mv_xor_desc_slot, chain_node);
 151
 152         if (chain_old_tail->type != desc->type)
 153                 return 0;
 154
 155         return 1;
 156 }
 157
 158 static void mv_set_mode(struct mv_xor_chan *chan,
 159                                enum dma_transaction_type type)
 160 {
 161         u32 op_mode;
 162         u32 config = readl_relaxed(XOR_CONFIG(chan));
 163
 164         switch (type) {
 165         case DMA_XOR:
 166                 op_mode = XOR_OPERATION_MODE_XOR;
 167                 break;
 168         case DMA_MEMCPY:
 169                 op_mode = XOR_OPERATION_MODE_MEMCPY;
 170                 break;
 171         default:
 172                 dev_err(mv_chan_to_devp(chan),
 173                         "error: unsupported operation %d\n",
 174                         type);
 175                 BUG();
 176                 return;
 177         }
 178
 179         config &= ~0x7;
 180         config |= op_mode;
 181
 182 #if defined(__BIG_ENDIAN)
 183         config |= XOR_DESCRIPTOR_SWAP;
 184 #else
 185         config &= ~XOR_DESCRIPTOR_SWAP;
 186 #endif
 187
 188         writel_relaxed(config, XOR_CONFIG(chan));
 189         chan->current_type = type;
 190 }
 191
 192 static void mv_chan_activate(struct mv_xor_chan *chan)
 193 {
 194         u32 activation;
 195
 196         dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
 197         activation = readl_relaxed(XOR_ACTIVATION(chan));
 198         activation |= 0x1;
 199         writel_relaxed(activation, XOR_ACTIVATION(chan));
 200 }
 201
 202 static char mv_chan_is_busy(struct mv_xor_chan *chan)
 203 {
 204         u32 state = readl_relaxed(XOR_ACTIVATION(chan));
 205
 206         state = (state >> 4) & 0x3;
 207
 208         return (state == 1) ? 1 : 0;
 209 }
 210
 211 static int mv_chan_xor_slot_count(size_t len, int src_cnt)
 212 {
 213         return 1;
 214 }
 215
 216 /**
 217  * mv_xor_free_slots - flags descriptor slots for reuse
 218  * @slot: Slot to free
 219  * Caller must hold &mv_chan->lock while calling this function
 220  */
 221 static void mv_xor_free_slots(struct mv_xor_chan *mv_chan,
 222                               struct mv_xor_desc_slot *slot)
 223 {
 224         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n",
 225                 __func__, __LINE__, slot);
 226
 227         slot->slots_per_op = 0;
 228
 229 }
 230
 231 /*
 232  * mv_xor_start_new_chain - program the engine to operate on new chain headed by
 233  * sw_desc
 234  * Caller must hold &mv_chan->lock while calling this function
 235  */
 236 static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan,
 237                                    struct mv_xor_desc_slot *sw_desc)
 238 {
 239         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
 240                 __func__, __LINE__, sw_desc);
 241         if (sw_desc->type != mv_chan->current_type)
 242                 mv_set_mode(mv_chan, sw_desc->type);
 243
 244         /* set the hardware chain */
 245         mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
 246
 247         mv_chan->pending += sw_desc->slot_cnt;
 248         mv_xor_issue_pending(&mv_chan->dmachan);
 249 }
 250
 251 static dma_cookie_t
 252 mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
 253         struct mv_xor_chan *mv_chan, dma_cookie_t cookie)
 254 {
 255         BUG_ON(desc->async_tx.cookie < 0);
 256
 257         if (desc->async_tx.cookie > 0) {
 258                 cookie = desc->async_tx.cookie;
 259
 260                 /* call the callback (must not sleep or submit new
 261                  * operations to this channel)
 262                  */
 263                 if (desc->async_tx.callback)
 264                         desc->async_tx.callback(
 265                                 desc->async_tx.callback_param);
 266
 267                 dma_descriptor_unmap(&desc->async_tx);
 268                 if (desc->group_head)
 269                         desc->group_head = NULL;
 270         }
 271
 272         /* run dependent operations */
 273         dma_run_dependencies(&desc->async_tx);
 274
 275         return cookie;
 276 }
 277
 278 static int
 279 mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan)
 280 {
 281         struct mv_xor_desc_slot *iter, *_iter;
 282
 283         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
 284         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 285                                  completed_node) {
 286
 287                 if (async_tx_test_ack(&iter->async_tx)) {
 288                         list_del(&iter->completed_node);
 289                         mv_xor_free_slots(mv_chan, iter);
 290                 }
 291         }
 292         return 0;
 293 }
 294
 295 static int
 296 mv_xor_clean_slot(struct mv_xor_desc_slot *desc,
 297         struct mv_xor_chan *mv_chan)
 298 {
 299         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
 300                 __func__, __LINE__, desc, desc->async_tx.flags);
 301         list_del(&desc->chain_node);
 302         /* the client is allowed to attach dependent operations
 303          * until 'ack' is set
 304          */
 305         if (!async_tx_test_ack(&desc->async_tx)) {
 306                 /* move this slot to the completed_slots */
 307                 list_add_tail(&desc->completed_node, &mv_chan->completed_slots);
 308                 return 0;
 309         }
 310
 311         mv_xor_free_slots(mv_chan, desc);
 312         return 0;
 313 }
 314
 315 static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 316 {
 317         struct mv_xor_desc_slot *iter, *_iter;
 318         dma_cookie_t cookie = 0;
 319         int busy = mv_chan_is_busy(mv_chan);
 320         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 321         int seen_current = 0;
 322
 323         dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
 324         dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
 325         mv_xor_clean_completed_slots(mv_chan);
 326
 327         /* free completed slots from the chain starting with
 328          * the oldest descriptor
 329          */
 330
 331         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 332                                         chain_node) {
 333                 prefetch(_iter);
 334                 prefetch(&_iter->async_tx);
 335
 336                 /* do not advance past the current descriptor loaded into the
 337                  * hardware channel, subsequent descriptors are either in
 338                  * process or have not been submitted
 339                  */
 340                 if (seen_current)
 341                         break;
 342
 343                 /* stop the search if we reach the current descriptor and the
 344                  * channel is busy
 345                  */
 346                 if (iter->async_tx.phys == current_desc) {
 347                         seen_current = 1;
 348                         if (busy)
 349                                 break;
 350                 }
 351
 352                 cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie);
 353
 354                 if (mv_xor_clean_slot(iter, mv_chan))
 355                         break;
 356         }
 357
 358         if ((busy == 0) && !list_empty(&mv_chan->chain)) {
 359                 struct mv_xor_desc_slot *chain_head;
 360                 chain_head = list_entry(mv_chan->chain.next,
 361                                         struct mv_xor_desc_slot,
 362                                         chain_node);
 363
 364                 mv_xor_start_new_chain(mv_chan, chain_head);
 365         }
 366
 367         if (cookie > 0)
 368                 mv_chan->dmachan.completed_cookie = cookie;
 369 }
 370
 371 static void
 372 mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan)
 373 {
 374         spin_lock_bh(&mv_chan->lock);
 375         __mv_xor_slot_cleanup(mv_chan);
 376         spin_unlock_bh(&mv_chan->lock);
 377 }
 378
 379 static void mv_xor_tasklet(unsigned long data)
 380 {
 381         struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
 382         mv_xor_slot_cleanup(chan);
 383 }
 384
 385 static struct mv_xor_desc_slot *
 386 mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots,
 387                     int slots_per_op)
 388 {
 389         struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL;
 390         LIST_HEAD(chain);
 391         int slots_found, retry = 0;
 392
 393         /* start search from the last allocated descrtiptor
 394          * if a contiguous allocation can not be found start searching
 395          * from the beginning of the list
 396          */
 397 retry:
 398         slots_found = 0;
 399         if (retry == 0)
 400                 iter = mv_chan->last_used;
 401         else
 402                 iter = list_entry(&mv_chan->all_slots,
 403                         struct mv_xor_desc_slot,
 404                         slot_node);
 405
 406         list_for_each_entry_safe_continue(
 407                 iter, _iter, &mv_chan->all_slots, slot_node) {
 408                 prefetch(_iter);
 409                 prefetch(&_iter->async_tx);
 410                 if (iter->slots_per_op) {
 411                         /* give up after finding the first busy slot
 412                          * on the second pass through the list
 413                          */
 414                         if (retry)
 415                                 break;
 416
 417                         slots_found = 0;
 418                         continue;
 419                 }
 420
 421                 /* start the allocation if the slot is correctly aligned */
 422                 if (!slots_found++)
 423                         alloc_start = iter;
 424
 425                 if (slots_found == num_slots) {
 426                         struct mv_xor_desc_slot *alloc_tail = NULL;
 427                         struct mv_xor_desc_slot *last_used = NULL;
 428                         iter = alloc_start;
 429                         while (num_slots) {
 430                                 int i;
 431
 432                                 /* pre-ack all but the last descriptor */
 433                                 async_tx_ack(&iter->async_tx);
 434
 435                                 list_add_tail(&iter->chain_node, &chain);
 436                                 alloc_tail = iter;
 437                                 iter->async_tx.cookie = 0;
 438                                 iter->slot_cnt = num_slots;
 439                                 iter->xor_check_result = NULL;
 440                                 for (i = 0; i < slots_per_op; i++) {
 441                                         iter->slots_per_op = slots_per_op - i;
 442                                         last_used = iter;
 443                                         iter = list_entry(iter->slot_node.next,
 444                                                 struct mv_xor_desc_slot,
 445                                                 slot_node);
 446                                 }
 447                                 num_slots -= slots_per_op;
 448                         }
 449                         alloc_tail->group_head = alloc_start;
 450                         alloc_tail->async_tx.cookie = -EBUSY;
 451                         list_splice(&chain, &alloc_tail->tx_list);
 452                         mv_chan->last_used = last_used;
 453                         mv_desc_clear_next_desc(alloc_start);
 454                         mv_desc_clear_next_desc(alloc_tail);
 455                         return alloc_tail;
 456                 }
 457         }
 458         if (!retry++)
 459                 goto retry;
 460
 461         /* try to free some slots if the allocation fails */
 462         tasklet_schedule(&mv_chan->irq_tasklet);
 463
 464         return NULL;
 465 }
 466
 467 /************************ DMA engine API functions ****************************/
 468 static dma_cookie_t
 469 mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
 470 {
 471         struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
 472         struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
 473         struct mv_xor_desc_slot *grp_start, *old_chain_tail;
 474         dma_cookie_t cookie;
 475         int new_hw_chain = 1;
 476
 477         dev_dbg(mv_chan_to_devp(mv_chan),
 478                 "%s sw_desc %p: async_tx %p\n",
 479                 __func__, sw_desc, &sw_desc->async_tx);
 480
 481         grp_start = sw_desc->group_head;
 482
 483         spin_lock_bh(&mv_chan->lock);
 484         cookie = dma_cookie_assign(tx);
 485
 486         if (list_empty(&mv_chan->chain))
 487                 list_splice_init(&sw_desc->tx_list, &mv_chan->chain);
 488         else {
 489                 new_hw_chain = 0;
 490
 491                 old_chain_tail = list_entry(mv_chan->chain.prev,
 492                                             struct mv_xor_desc_slot,
 493                                             chain_node);
 494                 list_splice_init(&grp_start->tx_list,
 495                                  &old_chain_tail->chain_node);
 496
 497                 if (!mv_can_chain(grp_start))
 498                         goto submit_done;
 499
 500                 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %x\n",
 501                         old_chain_tail->async_tx.phys);
 502
 503                 /* fix up the hardware chain */
 504                 mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
 505
 506                 /* if the channel is not busy */
 507                 if (!mv_chan_is_busy(mv_chan)) {
 508                         u32 current_desc = mv_chan_get_current_desc(mv_chan);
 509                         /*
 510                          * and the curren desc is the end of the chain before
 511                          * the append, then we need to start the channel
 512                          */
 513                         if (current_desc == old_chain_tail->async_tx.phys)
 514                                 new_hw_chain = 1;
 515                 }
 516         }
 517
 518         if (new_hw_chain)
 519                 mv_xor_start_new_chain(mv_chan, grp_start);
 520
 521 submit_done:
 522         spin_unlock_bh(&mv_chan->lock);
 523
 524         return cookie;
 525 }
 526
 527 /* returns the number of allocated descriptors */
 528 static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
 529 {
 530         char *hw_desc;
 531         int idx;
 532         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 533         struct mv_xor_desc_slot *slot = NULL;
 534         int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
 535
 536         /* Allocate descriptor slots */
 537         idx = mv_chan->slots_allocated;
 538         while (idx < num_descs_in_pool) {
 539                 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 540                 if (!slot) {
 541                         printk(KERN_INFO "MV XOR Channel only initialized"
 542                                 " %d descriptor slots", idx);
 543                         break;
 544                 }
 545                 hw_desc = (char *) mv_chan->dma_desc_pool_virt;
 546                 slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 547
 548                 dma_async_tx_descriptor_init(&slot->async_tx, chan);
 549                 slot->async_tx.tx_submit = mv_xor_tx_submit;
 550                 INIT_LIST_HEAD(&slot->chain_node);
 551                 INIT_LIST_HEAD(&slot->slot_node);
 552                 INIT_LIST_HEAD(&slot->tx_list);
 553                 hw_desc = (char *) mv_chan->dma_desc_pool;
 554                 slot->async_tx.phys =
 555                         (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE];
 556                 slot->idx = idx++;
 557
 558                 spin_lock_bh(&mv_chan->lock);
 559                 mv_chan->slots_allocated = idx;
 560                 list_add_tail(&slot->slot_node, &mv_chan->all_slots);
 561                 spin_unlock_bh(&mv_chan->lock);
 562         }
 563
 564         if (mv_chan->slots_allocated && !mv_chan->last_used)
 565                 mv_chan->last_used = list_entry(mv_chan->all_slots.next,
 566                                         struct mv_xor_desc_slot,
 567                                         slot_node);
 568
 569         dev_dbg(mv_chan_to_devp(mv_chan),
 570                 "allocated %d descriptor slots last_used: %p\n",
 571                 mv_chan->slots_allocated, mv_chan->last_used);
 572
 573         return mv_chan->slots_allocated ? : -ENOMEM;
 574 }
 575
 576 static struct dma_async_tx_descriptor *
 577 mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 578                 size_t len, unsigned long flags)
 579 {
 580         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 581         struct mv_xor_desc_slot *sw_desc, *grp_start;
 582         int slot_cnt;
 583
 584         dev_dbg(mv_chan_to_devp(mv_chan),
 585                 "%s dest: %x src %x len: %u flags: %ld\n",
 586                 __func__, dest, src, len, flags);
 587         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 588                 return NULL;
 589
 590         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 591
 592         spin_lock_bh(&mv_chan->lock);
 593         slot_cnt = mv_chan_memcpy_slot_count(len);
 594         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 595         if (sw_desc) {
 596                 sw_desc->type = DMA_MEMCPY;
 597                 sw_desc->async_tx.flags = flags;
 598                 grp_start = sw_desc->group_head;
 599                 mv_desc_init(grp_start, flags);
 600                 mv_desc_set_byte_count(grp_start, len);
 601                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 602                 mv_desc_set_src_addr(grp_start, 0, src);
 603                 sw_desc->unmap_src_cnt = 1;
 604                 sw_desc->unmap_len = len;
 605         }
 606         spin_unlock_bh(&mv_chan->lock);
 607
 608         dev_dbg(mv_chan_to_devp(mv_chan),
 609                 "%s sw_desc %p async_tx %p\n",
 610                 __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL);
 611
 612         return sw_desc ? &sw_desc->async_tx : NULL;
 613 }
 614
 615 static struct dma_async_tx_descriptor *
 616 mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
 617                     unsigned int src_cnt, size_t len, unsigned long flags)
 618 {
 619         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 620         struct mv_xor_desc_slot *sw_desc, *grp_start;
 621         int slot_cnt;
 622
 623         if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
 624                 return NULL;
 625
 626         BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
 627
 628         dev_dbg(mv_chan_to_devp(mv_chan),
 629                 "%s src_cnt: %d len: dest %x %u flags: %ld\n",
 630                 __func__, src_cnt, len, dest, flags);
 631
 632         spin_lock_bh(&mv_chan->lock);
 633         slot_cnt = mv_chan_xor_slot_count(len, src_cnt);
 634         sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1);
 635         if (sw_desc) {
 636                 sw_desc->type = DMA_XOR;
 637                 sw_desc->async_tx.flags = flags;
 638                 grp_start = sw_desc->group_head;
 639                 mv_desc_init(grp_start, flags);
 640                 /* the byte count field is the same as in memcpy desc*/
 641                 mv_desc_set_byte_count(grp_start, len);
 642                 mv_desc_set_dest_addr(sw_desc->group_head, dest);
 643                 sw_desc->unmap_src_cnt = src_cnt;
 644                 sw_desc->unmap_len = len;
 645                 while (src_cnt--)
 646                         mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]);
 647         }
 648         spin_unlock_bh(&mv_chan->lock);
 649         dev_dbg(mv_chan_to_devp(mv_chan),
 650                 "%s sw_desc %p async_tx %p \n",
 651                 __func__, sw_desc, &sw_desc->async_tx);
 652         return sw_desc ? &sw_desc->async_tx : NULL;
 653 }
 654
 655 static void mv_xor_free_chan_resources(struct dma_chan *chan)
 656 {
 657         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 658         struct mv_xor_desc_slot *iter, *_iter;
 659         int in_use_descs = 0;
 660
 661         mv_xor_slot_cleanup(mv_chan);
 662
 663         spin_lock_bh(&mv_chan->lock);
 664         list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
 665                                         chain_node) {
 666                 in_use_descs++;
 667                 list_del(&iter->chain_node);
 668         }
 669         list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
 670                                  completed_node) {
 671                 in_use_descs++;
 672                 list_del(&iter->completed_node);
 673         }
 674         list_for_each_entry_safe_reverse(
 675                 iter, _iter, &mv_chan->all_slots, slot_node) {
 676                 list_del(&iter->slot_node);
 677                 kfree(iter);
 678                 mv_chan->slots_allocated--;
 679         }
 680         mv_chan->last_used = NULL;
 681
 682         dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
 683                 __func__, mv_chan->slots_allocated);
 684         spin_unlock_bh(&mv_chan->lock);
 685
 686         if (in_use_descs)
 687                 dev_err(mv_chan_to_devp(mv_chan),
 688                         "freeing %d in use descriptors!\n", in_use_descs);
 689 }
 690
 691 /**
 692  * mv_xor_status - poll the status of an XOR transaction
 693  * @chan: XOR channel handle
 694  * @cookie: XOR transaction identifier
 695  * @txstate: XOR transactions state holder (or NULL)
 696  */
 697 static enum dma_status mv_xor_status(struct dma_chan *chan,
 698                                           dma_cookie_t cookie,
 699                                           struct dma_tx_state *txstate)
 700 {
 701         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 702         enum dma_status ret;
 703
 704         ret = dma_cookie_status(chan, cookie, txstate);
 705         if (ret == DMA_COMPLETE) {
 706                 mv_xor_clean_completed_slots(mv_chan);
 707                 return ret;
 708         }
 709         mv_xor_slot_cleanup(mv_chan);
 710
 711         return dma_cookie_status(chan, cookie, txstate);
 712 }
 713
 714 static void mv_dump_xor_regs(struct mv_xor_chan *chan)
 715 {
 716         u32 val;
 717
 718         val = readl_relaxed(XOR_CONFIG(chan));
 719         dev_err(mv_chan_to_devp(chan), "config       0x%08x\n", val);
 720
 721         val = readl_relaxed(XOR_ACTIVATION(chan));
 722         dev_err(mv_chan_to_devp(chan), "activation   0x%08x\n", val);
 723
 724         val = readl_relaxed(XOR_INTR_CAUSE(chan));
 725         dev_err(mv_chan_to_devp(chan), "intr cause   0x%08x\n", val);
 726
 727         val = readl_relaxed(XOR_INTR_MASK(chan));
 728         dev_err(mv_chan_to_devp(chan), "intr mask    0x%08x\n", val);
 729
 730         val = readl_relaxed(XOR_ERROR_CAUSE(chan));
 731         dev_err(mv_chan_to_devp(chan), "error cause  0x%08x\n", val);
 732
 733         val = readl_relaxed(XOR_ERROR_ADDR(chan));
 734         dev_err(mv_chan_to_devp(chan), "error addr   0x%08x\n", val);
 735 }
 736
 737 static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan,
 738                                          u32 intr_cause)
 739 {
 740         if (intr_cause & (1 << 4)) {
 741              dev_dbg(mv_chan_to_devp(chan),
 742                      "ignore this error\n");
 743              return;
 744         }
 745
 746         dev_err(mv_chan_to_devp(chan),
 747                 "error on chan %d. intr cause 0x%08x\n",
 748                 chan->idx, intr_cause);
 749
 750         mv_dump_xor_regs(chan);
 751         BUG();
 752 }
 753
 754 static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
 755 {
 756         struct mv_xor_chan *chan = data;
 757         u32 intr_cause = mv_chan_get_intr_cause(chan);
 758
 759         dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
 760
 761         if (mv_is_err_intr(intr_cause))
 762                 mv_xor_err_interrupt_handler(chan, intr_cause);
 763
 764         tasklet_schedule(&chan->irq_tasklet);
 765
 766         mv_xor_device_clear_eoc_cause(chan);
 767
 768         return IRQ_HANDLED;
 769 }
 770
 771 static void mv_xor_issue_pending(struct dma_chan *chan)
 772 {
 773         struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
 774
 775         if (mv_chan->pending >= MV_XOR_THRESHOLD) {
 776                 mv_chan->pending = 0;
 777                 mv_chan_activate(mv_chan);
 778         }
 779 }
 780
 781 /*
 782  * Perform a transaction to verify the HW works.
 783  */
 784
 785 static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan)
 786 {
 787         int i;
 788         void *src, *dest;
 789         dma_addr_t src_dma, dest_dma;
 790         struct dma_chan *dma_chan;
 791         dma_cookie_t cookie;
 792         struct dma_async_tx_descriptor *tx;
 793         struct dmaengine_unmap_data *unmap;
 794         int err = 0;
 795
 796         src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
 797         if (!src)
 798                 return -ENOMEM;
 799
 800         dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
 801         if (!dest) {
 802                 kfree(src);
 803                 return -ENOMEM;
 804         }
 805
 806         /* Fill in src buffer */
 807         for (i = 0; i < PAGE_SIZE; i++)
 808                 ((u8 *) src)[i] = (u8)i;
 809
 810         dma_chan = &mv_chan->dmachan;
 811         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
 812                 err = -ENODEV;
 813                 goto out;
 814         }
 815
 816         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
 817         if (!unmap) {
 818                 err = -ENOMEM;
 819                 goto free_resources;
 820         }
 821
 822         src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
 823                                  PAGE_SIZE, DMA_TO_DEVICE);
 824         unmap->to_cnt = 1;
 825         unmap->addr[0] = src_dma;
 826
 827         dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
 828                                   PAGE_SIZE, DMA_FROM_DEVICE);
 829         unmap->from_cnt = 1;
 830         unmap->addr[1] = dest_dma;
 831
 832         unmap->len = PAGE_SIZE;
 833
 834         tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
 835                                     PAGE_SIZE, 0);
 836         cookie = mv_xor_tx_submit(tx);
 837         mv_xor_issue_pending(dma_chan);
 838         async_tx_ack(tx);
 839         msleep(1);
 840
 841         if (mv_xor_status(dma_chan, cookie, NULL) !=
 842             DMA_COMPLETE) {
 843                 dev_err(dma_chan->device->dev,
 844                         "Self-test copy timed out, disabling\n");
 845                 err = -ENODEV;
 846                 goto free_resources;
 847         }
 848
 849         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
 850                                 PAGE_SIZE, DMA_FROM_DEVICE);
 851         if (memcmp(src, dest, PAGE_SIZE)) {
 852                 dev_err(dma_chan->device->dev,
 853                         "Self-test copy failed compare, disabling\n");
 854                 err = -ENODEV;
 855                 goto free_resources;
 856         }
 857
 858 free_resources:
 859         dmaengine_unmap_put(unmap);
 860         mv_xor_free_chan_resources(dma_chan);
 861 out:
 862         kfree(src);
 863         kfree(dest);
 864         return err;
 865 }
 866
 867 #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
 868 static int
 869 mv_xor_xor_self_test(struct mv_xor_chan *mv_chan)
 870 {
 871         int i, src_idx;
 872         struct page *dest;
 873         struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
 874         dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
 875         dma_addr_t dest_dma;
 876         struct dma_async_tx_descriptor *tx;
 877         struct dmaengine_unmap_data *unmap;
 878         struct dma_chan *dma_chan;
 879         dma_cookie_t cookie;
 880         u8 cmp_byte = 0;
 881         u32 cmp_word;
 882         int err = 0;
 883         int src_count = MV_XOR_NUM_SRC_TEST;
 884
 885         for (src_idx = 0; src_idx < src_count; src_idx++) {
 886                 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
 887                 if (!xor_srcs[src_idx]) {
 888                         while (src_idx--)
 889                                 __free_page(xor_srcs[src_idx]);
 890                         return -ENOMEM;
 891                 }
 892         }
 893
 894         dest = alloc_page(GFP_KERNEL);
 895         if (!dest) {
 896                 while (src_idx--)
 897                         __free_page(xor_srcs[src_idx]);
 898                 return -ENOMEM;
 899         }
 900
 901         /* Fill in src buffers */
 902         for (src_idx = 0; src_idx < src_count; src_idx++) {
 903                 u8 *ptr = page_address(xor_srcs[src_idx]);
 904                 for (i = 0; i < PAGE_SIZE; i++)
 905                         ptr[i] = (1 << src_idx);
 906         }
 907
 908         for (src_idx = 0; src_idx < src_count; src_idx++)
 909                 cmp_byte ^= (u8) (1 << src_idx);
 910
 911         cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
 912                 (cmp_byte << 8) | cmp_byte;
 913
 914         memset(page_address(dest), 0, PAGE_SIZE);
 915
 916         dma_chan = &mv_chan->dmachan;
 917         if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
 918                 err = -ENODEV;
 919                 goto out;
 920         }
 921
 922         unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
 923                                          GFP_KERNEL);
 924         if (!unmap) {
 925                 err = -ENOMEM;
 926                 goto free_resources;
 927         }
 928
 929         /* test xor */
 930         for (i = 0; i < src_count; i++) {
 931                 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
 932                                               0, PAGE_SIZE, DMA_TO_DEVICE);
 933                 dma_srcs[i] = unmap->addr[i];
 934                 unmap->to_cnt++;
 935         }
 936
 937         unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
 938                                       DMA_FROM_DEVICE);
 939         dest_dma = unmap->addr[src_count];
 940         unmap->from_cnt = 1;
 941         unmap->len = PAGE_SIZE;
 942
 943         tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
 944                                  src_count, PAGE_SIZE, 0);
 945
 946         cookie = mv_xor_tx_submit(tx);
 947         mv_xor_issue_pending(dma_chan);
 948         async_tx_ack(tx);
 949         msleep(8);
 950
 951         if (mv_xor_status(dma_chan, cookie, NULL) !=
 952             DMA_COMPLETE) {
 953                 dev_err(dma_chan->device->dev,
 954                         "Self-test xor timed out, disabling\n");
 955                 err = -ENODEV;
 956                 goto free_resources;
 957         }
 958
 959         dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
 960                                 PAGE_SIZE, DMA_FROM_DEVICE);
 961         for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
 962                 u32 *ptr = page_address(dest);
 963                 if (ptr[i] != cmp_word) {
 964                         dev_err(dma_chan->device->dev,
 965                                 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
 966                                 i, ptr[i], cmp_word);
 967                         err = -ENODEV;
 968                         goto free_resources;
 969                 }
 970         }
 971
 972 free_resources:
 973         dmaengine_unmap_put(unmap);
 974         mv_xor_free_chan_resources(dma_chan);
 975 out:
 976         src_idx = src_count;
 977         while (src_idx--)
 978                 __free_page(xor_srcs[src_idx]);
 979         __free_page(dest);
 980         return err;
 981 }
 982
 983 /* This driver does not implement any of the optional DMA operations. */
 984 static int
 985 mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 986                unsigned long arg)
 987 {
 988         return -ENOSYS;
 989 }
 990
 991 static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
 992 {
 993         struct dma_chan *chan, *_chan;
 994         struct device *dev = mv_chan->dmadev.dev;
 995
 996         dma_async_device_unregister(&mv_chan->dmadev);
 997
 998         dma_free_coherent(dev, MV_XOR_POOL_SIZE,
 999                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1000
1001         list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
1002                                  device_node) {
1003                 list_del(&chan->device_node);
1004         }
1005
1006         free_irq(mv_chan->irq, mv_chan);
1007
1008         return 0;
1009 }
1010
1011 static struct mv_xor_chan *
1012 mv_xor_channel_add(struct mv_xor_device *xordev,
1013                    struct platform_device *pdev,
1014                    int idx, dma_cap_mask_t cap_mask, int irq)
1015 {
1016         int ret = 0;
1017         struct mv_xor_chan *mv_chan;
1018         struct dma_device *dma_dev;
1019
1020         mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1021         if (!mv_chan)
1022                 return ERR_PTR(-ENOMEM);
1023
1024         mv_chan->idx = idx;
1025         mv_chan->irq = irq;
1026
1027         dma_dev = &mv_chan->dmadev;
1028
1029         /* allocate coherent memory for hardware descriptors
1030          * note: writecombine gives slightly better performance, but
1031          * requires that we explicitly flush the writes
1032          */
1033         mv_chan->dma_desc_pool_virt =
1034           dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE,
1035                                  &mv_chan->dma_desc_pool, GFP_KERNEL);
1036         if (!mv_chan->dma_desc_pool_virt)
1037                 return ERR_PTR(-ENOMEM);
1038
1039         /* discover transaction capabilites from the platform data */
1040         dma_dev->cap_mask = cap_mask;
1041
1042         INIT_LIST_HEAD(&dma_dev->channels);
1043
1044         /* set base routines */
1045         dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1046         dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1047         dma_dev->device_tx_status = mv_xor_status;
1048         dma_dev->device_issue_pending = mv_xor_issue_pending;
1049         dma_dev->device_control = mv_xor_control;
1050         dma_dev->dev = &pdev->dev;
1051
1052         /* set prep routines based on capability */
1053         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1054                 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1055         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1056                 dma_dev->max_xor = 8;
1057                 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1058         }
1059
1060         mv_chan->mmr_base = xordev->xor_base;
1061         mv_chan->mmr_high_base = xordev->xor_high_base;
1062         tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
1063                      mv_chan);
1064
1065         /* clear errors before enabling interrupts */
1066         mv_xor_device_clear_err_status(mv_chan);
1067
1068         ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1069                           0, dev_name(&pdev->dev), mv_chan);
1070         if (ret)
1071                 goto err_free_dma;
1072
1073         mv_chan_unmask_interrupts(mv_chan);
1074
1075         mv_set_mode(mv_chan, DMA_MEMCPY);
1076
1077         spin_lock_init(&mv_chan->lock);
1078         INIT_LIST_HEAD(&mv_chan->chain);
1079         INIT_LIST_HEAD(&mv_chan->completed_slots);
1080         INIT_LIST_HEAD(&mv_chan->all_slots);
1081         mv_chan->dmachan.device = dma_dev;
1082         dma_cookie_init(&mv_chan->dmachan);
1083
1084         list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1085
1086         if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1087                 ret = mv_xor_memcpy_self_test(mv_chan);
1088                 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1089                 if (ret)
1090                         goto err_free_irq;
1091         }
1092
1093         if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1094                 ret = mv_xor_xor_self_test(mv_chan);
1095                 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1096                 if (ret)
1097                         goto err_free_irq;
1098         }
1099
1100         dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n",
1101                  dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1102                  dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1103                  dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1104
1105         dma_async_device_register(dma_dev);
1106         return mv_chan;
1107
1108 err_free_irq:
1109         free_irq(mv_chan->irq, mv_chan);
1110  err_free_dma:
1111         dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1112                           mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1113         return ERR_PTR(ret);
1114 }
1115
1116 static void
1117 mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1118                          const struct mbus_dram_target_info *dram)
1119 {
1120         void __iomem *base = xordev->xor_high_base;
1121         u32 win_enable = 0;
1122         int i;
1123
1124         for (i = 0; i < 8; i++) {
1125                 writel(0, base + WINDOW_BASE(i));
1126                 writel(0, base + WINDOW_SIZE(i));
1127                 if (i < 4)
1128                         writel(0, base + WINDOW_REMAP_HIGH(i));
1129         }
1130
1131         for (i = 0; i < dram->num_cs; i++) {
1132                 const struct mbus_dram_window *cs = dram->cs + i;
1133
1134                 writel((cs->base & 0xffff0000) |
1135                        (cs->mbus_attr << 8) |
1136                        dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1137                 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1138
1139                 win_enable |= (1 << i);
1140                 win_enable |= 3 << (16 + (2 * i));
1141         }
1142
1143         writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1144         writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1145         writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1146         writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1147 }
1148
1149 static int mv_xor_probe(struct platform_device *pdev)
1150 {
1151         const struct mbus_dram_target_info *dram;
1152         struct mv_xor_device *xordev;
1153         struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1154         struct resource *res;
1155         int i, ret;
1156
1157         dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1158
1159         xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1160         if (!xordev)
1161                 return -ENOMEM;
1162
1163         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1164         if (!res)
1165                 return -ENODEV;
1166
1167         xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1168                                         resource_size(res));
1169         if (!xordev->xor_base)
1170                 return -EBUSY;
1171
1172         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1173         if (!res)
1174                 return -ENODEV;
1175
1176         xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1177                                              resource_size(res));
1178         if (!xordev->xor_high_base)
1179                 return -EBUSY;
1180
1181         platform_set_drvdata(pdev, xordev);
1182
1183         /*
1184          * (Re-)program MBUS remapping windows if we are asked to.
1185          */
1186         dram = mv_mbus_dram_info();
1187         if (dram)
1188                 mv_xor_conf_mbus_windows(xordev, dram);
1189
1190         /* Not all platforms can gate the clock, so it is not
1191          * an error if the clock does not exists.
1192          */
1193         xordev->clk = clk_get(&pdev->dev, NULL);
1194         if (!IS_ERR(xordev->clk))
1195                 clk_prepare_enable(xordev->clk);
1196
1197         if (pdev->dev.of_node) {
1198                 struct device_node *np;
1199                 int i = 0;
1200
1201                 for_each_child_of_node(pdev->dev.of_node, np) {
1202                         struct mv_xor_chan *chan;
1203                         dma_cap_mask_t cap_mask;
1204                         int irq;
1205
1206                         dma_cap_zero(cap_mask);
1207                         if (of_property_read_bool(np, "dmacap,memcpy"))
1208                                 dma_cap_set(DMA_MEMCPY, cap_mask);
1209                         if (of_property_read_bool(np, "dmacap,xor"))
1210                                 dma_cap_set(DMA_XOR, cap_mask);
1211                         if (of_property_read_bool(np, "dmacap,interrupt"))
1212                                 dma_cap_set(DMA_INTERRUPT, cap_mask);
1213
1214                         irq = irq_of_parse_and_map(np, 0);
1215                         if (!irq) {
1216                                 ret = -ENODEV;
1217                                 goto err_channel_add;
1218                         }
1219
1220                         chan = mv_xor_channel_add(xordev, pdev, i,
1221                                                   cap_mask, irq);
1222                         if (IS_ERR(chan)) {
1223                                 ret = PTR_ERR(chan);
1224                                 irq_dispose_mapping(irq);
1225                                 goto err_channel_add;
1226                         }
1227
1228                         xordev->channels[i] = chan;
1229                         i++;
1230                 }
1231         } else if (pdata && pdata->channels) {
1232                 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1233                         struct mv_xor_channel_data *cd;
1234                         struct mv_xor_chan *chan;
1235                         int irq;
1236
1237                         cd = &pdata->channels[i];
1238                         if (!cd) {
1239                                 ret = -ENODEV;
1240                                 goto err_channel_add;
1241                         }
1242
1243                         irq = platform_get_irq(pdev, i);
1244                         if (irq < 0) {
1245                                 ret = irq;
1246                                 goto err_channel_add;
1247                         }
1248
1249                         chan = mv_xor_channel_add(xordev, pdev, i,
1250                                                   cd->cap_mask, irq);
1251                         if (IS_ERR(chan)) {
1252                                 ret = PTR_ERR(chan);
1253                                 goto err_channel_add;
1254                         }
1255
1256                         xordev->channels[i] = chan;
1257                 }
1258         }
1259
1260         return 0;
1261
1262 err_channel_add:
1263         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1264                 if (xordev->channels[i]) {
1265                         mv_xor_channel_remove(xordev->channels[i]);
1266                         if (pdev->dev.of_node)
1267                                 irq_dispose_mapping(xordev->channels[i]->irq);
1268                 }
1269
1270         if (!IS_ERR(xordev->clk)) {
1271                 clk_disable_unprepare(xordev->clk);
1272                 clk_put(xordev->clk);
1273         }
1274
1275         return ret;
1276 }
1277
1278 static int mv_xor_remove(struct platform_device *pdev)
1279 {
1280         struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1281         int i;
1282
1283         for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1284                 if (xordev->channels[i])
1285                         mv_xor_channel_remove(xordev->channels[i]);
1286         }
1287
1288         if (!IS_ERR(xordev->clk)) {
1289                 clk_disable_unprepare(xordev->clk);
1290                 clk_put(xordev->clk);
1291         }
1292
1293         return 0;
1294 }
1295
1296 #ifdef CONFIG_OF
1297 static struct of_device_id mv_xor_dt_ids[] = {
1298        { .compatible = "marvell,orion-xor", },
1299        {},
1300 };
1301 MODULE_DEVICE_TABLE(of, mv_xor_dt_ids);
1302 #endif
1303
1304 static struct platform_driver mv_xor_driver = {
1305         .probe          = mv_xor_probe,
1306         .remove         = mv_xor_remove,
1307         .driver         = {
1308                 .owner          = THIS_MODULE,
1309                 .name           = MV_XOR_NAME,
1310                 .of_match_table = of_match_ptr(mv_xor_dt_ids),
1311         },
1312 };
1313
1314
1315 static int __init mv_xor_init(void)
1316 {
1317         return platform_driver_register(&mv_xor_driver);
1318 }
1319 module_init(mv_xor_init);
1320
1321 /* it's currently unsafe to unload this module */
1322 #if 0
1323 static void __exit mv_xor_exit(void)
1324 {
1325         platform_driver_unregister(&mv_xor_driver);
1326         return;
1327 }
1328
1329 module_exit(mv_xor_exit);
1330 #endif
1331
1332 MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1333 MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1334 MODULE_LICENSE("GPL");