1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
4 // Copyright (c) 2017 Sysam, Angelo Dureghello <angelo@sysam.it>
6 #include <linux/module.h>
7 #include <linux/interrupt.h>
8 #include <linux/dmaengine.h>
9 #include <linux/platform_device.h>
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
14 #define EDMA_CHANNELS 64
15 #define EDMA_MASK_CH(x) ((x) & GENMASK(5, 0))
17 static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
19 struct fsl_edma_engine *mcf_edma = dev_id;
20 struct edma_regs *regs = &mcf_edma->regs;
24 intmap = ioread32(regs->inth);
26 intmap |= ioread32(regs->intl);
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) {
31 if (intmap & BIT(ch)) {
32 iowrite8(EDMA_MASK_CH(ch), regs->cint);
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]);
40 static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
42 struct fsl_edma_engine *mcf_edma = dev_id;
43 struct edma_regs *regs = &mcf_edma->regs;
46 err = ioread32(regs->errl);
50 for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
52 fsl_edma_disable_request(&mcf_edma->chans[ch]);
53 iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
54 fsl_edma_err_chan_handler(&mcf_edma->chans[ch]);
58 err = ioread32(regs->errh);
62 for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
63 if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
64 fsl_edma_disable_request(&mcf_edma->chans[ch]);
65 iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
66 mcf_edma->chans[ch].status = DMA_ERROR;
67 mcf_edma->chans[ch].idle = true;
74 static int mcf_edma_irq_init(struct platform_device *pdev,
75 struct fsl_edma_engine *mcf_edma)
80 res = platform_get_resource_byname(pdev,
81 IORESOURCE_IRQ, "edma-tx-00-15");
85 for (ret = 0, i = res->start; i <= res->end; ++i)
86 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
90 res = platform_get_resource_byname(pdev,
91 IORESOURCE_IRQ, "edma-tx-16-55");
95 for (ret = 0, i = res->start; i <= res->end; ++i)
96 ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
100 ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
102 ret = request_irq(ret, mcf_edma_tx_handler,
103 0, "eDMA", mcf_edma);
108 ret = platform_get_irq_byname(pdev, "edma-err");
110 ret = request_irq(ret, mcf_edma_err_handler,
111 0, "eDMA", mcf_edma);
119 static void mcf_edma_irq_free(struct platform_device *pdev,
120 struct fsl_edma_engine *mcf_edma)
123 struct resource *res;
125 res = platform_get_resource_byname(pdev,
126 IORESOURCE_IRQ, "edma-tx-00-15");
128 for (irq = res->start; irq <= res->end; irq++)
129 free_irq(irq, mcf_edma);
132 res = platform_get_resource_byname(pdev,
133 IORESOURCE_IRQ, "edma-tx-16-55");
135 for (irq = res->start; irq <= res->end; irq++)
136 free_irq(irq, mcf_edma);
139 irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
141 free_irq(irq, mcf_edma);
143 irq = platform_get_irq_byname(pdev, "edma-err");
145 free_irq(irq, mcf_edma);
148 static struct fsl_edma_drvdata mcf_data = {
149 .flags = FSL_EDMA_DRV_EDMA64,
150 .setup_irq = mcf_edma_irq_init,
153 static int mcf_edma_probe(struct platform_device *pdev)
155 struct mcf_edma_platform_data *pdata;
156 struct fsl_edma_engine *mcf_edma;
157 struct edma_regs *regs;
160 pdata = dev_get_platdata(&pdev->dev);
162 dev_err(&pdev->dev, "no platform data supplied\n");
166 chans = pdata->dma_channels;
167 mcf_edma = devm_kzalloc(&pdev->dev, struct_size(mcf_edma, chans, chans),
172 mcf_edma->n_chans = chans;
174 /* Set up drvdata for ColdFire edma */
175 mcf_edma->drvdata = &mcf_data;
176 mcf_edma->big_endian = 1;
178 if (!mcf_edma->n_chans) {
179 dev_info(&pdev->dev, "setting default channel number to 64");
180 mcf_edma->n_chans = 64;
183 mutex_init(&mcf_edma->fsl_edma_mutex);
185 mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);
186 if (IS_ERR(mcf_edma->membase))
187 return PTR_ERR(mcf_edma->membase);
189 fsl_edma_setup_regs(mcf_edma);
190 regs = &mcf_edma->regs;
192 INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
193 for (i = 0; i < mcf_edma->n_chans; i++) {
194 struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
196 mcf_chan->edma = mcf_edma;
197 mcf_chan->slave_id = i;
198 mcf_chan->idle = true;
199 mcf_chan->dma_dir = DMA_NONE;
200 mcf_chan->vchan.desc_free = fsl_edma_free_desc;
201 vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
202 iowrite32(0x0, ®s->tcd[i].csr);
205 iowrite32(~0, regs->inth);
206 iowrite32(~0, regs->intl);
208 ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
212 dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
213 dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
214 dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
216 mcf_edma->dma_dev.dev = &pdev->dev;
217 mcf_edma->dma_dev.device_alloc_chan_resources =
218 fsl_edma_alloc_chan_resources;
219 mcf_edma->dma_dev.device_free_chan_resources =
220 fsl_edma_free_chan_resources;
221 mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
222 mcf_edma->dma_dev.device_prep_dma_cyclic =
223 fsl_edma_prep_dma_cyclic;
224 mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
225 mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
226 mcf_edma->dma_dev.device_pause = fsl_edma_pause;
227 mcf_edma->dma_dev.device_resume = fsl_edma_resume;
228 mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
229 mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
231 mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
232 mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
233 mcf_edma->dma_dev.directions =
234 BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
236 mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
237 mcf_edma->dma_dev.filter.map = pdata->slave_map;
238 mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
240 platform_set_drvdata(pdev, mcf_edma);
242 ret = dma_async_device_register(&mcf_edma->dma_dev);
245 "Can't register Freescale eDMA engine. (%d)\n", ret);
249 /* Enable round robin arbitration */
250 iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
255 static int mcf_edma_remove(struct platform_device *pdev)
257 struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
259 mcf_edma_irq_free(pdev, mcf_edma);
260 fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
261 dma_async_device_unregister(&mcf_edma->dma_dev);
266 static struct platform_driver mcf_edma_driver = {
270 .probe = mcf_edma_probe,
271 .remove = mcf_edma_remove,
274 bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
276 if (chan->device->dev->driver == &mcf_edma_driver.driver) {
277 struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
279 return (mcf_chan->slave_id == (uintptr_t)param);
284 EXPORT_SYMBOL(mcf_edma_filter_fn);
286 static int __init mcf_edma_init(void)
288 return platform_driver_register(&mcf_edma_driver);
290 subsys_initcall(mcf_edma_init);
292 static void __exit mcf_edma_exit(void)
294 platform_driver_unregister(&mcf_edma_driver);
296 module_exit(mcf_edma_exit);
298 MODULE_ALIAS("platform:mcf-edma");
299 MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family");
300 MODULE_LICENSE("GPL v2");