drivers/dma/jh7110-pl08x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2006 ARM Ltd.
   4  * Copyright (c) 2010 ST-Ericsson SA
   5  * Copyirght (c) 2017 Linaro Ltd.
   6  *
   7  * Author: Peter Pearse <peter.pearse@arm.com>
   8  * Author: Linus Walleij <linus.walleij@linaro.org>
   9  *
  10  * Documentation: ARM DDI 0196G == PL080
  11  * Documentation: ARM DDI 0218E == PL081
  12  * Documentation: S3C6410 User's Manual == PL080S
  13  *
  14  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
  15  * channel.
  16  *
  17  * The PL080 has 8 channels available for simultaneous use, and the PL081
  18  * has only two channels. So on these DMA controllers the number of channels
  19  * and the number of incoming DMA signals are two totally different things.
  20  * It is usually not possible to theoretically handle all physical signals,
  21  * so a multiplexing scheme with possible denial of use is necessary.
  22  *
  23  * The PL080 has a dual bus master, PL081 has a single master.
  24  *
  25  * PL080S is a version modified by Samsung and used in S3C64xx SoCs.
  26  * It differs in following aspects:
  27  * - CH_CONFIG register at different offset,
  28  * - separate CH_CONTROL2 register for transfer size,
  29  * - bigger maximum transfer size,
  30  * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
  31  * - no support for peripheral flow control.
  32  *
  33  * Memory to peripheral transfer may be visualized as
  34  *      Get data from memory to DMAC
  35  *      Until no data left
  36  *              On burst request from peripheral
  37  *                      Destination burst from DMAC to peripheral
  38  *                      Clear burst request
  39  *      Raise terminal count interrupt
  40  *
  41  * For peripherals with a FIFO:
  42  * Source      burst size == half the depth of the peripheral FIFO
  43  * Destination burst size == the depth of the peripheral FIFO
  44  *
  45  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  46  * signals, the DMA controller will simply facilitate its AHB master.)
  47  *
  48  * ASSUMES default (little) endianness for DMA transfers
  49  *
  50  * The PL08x has two flow control settings:
  51  *  - DMAC flow control: the transfer size defines the number of transfers
  52  *    which occur for the current LLI entry, and the DMAC raises TC at the
  53  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  54  *    to both the BREQ and SREQ signals (contrary to documented),
  55  *    transferring data if either is active.  The LBREQ and LSREQ signals
  56  *    are ignored.
  57  *
  58  *  - Peripheral flow control: the transfer size is ignored (and should be
  59  *    zero).  The data is transferred from the current LLI entry, until
  60  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  61  *    will then move to the next LLI entry. Unsupported by PL080S.
  62  */
  63 //#include <linux/amba/bus.h>
  64 #include <linux/amba/pl08x.h>
  65 #include <linux/debugfs.h>
  66 #include <linux/delay.h>
  67 #include <linux/device.h>
  68 #include <linux/dmaengine.h>
  69 #include <linux/dmapool.h>
  70 #include <linux/dma-mapping.h>
  71 #include <linux/export.h>
  72 #include <linux/init.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/module.h>
  75 #include <linux/of.h>
  76 #include <linux/of_dma.h>
  77 #include <linux/of_device.h>
  78 #include <linux/platform_device.h>
  79 #include <linux/pm_runtime.h>
  80 #include <linux/seq_file.h>
  81 #include <linux/slab.h>
  82 #include <linux/amba/pl080.h>
  83
  84 #include "dmaengine.h"
  85 #include "virt-dma.h"
  86
  87 #define DRIVER_NAME     "pl08xdmac"
  88
  89 #define PL80X_DMA_BUSWIDTHS \
  90         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  91         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  92         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  93         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  94
  95 //static struct amba_driver pl08x_amba_driver;
  96 struct pl08x_driver_data;
  97
  98 /**
  99  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
 100  * @config_offset: offset to the configuration register
 101  * @channels: the number of channels available in this variant
 102  * @signals: the number of request signals available from the hardware
 103  * @dualmaster: whether this version supports dual AHB masters or not.
 104  * @nomadik: whether this variant is a ST Microelectronics Nomadik, where the
 105  *      channels have Nomadik security extension bits that need to be checked
 106  *      for permission before use and some registers are missing
 107  * @pl080s: whether this variant is a Samsung PL080S, which has separate
 108  *      register and LLI word for transfer size.
 109  * @ftdmac020: whether this variant is a Faraday Technology FTDMAC020
 110  * @max_transfer_size: the maximum single element transfer size for this
 111  *      PL08x variant.
 112  */
 113 struct vendor_data {
 114         u8 config_offset;
 115         u8 channels;
 116         u8 signals;
 117         bool dualmaster;
 118         bool nomadik;
 119         bool pl080s;
 120         bool ftdmac020;
 121         u32 max_transfer_size;
 122 };
 123
 124 /**
 125  * struct pl08x_bus_data - information of source or destination
 126  * busses for a transfer
 127  * @addr: current address
 128  * @maxwidth: the maximum width of a transfer on this bus
 129  * @buswidth: the width of this bus in bytes: 1, 2 or 4
 130  */
 131 struct pl08x_bus_data {
 132         dma_addr_t addr;
 133         u8 maxwidth;
 134         u8 buswidth;
 135 };
 136
 137 #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
 138
 139 /**
 140  * struct pl08x_phy_chan - holder for the physical channels
 141  * @id: physical index to this channel
 142  * @base: memory base address for this physical channel
 143  * @reg_config: configuration address for this physical channel
 144  * @reg_control: control address for this physical channel
 145  * @reg_src: transfer source address register
 146  * @reg_dst: transfer destination address register
 147  * @reg_lli: transfer LLI address register
 148  * @reg_busy: if the variant has a special per-channel busy register,
 149  * this contains a pointer to it
 150  * @lock: a lock to use when altering an instance of this struct
 151  * @serving: the virtual channel currently being served by this physical
 152  * channel
 153  * @locked: channel unavailable for the system, e.g. dedicated to secure
 154  * world
 155  * @ftdmac020: channel is on a FTDMAC020
 156  * @pl080s: channel is on a PL08s
 157  */
 158 struct pl08x_phy_chan {
 159         unsigned int id;
 160         void __iomem *base;
 161         void __iomem *reg_config;
 162         void __iomem *reg_control;
 163         void __iomem *reg_src;
 164         void __iomem *reg_dst;
 165         void __iomem *reg_lli;
 166         void __iomem *reg_busy;
 167         spinlock_t lock;
 168         struct pl08x_dma_chan *serving;
 169         bool locked;
 170         bool ftdmac020;
 171         bool pl080s;
 172 };
 173
 174 /**
 175  * struct pl08x_sg - structure containing data per sg
 176  * @src_addr: src address of sg
 177  * @dst_addr: dst address of sg
 178  * @len: transfer len in bytes
 179  * @node: node for txd's dsg_list
 180  */
 181 struct pl08x_sg {
 182         dma_addr_t src_addr;
 183         dma_addr_t dst_addr;
 184         size_t len;
 185         struct list_head node;
 186 };
 187
 188 /**
 189  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 190  * @vd: virtual DMA descriptor
 191  * @dsg_list: list of children sg's
 192  * @llis_bus: DMA memory address (physical) start for the LLIs
 193  * @llis_va: virtual memory address start for the LLIs
 194  * @cctl: control reg values for current txd
 195  * @ccfg: config reg values for current txd
 196  * @done: this marks completed descriptors, which should not have their
 197  *   mux released.
 198  * @cyclic: indicate cyclic transfers
 199  */
 200 struct pl08x_txd {
 201         struct virt_dma_desc vd;
 202         struct list_head dsg_list;
 203         dma_addr_t llis_bus;
 204         u32 *llis_va;
 205         /* Default cctl value for LLIs */
 206         u32 cctl;
 207         /*
 208          * Settings to be put into the physical channel when we
 209          * trigger this txd.  Other registers are in llis_va[0].
 210          */
 211         u32 ccfg;
 212         bool done;
 213         bool cyclic;
 214 };
 215
 216 /**
 217  * enum pl08x_dma_chan_state - holds the PL08x specific virtual channel
 218  * states
 219  * @PL08X_CHAN_IDLE: the channel is idle
 220  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 221  * channel and is running a transfer on it
 222  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 223  * channel, but the transfer is currently paused
 224  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 225  * channel to become available (only pertains to memcpy channels)
 226  */
 227 enum pl08x_dma_chan_state {
 228         PL08X_CHAN_IDLE,
 229         PL08X_CHAN_RUNNING,
 230         PL08X_CHAN_PAUSED,
 231         PL08X_CHAN_WAITING,
 232 };
 233
 234 /**
 235  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 236  * @vc: wrappped virtual channel
 237  * @phychan: the physical channel utilized by this channel, if there is one
 238  * @name: name of channel
 239  * @cd: channel platform data
 240  * @cfg: slave configuration
 241  * @at: active transaction on this channel
 242  * @host: a pointer to the host (internal use)
 243  * @state: whether the channel is idle, paused, running etc
 244  * @slave: whether this channel is a device (slave) or for memcpy
 245  * @signal: the physical DMA request signal which this channel is using
 246  * @mux_use: count of descriptors using this DMA request signal setting
 247  * @waiting_at: time in jiffies when this channel moved to waiting state
 248  */
 249 struct pl08x_dma_chan {
 250         struct virt_dma_chan vc;
 251         struct pl08x_phy_chan *phychan;
 252         const char *name;
 253         struct pl08x_channel_data *cd;
 254         struct dma_slave_config cfg;
 255         struct pl08x_txd *at;
 256         struct pl08x_driver_data *host;
 257         enum pl08x_dma_chan_state state;
 258         int chan_id;
 259         bool slave;
 260         int signal;
 261         unsigned mux_use;
 262         unsigned long waiting_at;
 263 };
 264
 265 /**
 266  * struct pl08x_driver_data - the local state holder for the PL08x
 267  * @slave: optional slave engine for this instance
 268  * @memcpy: memcpy engine for this instance
 269  * @has_slave: the PL08x has a slave engine (routed signals)
 270  * @base: virtual memory base (remapped) for the PL08x
 271  * @adev: the corresponding AMBA (PrimeCell) bus entry
 272  * @vd: vendor data for this PL08x variant
 273  * @pd: platform data passed in from the platform/machine
 274  * @phy_chans: array of data for the physical channels
 275  * @pool: a pool for the LLI descriptors
 276  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
 277  * fetches
 278  * @mem_buses: set to indicate memory transfers on AHB2.
 279  * @lli_words: how many words are used in each LLI item for this variant
 280  */
 281 struct pl08x_driver_data {
 282         struct dma_device slave;
 283         struct dma_device memcpy;
 284         bool has_slave;
 285         void __iomem *base;
 286         struct platform_device *adev;
 287         const struct vendor_data *vd;
 288         struct pl08x_platform_data *pd;
 289         struct pl08x_phy_chan *phy_chans;
 290         struct dma_pool *pool;
 291         u8 lli_buses;
 292         u8 mem_buses;
 293         u8 lli_words;
 294 };
 295
 296 /*
 297  * PL08X specific defines
 298  */
 299
 300 /* The order of words in an LLI. */
 301 #define PL080_LLI_SRC           0
 302 #define PL080_LLI_DST           1
 303 #define PL080_LLI_LLI           2
 304 #define PL080_LLI_CCTL          3
 305 #define PL080S_LLI_CCTL2        4
 306
 307 /* Total words in an LLI. */
 308 #define PL080_LLI_WORDS         4
 309 #define PL080S_LLI_WORDS        8
 310
 311 /*
 312  * Number of LLIs in each LLI buffer allocated for one transfer
 313  * (maximum times we call dma_pool_alloc on this pool without freeing)
 314  */
 315 #define MAX_NUM_TSFR_LLIS       512
 316 #define PL08X_ALIGN             8
 317
 318 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 319 {
 320         return container_of(chan, struct pl08x_dma_chan, vc.chan);
 321 }
 322
 323 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
 324 {
 325         return container_of(tx, struct pl08x_txd, vd.tx);
 326 }
 327
 328 /*
 329  * Mux handling.
 330  *
 331  * This gives us the DMA request input to the PL08x primecell which the
 332  * peripheral described by the channel data will be routed to, possibly
 333  * via a board/SoC specific external MUX.  One important point to note
 334  * here is that this does not depend on the physical channel.
 335  */
 336 static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
 337 {
 338         const struct pl08x_platform_data *pd = plchan->host->pd;
 339         int ret;
 340
 341         if (plchan->mux_use++ == 0 && pd->get_xfer_signal) {
 342                 ret = pd->get_xfer_signal(plchan->cd);
 343                 if (ret < 0) {
 344                         plchan->mux_use = 0;
 345                         return ret;
 346                 }
 347
 348                 plchan->signal = ret;
 349         }
 350         return 0;
 351 }
 352
 353 static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
 354 {
 355         const struct pl08x_platform_data *pd = plchan->host->pd;
 356
 357         if (plchan->signal >= 0) {
 358                 WARN_ON(plchan->mux_use == 0);
 359
 360                 if (--plchan->mux_use == 0 && pd->put_xfer_signal) {
 361                         pd->put_xfer_signal(plchan->cd, plchan->signal);
 362                         plchan->signal = -1;
 363                 }
 364         }
 365 }
 366
 367 /*
 368  * Physical channel handling
 369  */
 370
 371 /* Whether a certain channel is busy or not */
 372 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 373 {
 374         unsigned int val;
 375
 376         /* If we have a special busy register, take a shortcut */
 377         if (ch->reg_busy) {
 378                 val = readl(ch->reg_busy);
 379                 return !!(val & BIT(ch->id));
 380         }
 381         val = readl(ch->reg_config);
 382         return val & PL080_CONFIG_ACTIVE;
 383 }
 384
 385 /*
 386  * pl08x_write_lli() - Write an LLI into the DMA controller.
 387  *
 388  * The PL08x derivatives support linked lists, but the first item of the
 389  * list containing the source, destination, control word and next LLI is
 390  * ignored. Instead the driver has to write those values directly into the
 391  * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE
 392  * register need to be set up for the first transfer.
 393  */
 394 static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
 395                 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
 396 {
 397         if (pl08x->vd->pl080s)
 398                 dev_vdbg(&pl08x->adev->dev,
 399                         "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 400                         "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",
 401                         phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
 402                         lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL],
 403                         lli[PL080S_LLI_CCTL2], ccfg);
 404         else
 405                 //dev_vdbg(&pl08x->adev->dev,
 406                 dev_info(&pl08x->adev->dev,
 407                         "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 408                         "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
 409                         phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
 410                         lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);
 411
 412         writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
 413         writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
 414         writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
 415
 416         /*
 417          * The FTMAC020 has a different layout in the CCTL word of the LLI
 418          * and the CCTL register which is split in CSR and SIZE registers.
 419          * Convert the LLI item CCTL into the proper values to write into
 420          * the CSR and SIZE registers.
 421          */
 422         if (phychan->ftdmac020) {
 423                 u32 llictl = lli[PL080_LLI_CCTL];
 424                 u32 val = 0;
 425
 426                 /* Write the transfer size (12 bits) to the size register */
 427                 writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK,
 428                                phychan->base + FTDMAC020_CH_SIZE);
 429                 /*
 430                  * Then write the control bits 28..16 to the control register
 431                  * by shuffleing the bits around to where they are in the
 432                  * main register. The mapping is as follows:
 433                  * Bit 28: TC_MSK - mask on all except last LLI
 434                  * Bit 27..25: SRC_WIDTH
 435                  * Bit 24..22: DST_WIDTH
 436                  * Bit 21..20: SRCAD_CTRL
 437                  * Bit 19..17: DSTAD_CTRL
 438                  * Bit 17: SRC_SEL
 439                  * Bit 16: DST_SEL
 440                  */
 441                 if (llictl & FTDMAC020_LLI_TC_MSK)
 442                         val |= FTDMAC020_CH_CSR_TC_MSK;
 443                 val |= ((llictl  & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
 444                         (FTDMAC020_LLI_SRC_WIDTH_SHIFT -
 445                          FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT));
 446                 val |= ((llictl  & FTDMAC020_LLI_DST_WIDTH_MSK) >>
 447                         (FTDMAC020_LLI_DST_WIDTH_SHIFT -
 448                          FTDMAC020_CH_CSR_DST_WIDTH_SHIFT));
 449                 val |= ((llictl  & FTDMAC020_LLI_SRCAD_CTL_MSK) >>
 450                         (FTDMAC020_LLI_SRCAD_CTL_SHIFT -
 451                          FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT));
 452                 val |= ((llictl  & FTDMAC020_LLI_DSTAD_CTL_MSK) >>
 453                         (FTDMAC020_LLI_DSTAD_CTL_SHIFT -
 454                          FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT));
 455                 if (llictl & FTDMAC020_LLI_SRC_SEL)
 456                         val |= FTDMAC020_CH_CSR_SRC_SEL;
 457                 if (llictl & FTDMAC020_LLI_DST_SEL)
 458                         val |= FTDMAC020_CH_CSR_DST_SEL;
 459
 460                 /*
 461                  * Set up the bits that exist in the CSR but are not
 462                  * part the LLI, i.e. only gets written to the control
 463                  * register right here.
 464                  *
 465                  * FIXME: do not just handle memcpy, also handle slave DMA.
 466                  */
 467                 switch (pl08x->pd->memcpy_burst_size) {
 468                 default:
 469                 case PL08X_BURST_SZ_1:
 470                         val |= PL080_BSIZE_1 <<
 471                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 472                         break;
 473                 case PL08X_BURST_SZ_4:
 474                         val |= PL080_BSIZE_4 <<
 475                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 476                         break;
 477                 case PL08X_BURST_SZ_8:
 478                         val |= PL080_BSIZE_8 <<
 479                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 480                         break;
 481                 case PL08X_BURST_SZ_16:
 482                         val |= PL080_BSIZE_16 <<
 483                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 484                         break;
 485                 case PL08X_BURST_SZ_32:
 486                         val |= PL080_BSIZE_32 <<
 487                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 488                         break;
 489                 case PL08X_BURST_SZ_64:
 490                         val |= PL080_BSIZE_64 <<
 491                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 492                         break;
 493                 case PL08X_BURST_SZ_128:
 494                         val |= PL080_BSIZE_128 <<
 495                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 496                         break;
 497                 case PL08X_BURST_SZ_256:
 498                         val |= PL080_BSIZE_256 <<
 499                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 500                         break;
 501                 }
 502
 503                 /* Protection flags */
 504                 if (pl08x->pd->memcpy_prot_buff)
 505                         val |= FTDMAC020_CH_CSR_PROT2;
 506                 if (pl08x->pd->memcpy_prot_cache)
 507                         val |= FTDMAC020_CH_CSR_PROT3;
 508                 /* We are the kernel, so we are in privileged mode */
 509                 val |= FTDMAC020_CH_CSR_PROT1;
 510
 511                 writel_relaxed(val, phychan->reg_control);
 512         } else {
 513                 /*              printk("this is debug lli[PL080_LLI_CCTL] = %x reg_control = %x  %s %s %d\n",
 514                        lli[PL080_LLI_CCTL],phychan->reg_control,__FILE__,__func__,__LINE__);
 515                 */
 516                 /* Bits are just identical */
 517                 writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
 518         }
 519
 520         /* Second control word on the PL080s */
 521         if (pl08x->vd->pl080s)
 522                 writel_relaxed(lli[PL080S_LLI_CCTL2],
 523                                 phychan->base + PL080S_CH_CONTROL2);
 524
 525         /*
 526         printk("this is debug ccfg = %x reg_config = %x  %s %s %d\n",
 527                ccfg,phychan->reg_config,__FILE__,__func__,__LINE__);
 528         */
 529         writel(ccfg, phychan->reg_config);
 530 }
 531
 532 /*
 533  * Set the initial DMA register values i.e. those for the first LLI
 534  * The next LLI pointer and the configuration interrupt bit have
 535  * been set when the LLIs were constructed.  Poke them into the hardware
 536  * and start the transfer.
 537  */
 538 static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 539 {
 540         struct pl08x_driver_data *pl08x = plchan->host;
 541         struct pl08x_phy_chan *phychan = plchan->phychan;
 542         struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc);
 543         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
 544         u32 val;
 545
 546         list_del(&txd->vd.node);
 547
 548         plchan->at = txd;
 549
 550         /* Wait for channel inactive */
 551         while (pl08x_phy_channel_busy(phychan))
 552                 cpu_relax();
 553         //printk("this is debug txd->ccfg = %x  %s %s %d\n",txd->ccfg,__FILE__,__func__,__LINE__);
 554         pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);
 555
 556         /* Enable the DMA channel */
 557         /* Do not access config register until channel shows as disabled */
 558         //printk("this is debug en_chan = %x id = %d %s %s %d\n",readl(pl08x->base + PL080_EN_CHAN),phychan->id,__FILE__,__func__,__LINE__);
 559         while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
 560                 cpu_relax();
 561
 562         //printk("this is debug en_chan = %x id = %d %s %s %d\n",readl(pl08x->base + PL080_EN_CHAN),phychan->id,__FILE__,__func__,__LINE__);
 563         /* Do not access config register until channel shows as inactive */
 564         if (phychan->ftdmac020) {
 565                 val = readl(phychan->reg_config);
 566                 while (val & FTDMAC020_CH_CFG_BUSY)
 567                         val = readl(phychan->reg_config);
 568
 569                 val = readl(phychan->reg_control);
 570                 while (val & FTDMAC020_CH_CSR_EN)
 571                         val = readl(phychan->reg_control);
 572
 573                 writel(val | FTDMAC020_CH_CSR_EN,
 574                        phychan->reg_control);
 575         } else {
 576                 val = readl(phychan->reg_config);
 577                 while ((val & PL080_CONFIG_ACTIVE) ||
 578                        (val & PL080_CONFIG_ENABLE))
 579                         val = readl(phychan->reg_config);
 580                 //printk("this is debug val = %x  phychan->reg_config = %x  %s %s %d\n",val, phychan->reg_config,__FILE__,__func__,__LINE__);
 581                 writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
 582 #if 0
 583                 while(!(readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))){
 584                         printk("this is debug val = %x  phychan->reg_config = %x  %s %s %d\n",val, phychan->reg_config,__FILE__,__func__,__LINE__);
 585                         writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
 586                 }
 587 #endif
 588         }
 589         //printk("this is debug reg_config = %x  en_chan = %x id = %d %s %s %d\n",readl(phychan->reg_config),
 590         //       readl(pl08x->base + PL080_EN_CHAN),phychan->id,__FILE__,__func__,__LINE__);
 591 }
 592
 593 /*
 594  * Pause the channel by setting the HALT bit.
 595  *
 596  * For M->P transfers, pause the DMAC first and then stop the peripheral -
 597  * the FIFO can only drain if the peripheral is still requesting data.
 598  * (note: this can still timeout if the DMAC FIFO never drains of data.)
 599  *
 600  * For P->M transfers, disable the peripheral first to stop it filling
 601  * the DMAC FIFO, and then pause the DMAC.
 602  */
 603 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 604 {
 605         u32 val;
 606         int timeout;
 607
 608         if (ch->ftdmac020) {
 609                 /* Use the enable bit on the FTDMAC020 */
 610                 val = readl(ch->reg_control);
 611                 val &= ~FTDMAC020_CH_CSR_EN;
 612                 writel(val, ch->reg_control);
 613                 return;
 614         }
 615
 616         /* Set the HALT bit and wait for the FIFO to drain */
 617         val = readl(ch->reg_config);
 618         val |= PL080_CONFIG_HALT;
 619         writel(val, ch->reg_config);
 620
 621         /* Wait for channel inactive */
 622         for (timeout = 1000; timeout; timeout--) {
 623                 if (!pl08x_phy_channel_busy(ch))
 624                         break;
 625                 udelay(1);
 626         }
 627         if (pl08x_phy_channel_busy(ch))
 628                 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
 629 }
 630
 631 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 632 {
 633         u32 val;
 634
 635         /* Use the enable bit on the FTDMAC020 */
 636         if (ch->ftdmac020) {
 637                 val = readl(ch->reg_control);
 638                 val |= FTDMAC020_CH_CSR_EN;
 639                 writel(val, ch->reg_control);
 640                 return;
 641         }
 642
 643         /* Clear the HALT bit */
 644         val = readl(ch->reg_config);
 645         val &= ~PL080_CONFIG_HALT;
 646         writel(val, ch->reg_config);
 647 }
 648
 649 /*
 650  * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
 651  * clears any pending interrupt status.  This should not be used for
 652  * an on-going transfer, but as a method of shutting down a channel
 653  * (eg, when it's no longer used) or terminating a transfer.
 654  */
 655 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 656         struct pl08x_phy_chan *ch)
 657 {
 658         u32 val;
 659
 660         /* The layout for the FTDMAC020 is different */
 661         if (ch->ftdmac020) {
 662                 /* Disable all interrupts */
 663                 val = readl(ch->reg_config);
 664                 val |= (FTDMAC020_CH_CFG_INT_ABT_MASK |
 665                         FTDMAC020_CH_CFG_INT_ERR_MASK |
 666                         FTDMAC020_CH_CFG_INT_TC_MASK);
 667                 writel(val, ch->reg_config);
 668
 669                 /* Abort and disable channel */
 670                 val = readl(ch->reg_control);
 671                 val &= ~FTDMAC020_CH_CSR_EN;
 672                 val |= FTDMAC020_CH_CSR_ABT;
 673                 writel(val, ch->reg_control);
 674
 675                 /* Clear ABT and ERR interrupt flags */
 676                 writel(BIT(ch->id) | BIT(ch->id + 16),
 677                        pl08x->base + PL080_ERR_CLEAR);
 678                 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
 679
 680                 return;
 681         }
 682
 683         val = readl(ch->reg_config);
 684         val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
 685                  PL080_CONFIG_TC_IRQ_MASK);
 686         writel(val, ch->reg_config);
 687
 688         writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
 689         writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
 690 }
 691
 692 static u32 get_bytes_in_phy_channel(struct pl08x_phy_chan *ch)
 693 {
 694         u32 val;
 695         u32 bytes;
 696
 697         if (ch->ftdmac020) {
 698                 bytes = readl(ch->base + FTDMAC020_CH_SIZE);
 699
 700                 val = readl(ch->reg_control);
 701                 val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK;
 702                 val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT;
 703         } else if (ch->pl080s) {
 704                 val = readl(ch->base + PL080S_CH_CONTROL2);
 705                 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 706
 707                 val = readl(ch->reg_control);
 708                 val &= PL080_CONTROL_SWIDTH_MASK;
 709                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 710         } else {
 711                 /* Plain PL08x */
 712                 val = readl(ch->reg_control);
 713                 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
 714
 715                 val &= PL080_CONTROL_SWIDTH_MASK;
 716                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 717         }
 718
 719         switch (val) {
 720         case PL080_WIDTH_8BIT:
 721                 break;
 722         case PL080_WIDTH_16BIT:
 723                 bytes *= 2;
 724                 break;
 725         case PL080_WIDTH_32BIT:
 726                 bytes *= 4;
 727                 break;
 728         }
 729         return bytes;
 730 }
 731
 732 static u32 get_bytes_in_lli(struct pl08x_phy_chan *ch, const u32 *llis_va)
 733 {
 734         u32 val;
 735         u32 bytes;
 736
 737         if (ch->ftdmac020) {
 738                 val = llis_va[PL080_LLI_CCTL];
 739                 bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK;
 740
 741                 val = llis_va[PL080_LLI_CCTL];
 742                 val &= FTDMAC020_LLI_SRC_WIDTH_MSK;
 743                 val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT;
 744         } else if (ch->pl080s) {
 745                 val = llis_va[PL080S_LLI_CCTL2];
 746                 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 747
 748                 val = llis_va[PL080_LLI_CCTL];
 749                 val &= PL080_CONTROL_SWIDTH_MASK;
 750                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 751         } else {
 752                 /* Plain PL08x */
 753                 val = llis_va[PL080_LLI_CCTL];
 754                 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
 755
 756                 val &= PL080_CONTROL_SWIDTH_MASK;
 757                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 758         }
 759
 760         switch (val) {
 761         case PL080_WIDTH_8BIT:
 762                 break;
 763         case PL080_WIDTH_16BIT:
 764                 bytes *= 2;
 765                 break;
 766         case PL080_WIDTH_32BIT:
 767                 bytes *= 4;
 768                 break;
 769         }
 770         return bytes;
 771 }
 772
 773 /* The channel should be paused when calling this */
 774 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 775 {
 776         struct pl08x_driver_data *pl08x = plchan->host;
 777         const u32 *llis_va, *llis_va_limit;
 778         struct pl08x_phy_chan *ch;
 779         dma_addr_t llis_bus;
 780         struct pl08x_txd *txd;
 781         u32 llis_max_words;
 782         size_t bytes;
 783         u32 clli;
 784
 785         ch = plchan->phychan;
 786         txd = plchan->at;
 787
 788         if (!ch || !txd)
 789                 return 0;
 790
 791         /*
 792          * Follow the LLIs to get the number of remaining
 793          * bytes in the currently active transaction.
 794          */
 795         clli = readl(ch->reg_lli) & ~PL080_LLI_LM_AHB2;
 796
 797         /* First get the remaining bytes in the active transfer */
 798         bytes = get_bytes_in_phy_channel(ch);
 799
 800         if (!clli)
 801                 return bytes;
 802
 803         llis_va = txd->llis_va;
 804         llis_bus = txd->llis_bus;
 805
 806         llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS;
 807         BUG_ON(clli < llis_bus || clli >= llis_bus +
 808                                                 sizeof(u32) * llis_max_words);
 809
 810         /*
 811          * Locate the next LLI - as this is an array,
 812          * it's simple maths to find.
 813          */
 814         llis_va += (clli - llis_bus) / sizeof(u32);
 815
 816         llis_va_limit = llis_va + llis_max_words;
 817
 818         for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) {
 819                 bytes += get_bytes_in_lli(ch, llis_va);
 820
 821                 /*
 822                  * A LLI pointer going backward terminates the LLI list
 823                  */
 824                 if (llis_va[PL080_LLI_LLI] <= clli)
 825                         break;
 826         }
 827
 828         return bytes;
 829 }
 830
 831 /*
 832  * Allocate a physical channel for a virtual channel
 833  *
 834  * Try to locate a physical channel to be used for this transfer. If all
 835  * are taken return NULL and the requester will have to cope by using
 836  * some fallback PIO mode or retrying later.
 837  */
 838 static struct pl08x_phy_chan *
 839 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 840                       struct pl08x_dma_chan *virt_chan)
 841 {
 842         struct pl08x_phy_chan *ch = NULL;
 843         unsigned long flags;
 844         int i;
 845
 846         //printk("this is debug virt_chan->id = %d %s %s %d\n",virt_chan->chan_id,__FILE__,__func__,__LINE__);
 847 #if 1
 848         ch = &pl08x->phy_chans[virt_chan->chan_id];
 849
 850         spin_lock_irqsave(&ch->lock, flags);
 851
 852         if (!ch->locked && !ch->serving) {
 853                 ch->serving = virt_chan;
 854                 spin_unlock_irqrestore(&ch->lock, flags);
 855                 return ch;
 856         }
 857
 858         spin_unlock_irqrestore(&ch->lock, flags);
 859 #endif
 860         for (i = 0; i < pl08x->vd->channels; i++) {
 861                 ch = &pl08x->phy_chans[i];
 862
 863                 spin_lock_irqsave(&ch->lock, flags);
 864
 865                 if (!ch->locked && !ch->serving) {
 866                         ch->serving = virt_chan;
 867                         spin_unlock_irqrestore(&ch->lock, flags);
 868                         break;
 869                 }
 870
 871                 spin_unlock_irqrestore(&ch->lock, flags);
 872         }
 873
 874         if (i == pl08x->vd->channels) {
 875                 /* No physical channel available, cope with it */
 876                 return NULL;
 877         }
 878
 879         return ch;
 880 }
 881
 882 /* Mark the physical channel as free.  Note, this write is atomic. */
 883 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 884                                          struct pl08x_phy_chan *ch)
 885 {
 886         ch->serving = NULL;
 887 }
 888
 889 /*
 890  * Try to allocate a physical channel.  When successful, assign it to
 891  * this virtual channel, and initiate the next descriptor.  The
 892  * virtual channel lock must be held at this point.
 893  */
 894 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan)
 895 {
 896         struct pl08x_driver_data *pl08x = plchan->host;
 897         struct pl08x_phy_chan *ch;
 898
 899         ch = pl08x_get_phy_channel(pl08x, plchan);
 900         if (!ch) {
 901                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
 902                 plchan->state = PL08X_CHAN_WAITING;
 903                 plchan->waiting_at = jiffies;
 904                 return;
 905         }
 906
 907         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
 908                 ch->id, plchan->name);
 909
 910         plchan->phychan = ch;
 911         plchan->state = PL08X_CHAN_RUNNING;
 912         pl08x_start_next_txd(plchan);
 913 }
 914
 915 static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
 916         struct pl08x_dma_chan *plchan)
 917 {
 918         struct pl08x_driver_data *pl08x = plchan->host;
 919
 920         dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
 921                 ch->id, plchan->name);
 922
 923         /*
 924          * We do this without taking the lock; we're really only concerned
 925          * about whether this pointer is NULL or not, and we're guaranteed
 926          * that this will only be called when it _already_ is non-NULL.
 927          */
 928         ch->serving = plchan;
 929         plchan->phychan = ch;
 930         plchan->state = PL08X_CHAN_RUNNING;
 931         pl08x_start_next_txd(plchan);
 932 }
 933
 934 /*
 935  * Free a physical DMA channel, potentially reallocating it to another
 936  * virtual channel if we have any pending.
 937  */
 938 static void pl08x_phy_free(struct pl08x_dma_chan *plchan)
 939 {
 940         struct pl08x_driver_data *pl08x = plchan->host;
 941         struct pl08x_dma_chan *p, *next;
 942         unsigned long waiting_at;
 943  retry:
 944         next = NULL;
 945         waiting_at = jiffies;
 946
 947         /*
 948          * Find a waiting virtual channel for the next transfer.
 949          * To be fair, time when each channel reached waiting state is compared
 950          * to select channel that is waiting for the longest time.
 951          */
 952         list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
 953                 if (p->state == PL08X_CHAN_WAITING &&
 954                     p->waiting_at <= waiting_at) {
 955                         next = p;
 956                         waiting_at = p->waiting_at;
 957                 }
 958
 959         if (!next && pl08x->has_slave) {
 960                 list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
 961                         if (p->state == PL08X_CHAN_WAITING &&
 962                             p->waiting_at <= waiting_at) {
 963                                 next = p;
 964                                 waiting_at = p->waiting_at;
 965                         }
 966         }
 967
 968         /* Ensure that the physical channel is stopped */
 969         pl08x_terminate_phy_chan(pl08x, plchan->phychan);
 970
 971         if (next) {
 972                 bool success;
 973
 974                 /*
 975                  * Eww.  We know this isn't going to deadlock
 976                  * but lockdep probably doesn't.
 977                  */
 978                 spin_lock(&next->vc.lock);
 979                 /* Re-check the state now that we have the lock */
 980                 success = next->state == PL08X_CHAN_WAITING;
 981                 if (success)
 982                         pl08x_phy_reassign_start(plchan->phychan, next);
 983                 spin_unlock(&next->vc.lock);
 984
 985                 /* If the state changed, try to find another channel */
 986                 if (!success)
 987                         goto retry;
 988         } else {
 989                 /* No more jobs, so free up the physical channel */
 990                 pl08x_put_phy_channel(pl08x, plchan->phychan);
 991         }
 992
 993         plchan->phychan = NULL;
 994         plchan->state = PL08X_CHAN_IDLE;
 995 }
 996
 997 /*
 998  * LLI handling
 999  */
1000
1001 static inline unsigned int
1002 pl08x_get_bytes_for_lli(struct pl08x_driver_data *pl08x,
1003                         u32 cctl,
1004                         bool source)
1005 {
1006         u32 val;
1007
1008         if (pl08x->vd->ftdmac020) {
1009                 if (source)
1010                         val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
1011                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1012                 else
1013                         val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
1014                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1015         } else {
1016                 if (source)
1017                         val = (cctl & PL080_CONTROL_SWIDTH_MASK) >>
1018                                 PL080_CONTROL_SWIDTH_SHIFT;
1019                 else
1020                         val = (cctl & PL080_CONTROL_DWIDTH_MASK) >>
1021                                 PL080_CONTROL_DWIDTH_SHIFT;
1022         }
1023
1024         switch (val) {
1025         case PL080_WIDTH_8BIT:
1026                 return 1;
1027         case PL080_WIDTH_16BIT:
1028                 return 2;
1029         case PL080_WIDTH_32BIT:
1030                 return 4;
1031         default:
1032                 break;
1033         }
1034         BUG();
1035         return 0;
1036 }
1037
1038 static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x,
1039                                          u32 cctl,
1040                                          u8 srcwidth, u8 dstwidth,
1041                                          size_t tsize)
1042 {
1043         u32 retbits = cctl;
1044
1045         /*
1046          * Remove all src, dst and transfer size bits, then set the
1047          * width and size according to the parameters. The bit offsets
1048          * are different in the FTDMAC020 so we need to accound for this.
1049          */
1050         if (pl08x->vd->ftdmac020) {
1051                 retbits &= ~FTDMAC020_LLI_DST_WIDTH_MSK;
1052                 retbits &= ~FTDMAC020_LLI_SRC_WIDTH_MSK;
1053                 retbits &= ~FTDMAC020_LLI_TRANSFER_SIZE_MASK;
1054
1055                 switch (srcwidth) {
1056                 case 1:
1057                         retbits |= PL080_WIDTH_8BIT <<
1058                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1059                         break;
1060                 case 2:
1061                         retbits |= PL080_WIDTH_16BIT <<
1062                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1063                         break;
1064                 case 4:
1065                         retbits |= PL080_WIDTH_32BIT <<
1066                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1067                         break;
1068                 default:
1069                         BUG();
1070                         break;
1071                 }
1072
1073                 switch (dstwidth) {
1074                 case 1:
1075                         retbits |= PL080_WIDTH_8BIT <<
1076                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1077                         break;
1078                 case 2:
1079                         retbits |= PL080_WIDTH_16BIT <<
1080                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1081                         break;
1082                 case 4:
1083                         retbits |= PL080_WIDTH_32BIT <<
1084                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1085                         break;
1086                 default:
1087                         BUG();
1088                         break;
1089                 }
1090
1091                 tsize &= FTDMAC020_LLI_TRANSFER_SIZE_MASK;
1092                 retbits |= tsize << FTDMAC020_LLI_TRANSFER_SIZE_SHIFT;
1093         } else {
1094                 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
1095                 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
1096                 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
1097
1098                 switch (srcwidth) {
1099                 case 1:
1100                         retbits |= PL080_WIDTH_8BIT <<
1101                                 PL080_CONTROL_SWIDTH_SHIFT;
1102                         break;
1103                 case 2:
1104                         retbits |= PL080_WIDTH_16BIT <<
1105                                 PL080_CONTROL_SWIDTH_SHIFT;
1106                         break;
1107                 case 4:
1108                         retbits |= PL080_WIDTH_32BIT <<
1109                                 PL080_CONTROL_SWIDTH_SHIFT;
1110                         break;
1111                 default:
1112                         BUG();
1113                         break;
1114                 }
1115
1116                 switch (dstwidth) {
1117                 case 1:
1118                         retbits |= PL080_WIDTH_8BIT <<
1119                                 PL080_CONTROL_DWIDTH_SHIFT;
1120                         break;
1121                 case 2:
1122                         retbits |= PL080_WIDTH_16BIT <<
1123                                 PL080_CONTROL_DWIDTH_SHIFT;
1124                         break;
1125                 case 4:
1126                         retbits |= PL080_WIDTH_32BIT <<
1127                                 PL080_CONTROL_DWIDTH_SHIFT;
1128                         break;
1129                 default:
1130                         BUG();
1131                         break;
1132                 }
1133
1134                 tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK;
1135                 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
1136         }
1137
1138         return retbits;
1139 }
1140
1141 struct pl08x_lli_build_data {
1142         struct pl08x_txd *txd;
1143         struct pl08x_bus_data srcbus;
1144         struct pl08x_bus_data dstbus;
1145         size_t remainder;
1146         u32 lli_bus;
1147 };
1148
1149 /*
1150  * Autoselect a master bus to use for the transfer. Slave will be the chosen as
1151  * victim in case src & dest are not similarly aligned. i.e. If after aligning
1152  * masters address with width requirements of transfer (by sending few byte by
1153  * byte data), slave is still not aligned, then its width will be reduced to
1154  * BYTE.
1155  * - prefers the destination bus if both available
1156  * - prefers bus with fixed address (i.e. peripheral)
1157  */
1158 static void pl08x_choose_master_bus(struct pl08x_driver_data *pl08x,
1159                                     struct pl08x_lli_build_data *bd,
1160                                     struct pl08x_bus_data **mbus,
1161                                     struct pl08x_bus_data **sbus,
1162                                     u32 cctl)
1163 {
1164         bool dst_incr;
1165         bool src_incr;
1166
1167         /*
1168          * The FTDMAC020 only supports memory-to-memory transfer, so
1169          * source and destination always increase.
1170          */
1171         if (pl08x->vd->ftdmac020) {
1172                 dst_incr = true;
1173                 src_incr = true;
1174         } else {
1175                 dst_incr = !!(cctl & PL080_CONTROL_DST_INCR);
1176                 src_incr = !!(cctl & PL080_CONTROL_SRC_INCR);
1177         }
1178
1179         /*
1180          * If either bus is not advancing, i.e. it is a peripheral, that
1181          * one becomes master
1182          */
1183         if (!dst_incr) {
1184                 *mbus = &bd->dstbus;
1185                 *sbus = &bd->srcbus;
1186         } else if (!src_incr) {
1187                 *mbus = &bd->srcbus;
1188                 *sbus = &bd->dstbus;
1189         } else {
1190                 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
1191                         *mbus = &bd->dstbus;
1192                         *sbus = &bd->srcbus;
1193                 } else {
1194                         *mbus = &bd->srcbus;
1195                         *sbus = &bd->dstbus;
1196                 }
1197         }
1198 }
1199
1200 /*
1201  * Fills in one LLI for a certain transfer descriptor and advance the counter
1202  */
1203 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
1204                                     struct pl08x_lli_build_data *bd,
1205                                     int num_llis, int len, u32 cctl, u32 cctl2)
1206 {
1207         u32 offset = num_llis * pl08x->lli_words;
1208         u32 *llis_va = bd->txd->llis_va + offset;
1209         dma_addr_t llis_bus = bd->txd->llis_bus;
1210
1211         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
1212
1213         /*
1214         printk("this is debug num_llis = %x lli_words = %x %s %s %d\n",
1215                 num_llis,pl08x->lli_words,__FILE__,__func__,__LINE__);
1216         */
1217         /* Advance the offset to next LLI. */
1218         offset += pl08x->lli_words;
1219
1220         llis_va[PL080_LLI_SRC] = bd->srcbus.addr;
1221         llis_va[PL080_LLI_DST] = bd->dstbus.addr;
1222         llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset);
1223         llis_va[PL080_LLI_LLI] |= bd->lli_bus;
1224         llis_va[PL080_LLI_CCTL] = cctl;
1225         if (pl08x->vd->pl080s)
1226                 llis_va[PL080S_LLI_CCTL2] = cctl2;
1227
1228         if (pl08x->vd->ftdmac020) {
1229                 /* FIXME: only memcpy so far so both increase */
1230                 bd->srcbus.addr += len;
1231                 bd->dstbus.addr += len;
1232         } else {
1233                 if (cctl & PL080_CONTROL_SRC_INCR)
1234                         bd->srcbus.addr += len;
1235                 if (cctl & PL080_CONTROL_DST_INCR)
1236                         bd->dstbus.addr += len;
1237         }
1238
1239         BUG_ON(bd->remainder < len);
1240
1241         bd->remainder -= len;
1242 }
1243
1244 static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
1245                         struct pl08x_lli_build_data *bd, u32 *cctl, u32 len,
1246                         int num_llis, size_t *total_bytes)
1247 {
1248         *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len);
1249         pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len);
1250         (*total_bytes) += len;
1251 }
1252
1253 #if 1
1254 static void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1255                            const u32 *llis_va, int num_llis)
1256 {
1257         int i;
1258
1259         if (pl08x->vd->pl080s) {
1260                 dev_vdbg(&pl08x->adev->dev,
1261                         "%-3s %-9s  %-10s %-10s %-10s %-10s %s\n",
1262                         "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
1263                 for (i = 0; i < num_llis; i++) {
1264                         dev_vdbg(&pl08x->adev->dev,
1265                                 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1266                                 i, llis_va, llis_va[PL080_LLI_SRC],
1267                                 llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
1268                                 llis_va[PL080_LLI_CCTL],
1269                                 llis_va[PL080S_LLI_CCTL2]);
1270                         llis_va += pl08x->lli_words;
1271                 }
1272         } else {
1273                 //dev_vdbg(&pl08x->adev->dev,
1274                 dev_info(&pl08x->adev->dev,
1275                         "%-3s %-9s  %-10s %-10s %-10s %s\n",
1276                         "lli", "", "csrc", "cdst", "clli", "cctl");
1277                 for (i = 0; i < num_llis; i++) {
1278                         //dev_vdbg(&pl08x->adev->dev,
1279                         dev_info(&pl08x->adev->dev,
1280                                 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1281                                 i, llis_va, llis_va[PL080_LLI_SRC],
1282                                 llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
1283                                 llis_va[PL080_LLI_CCTL]);
1284                         llis_va += pl08x->lli_words;
1285                 }
1286         }
1287 }
1288 #else
1289 static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1290                                   const u32 *llis_va, int num_llis) {}
1291 #endif
1292
1293 extern u64 dw_virt_to_phys(void *vaddr);
1294 /*
1295  * This fills in the table of LLIs for the transfer descriptor
1296  * Note that we assume we never have to change the burst sizes
1297  * Return 0 for error
1298  */
1299 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
1300                               struct pl08x_txd *txd)
1301 {
1302         struct pl08x_bus_data *mbus, *sbus;
1303         struct pl08x_lli_build_data bd;
1304         int num_llis = 0;
1305         u32 cctl, early_bytes = 0;
1306         size_t max_bytes_per_lli, total_bytes;
1307         u32 *llis_va, *last_lli;
1308         struct pl08x_sg *dsg;
1309
1310         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
1311         if (!txd->llis_va) {
1312                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
1313                 return 0;
1314         }
1315
1316         /*
1317         printk("this is debug txd->llis_bus = %llx pl08x->lli_buses = %x llis_va = %llx %s %s %d\n",
1318                txd->llis_bus,pl08x->lli_buses,dw_virt_to_phys(txd->llis_va),__FILE__,__func__,__LINE__);
1319         */
1320         bd.txd = txd;
1321         bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
1322         cctl = txd->cctl;
1323
1324         /* Find maximum width of the source bus */
1325         bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true);
1326
1327         /* Find maximum width of the destination bus */
1328         bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false);
1329
1330         list_for_each_entry(dsg, &txd->dsg_list, node) {
1331                 total_bytes = 0;
1332                 cctl = txd->cctl;
1333
1334                 bd.srcbus.addr = dsg->src_addr;
1335                 bd.dstbus.addr = dsg->dst_addr;
1336                 bd.remainder = dsg->len;
1337                 bd.srcbus.buswidth = bd.srcbus.maxwidth;
1338                 bd.dstbus.buswidth = bd.dstbus.maxwidth;
1339
1340                 pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl);
1341
1342                 dev_vdbg(&pl08x->adev->dev,
1343                         "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
1344                         (u64)bd.srcbus.addr,
1345                         cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
1346                         bd.srcbus.buswidth,
1347                         (u64)bd.dstbus.addr,
1348                         cctl & PL080_CONTROL_DST_INCR ? "+" : "",
1349                         bd.dstbus.buswidth,
1350                         bd.remainder);
1351                 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
1352                         mbus == &bd.srcbus ? "src" : "dst",
1353                         sbus == &bd.srcbus ? "src" : "dst");
1354
1355                 /*
1356                  * Zero length is only allowed if all these requirements are
1357                  * met:
1358                  * - flow controller is peripheral.
1359                  * - src.addr is aligned to src.width
1360                  * - dst.addr is aligned to dst.width
1361                  *
1362                  * sg_len == 1 should be true, as there can be two cases here:
1363                  *
1364                  * - Memory addresses are contiguous and are not scattered.
1365                  *   Here, Only one sg will be passed by user driver, with
1366                  *   memory address and zero length. We pass this to controller
1367                  *   and after the transfer it will receive the last burst
1368                  *   request from peripheral and so transfer finishes.
1369                  *
1370                  * - Memory addresses are scattered and are not contiguous.
1371                  *   Here, Obviously as DMA controller doesn't know when a lli's
1372                  *   transfer gets over, it can't load next lli. So in this
1373                  *   case, there has to be an assumption that only one lli is
1374                  *   supported. Thus, we can't have scattered addresses.
1375                  */
1376                 if (!bd.remainder) {
1377                         u32 fc;
1378
1379                         /* FTDMAC020 only does memory-to-memory */
1380                         if (pl08x->vd->ftdmac020)
1381                                 fc = PL080_FLOW_MEM2MEM;
1382                         else
1383                                 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
1384                                         PL080_CONFIG_FLOW_CONTROL_SHIFT;
1385                         if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
1386                                         (fc <= PL080_FLOW_SRC2DST_SRC))) {
1387                                 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
1388                                         __func__);
1389                                 return 0;
1390                         }
1391
1392                         if (!IS_BUS_ALIGNED(&bd.srcbus) ||
1393                                 !IS_BUS_ALIGNED(&bd.dstbus)) {
1394                                 dev_err(&pl08x->adev->dev,
1395                                         "%s src & dst address must be aligned to src"
1396                                         " & dst width if peripheral is flow controller",
1397                                         __func__);
1398                                 return 0;
1399                         }
1400
1401                         cctl = pl08x_lli_control_bits(pl08x, cctl,
1402                                         bd.srcbus.buswidth, bd.dstbus.buswidth,
1403                                         0);
1404                         pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1405                                         0, cctl, 0);
1406                         break;
1407                 }
1408
1409                 /*
1410                  * Send byte by byte for following cases
1411                  * - Less than a bus width available
1412                  * - until master bus is aligned
1413                  */
1414                 if (bd.remainder < mbus->buswidth)
1415                         early_bytes = bd.remainder;
1416                 else if (!IS_BUS_ALIGNED(mbus)) {
1417                         early_bytes = mbus->buswidth -
1418                                 (mbus->addr & (mbus->buswidth - 1));
1419                         if ((bd.remainder - early_bytes) < mbus->buswidth)
1420                                 early_bytes = bd.remainder;
1421                 }
1422
1423                 if (early_bytes) {
1424                         dev_vdbg(&pl08x->adev->dev,
1425                                 "%s byte width LLIs (remain 0x%08zx)\n",
1426                                 __func__, bd.remainder);
1427                         prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes,
1428                                 num_llis++, &total_bytes);
1429                 }
1430
1431                 if (bd.remainder) {
1432                         /*
1433                          * Master now aligned
1434                          * - if slave is not then we must set its width down
1435                          */
1436                         if (!IS_BUS_ALIGNED(sbus)) {
1437                                 dev_dbg(&pl08x->adev->dev,
1438                                         "%s set down bus width to one byte\n",
1439                                         __func__);
1440
1441                                 sbus->buswidth = 1;
1442                         }
1443
1444                         /*
1445                          * Bytes transferred = tsize * src width, not
1446                          * MIN(buswidths)
1447                          */
1448                         max_bytes_per_lli = bd.srcbus.buswidth *
1449                                                 pl08x->vd->max_transfer_size;
1450                         dev_vdbg(&pl08x->adev->dev,
1451                                 "%s max bytes per lli = %zu\n",
1452                                 __func__, max_bytes_per_lli);
1453
1454                         /*
1455                          * Make largest possible LLIs until less than one bus
1456                          * width left
1457                          */
1458                         while (bd.remainder > (mbus->buswidth - 1)) {
1459                                 size_t lli_len, tsize, width;
1460
1461                                 /*
1462                                  * If enough left try to send max possible,
1463                                  * otherwise try to send the remainder
1464                                  */
1465                                 lli_len = min(bd.remainder, max_bytes_per_lli);
1466
1467                                 /*
1468                                  * Check against maximum bus alignment:
1469                                  * Calculate actual transfer size in relation to
1470                                  * bus width an get a maximum remainder of the
1471                                  * highest bus width - 1
1472                                  */
1473                                 width = max(mbus->buswidth, sbus->buswidth);
1474                                 lli_len = (lli_len / width) * width;
1475                                 tsize = lli_len / bd.srcbus.buswidth;
1476
1477                                 dev_vdbg(&pl08x->adev->dev,
1478                                         "%s fill lli with single lli chunk of "
1479                                         "size 0x%08zx (remainder 0x%08zx)\n",
1480                                         __func__, lli_len, bd.remainder);
1481
1482                                 cctl = pl08x_lli_control_bits(pl08x, cctl,
1483                                         bd.srcbus.buswidth, bd.dstbus.buswidth,
1484                                         tsize);
1485                                 pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1486                                                 lli_len, cctl, tsize);
1487                                 total_bytes += lli_len;
1488                         }
1489
1490                         /*
1491                          * Send any odd bytes
1492                          */
1493                         if (bd.remainder) {
1494                                 dev_vdbg(&pl08x->adev->dev,
1495                                         "%s align with boundary, send odd bytes (remain %zu)\n",
1496                                         __func__, bd.remainder);
1497                                 prep_byte_width_lli(pl08x, &bd, &cctl,
1498                                         bd.remainder, num_llis++, &total_bytes);
1499                         }
1500                 }
1501
1502                 if (total_bytes != dsg->len) {
1503                         dev_err(&pl08x->adev->dev,
1504                                 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1505                                 __func__, total_bytes, dsg->len);
1506                         return 0;
1507                 }
1508
1509                 if (num_llis >= MAX_NUM_TSFR_LLIS) {
1510                         dev_err(&pl08x->adev->dev,
1511                                 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1512                                 __func__, MAX_NUM_TSFR_LLIS);
1513                         return 0;
1514                 }
1515         }
1516
1517         llis_va = txd->llis_va;
1518         last_lli = llis_va + (num_llis - 1) * pl08x->lli_words;
1519
1520         if (txd->cyclic) {
1521                 /* Link back to the first LLI. */
1522                 last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus;
1523         } else {
1524                 /* The final LLI terminates the LLI. */
1525                 last_lli[PL080_LLI_LLI] = 0;
1526                 /* The final LLI element shall also fire an interrupt. */
1527                 if (pl08x->vd->ftdmac020)
1528                         last_lli[PL080_LLI_CCTL] &= ~FTDMAC020_LLI_TC_MSK;
1529                 else
1530                         last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN;
1531         }
1532
1533         pl08x_dump_lli(pl08x, llis_va, num_llis);
1534
1535         return num_llis;
1536 }
1537
1538 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
1539                            struct pl08x_txd *txd)
1540 {
1541         struct pl08x_sg *dsg, *_dsg;
1542
1543         if (txd->llis_va)
1544                 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
1545
1546         list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
1547                 list_del(&dsg->node);
1548                 kfree(dsg);
1549         }
1550
1551         kfree(txd);
1552 }
1553
1554 static void pl08x_desc_free(struct virt_dma_desc *vd)
1555 {
1556         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1557         struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
1558
1559         dma_descriptor_unmap(&vd->tx);
1560         if (!txd->done)
1561                 pl08x_release_mux(plchan);
1562
1563         pl08x_free_txd(plchan->host, txd);
1564 }
1565
1566 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1567                                 struct pl08x_dma_chan *plchan)
1568 {
1569         LIST_HEAD(head);
1570
1571         vchan_get_all_descriptors(&plchan->vc, &head);
1572         vchan_dma_desc_free_list(&plchan->vc, &head);
1573 }
1574
1575 /*
1576  * The DMA ENGINE API
1577  */
1578 static void pl08x_free_chan_resources(struct dma_chan *chan)
1579 {
1580         /* Ensure all queued descriptors are freed */
1581         vchan_free_chan_resources(to_virt_chan(chan));
1582 }
1583
1584 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1585                 struct dma_chan *chan, unsigned long flags)
1586 {
1587         struct dma_async_tx_descriptor *retval = NULL;
1588
1589         return retval;
1590 }
1591
1592 /*
1593  * Code accessing dma_async_is_complete() in a tight loop may give problems.
1594  * If slaves are relying on interrupts to signal completion this function
1595  * must not be called with interrupts disabled.
1596  */
1597 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1598                 dma_cookie_t cookie, struct dma_tx_state *txstate)
1599 {
1600         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1601         struct virt_dma_desc *vd;
1602         unsigned long flags;
1603         enum dma_status ret;
1604         size_t bytes = 0;
1605
1606         ret = dma_cookie_status(chan, cookie, txstate);
1607         if (ret == DMA_COMPLETE)
1608                 return ret;
1609
1610         /*
1611          * There's no point calculating the residue if there's
1612          * no txstate to store the value.
1613          */
1614         if (!txstate) {
1615                 if (plchan->state == PL08X_CHAN_PAUSED)
1616                         ret = DMA_PAUSED;
1617                 return ret;
1618         }
1619
1620         spin_lock_irqsave(&plchan->vc.lock, flags);
1621         ret = dma_cookie_status(chan, cookie, txstate);
1622         if (ret != DMA_COMPLETE) {
1623                 vd = vchan_find_desc(&plchan->vc, cookie);
1624                 if (vd) {
1625                         /* On the issued list, so hasn't been processed yet */
1626                         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1627                         struct pl08x_sg *dsg;
1628
1629                         list_for_each_entry(dsg, &txd->dsg_list, node)
1630                                 bytes += dsg->len;
1631                 } else {
1632                         bytes = pl08x_getbytes_chan(plchan);
1633                 }
1634         }
1635         spin_unlock_irqrestore(&plchan->vc.lock, flags);
1636
1637         /*
1638          * This cookie not complete yet
1639          * Get number of bytes left in the active transactions and queue
1640          */
1641         dma_set_residue(txstate, bytes);
1642
1643         if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
1644                 ret = DMA_PAUSED;
1645
1646         /* Whether waiting or running, we're in progress */
1647         return ret;
1648 }
1649
1650 /* PrimeCell DMA extension */
1651 struct burst_table {
1652         u32 burstwords;
1653         u32 reg;
1654 };
1655
1656 static const struct burst_table burst_sizes[] = {
1657         {
1658                 .burstwords = 256,
1659                 .reg = PL080_BSIZE_256,
1660         },
1661         {
1662                 .burstwords = 128,
1663                 .reg = PL080_BSIZE_128,
1664         },
1665         {
1666                 .burstwords = 64,
1667                 .reg = PL080_BSIZE_64,
1668         },
1669         {
1670                 .burstwords = 32,
1671                 .reg = PL080_BSIZE_32,
1672         },
1673         {
1674                 .burstwords = 16,
1675                 .reg = PL080_BSIZE_16,
1676         },
1677         {
1678                 .burstwords = 8,
1679                 .reg = PL080_BSIZE_8,
1680         },
1681         {
1682                 .burstwords = 4,
1683                 .reg = PL080_BSIZE_4,
1684         },
1685         {
1686                 .burstwords = 0,
1687                 .reg = PL080_BSIZE_1,
1688         },
1689 };
1690
1691 /*
1692  * Given the source and destination available bus masks, select which
1693  * will be routed to each port.  We try to have source and destination
1694  * on separate ports, but always respect the allowable settings.
1695  */
1696 static u32 pl08x_select_bus(bool ftdmac020, u8 src, u8 dst)
1697 {
1698         u32 cctl = 0;
1699         u32 dst_ahb2;
1700         u32 src_ahb2;
1701
1702         /* The FTDMAC020 use different bits to indicate src/dst bus */
1703         if (ftdmac020) {
1704                 dst_ahb2 = FTDMAC020_LLI_DST_SEL;
1705                 src_ahb2 = FTDMAC020_LLI_SRC_SEL;
1706         } else {
1707                 dst_ahb2 = PL080_CONTROL_DST_AHB2;
1708                 src_ahb2 = PL080_CONTROL_SRC_AHB2;
1709         }
1710
1711         if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1712                 cctl |= dst_ahb2;
1713         if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1714                 cctl |= src_ahb2;
1715
1716         //printk("this is debug dst = %x src = %x cctl = %x %s %s %d\n",dst,src,cctl,__FILE__,__func__,__LINE__);
1717
1718         return cctl;
1719 }
1720
1721 static u32 pl08x_cctl(u32 cctl)
1722 {
1723         cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1724                   PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1725                   PL080_CONTROL_PROT_MASK);
1726
1727         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1728         return cctl | PL080_CONTROL_PROT_SYS;
1729 }
1730
1731 static u32 pl08x_width(enum dma_slave_buswidth width)
1732 {
1733         switch (width) {
1734         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1735                 return PL080_WIDTH_8BIT;
1736         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1737                 return PL080_WIDTH_16BIT;
1738         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1739                 return PL080_WIDTH_32BIT;
1740         default:
1741                 return ~0;
1742         }
1743 }
1744
1745 static u32 pl08x_burst(u32 maxburst)
1746 {
1747         int i;
1748
1749         for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1750                 if (burst_sizes[i].burstwords <= maxburst)
1751                         break;
1752
1753         return burst_sizes[i].reg;
1754 }
1755
1756 static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
1757         enum dma_slave_buswidth addr_width, u32 maxburst)
1758 {
1759         u32 width, burst, cctl = 0;
1760
1761         width = pl08x_width(addr_width);
1762         if (width == ~0)
1763                 return ~0;
1764
1765         cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1766         cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1767
1768         /*
1769          * If this channel will only request single transfers, set this
1770          * down to ONE element.  Also select one element if no maxburst
1771          * is specified.
1772          */
1773         if (plchan->cd->single)
1774                 maxburst = 1;
1775
1776         burst = pl08x_burst(maxburst);
1777         cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1778         cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1779
1780         return pl08x_cctl(cctl);
1781 }
1782
1783 /*
1784  * Slave transactions callback to the slave device to allow
1785  * synchronization of slave DMA signals with the DMAC enable
1786  */
1787 static void pl08x_issue_pending(struct dma_chan *chan)
1788 {
1789         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1790         unsigned long flags;
1791
1792         plchan->chan_id = chan->chan_id;
1793
1794         spin_lock_irqsave(&plchan->vc.lock, flags);
1795         if (vchan_issue_pending(&plchan->vc)) {
1796                 if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
1797                         pl08x_phy_alloc_and_start(plchan);
1798         }
1799         spin_unlock_irqrestore(&plchan->vc.lock, flags);
1800 }
1801
1802 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1803 {
1804         struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1805
1806         if (txd)
1807                 INIT_LIST_HEAD(&txd->dsg_list);
1808         return txd;
1809 }
1810
1811 static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x)
1812 {
1813         u32 cctl = 0;
1814
1815         /* Conjure cctl */
1816         switch (pl08x->pd->memcpy_burst_size) {
1817         default:
1818                 dev_err(&pl08x->adev->dev,
1819                         "illegal burst size for memcpy, set to 1\n");
1820                 fallthrough;
1821         case PL08X_BURST_SZ_1:
1822                 cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
1823                         PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;
1824                 break;
1825         case PL08X_BURST_SZ_4:
1826                 cctl |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
1827                         PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT;
1828                 break;
1829         case PL08X_BURST_SZ_8:
1830                 cctl |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT |
1831                         PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT;
1832                 break;
1833         case PL08X_BURST_SZ_16:
1834                 cctl |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT |
1835                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT;
1836                 break;
1837         case PL08X_BURST_SZ_32:
1838                 cctl |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT |
1839                         PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT;
1840                 break;
1841         case PL08X_BURST_SZ_64:
1842                 cctl |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT |
1843                         PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT;
1844                 break;
1845         case PL08X_BURST_SZ_128:
1846                 cctl |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT |
1847                         PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT;
1848                 break;
1849         case PL08X_BURST_SZ_256:
1850                 cctl |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |
1851                         PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT;
1852                 break;
1853         }
1854
1855         switch (pl08x->pd->memcpy_bus_width) {
1856         default:
1857                 dev_err(&pl08x->adev->dev,
1858                         "illegal bus width for memcpy, set to 8 bits\n");
1859                 fallthrough;
1860         case PL08X_BUS_WIDTH_8_BITS:
1861                 cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
1862                         PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
1863                 break;
1864         case PL08X_BUS_WIDTH_16_BITS:
1865                 cctl |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT |
1866                         PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
1867                 break;
1868         case PL08X_BUS_WIDTH_32_BITS:
1869                 cctl |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
1870                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
1871                 break;
1872         }
1873
1874         /* Protection flags */
1875         if (pl08x->pd->memcpy_prot_buff)
1876                 cctl |= PL080_CONTROL_PROT_BUFF;
1877         if (pl08x->pd->memcpy_prot_cache)
1878                 cctl |= PL080_CONTROL_PROT_CACHE;
1879
1880         /* We are the kernel, so we are in privileged mode */
1881         cctl |= PL080_CONTROL_PROT_SYS;
1882
1883         /* Both to be incremented or the code will break */
1884         cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1885
1886         if (pl08x->vd->dualmaster)
1887                 cctl |= pl08x_select_bus(false,
1888                                          pl08x->mem_buses,
1889                                          pl08x->mem_buses);
1890
1891         return cctl;
1892 }
1893
1894 static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x)
1895 {
1896         u32 cctl = 0;
1897
1898         /* Conjure cctl */
1899         switch (pl08x->pd->memcpy_bus_width) {
1900         default:
1901                 dev_err(&pl08x->adev->dev,
1902                         "illegal bus width for memcpy, set to 8 bits\n");
1903                 fallthrough;
1904         case PL08X_BUS_WIDTH_8_BITS:
1905                 cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1906                         PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1907                 break;
1908         case PL08X_BUS_WIDTH_16_BITS:
1909                 cctl |= PL080_WIDTH_16BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1910                         PL080_WIDTH_16BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1911                 break;
1912         case PL08X_BUS_WIDTH_32_BITS:
1913                 cctl |= PL080_WIDTH_32BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1914                         PL080_WIDTH_32BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1915                 break;
1916         }
1917
1918         /*
1919          * By default mask the TC IRQ on all LLIs, it will be unmasked on
1920          * the last LLI item by other code.
1921          */
1922         cctl |= FTDMAC020_LLI_TC_MSK;
1923
1924         /*
1925          * Both to be incremented so leave bits FTDMAC020_LLI_SRCAD_CTL
1926          * and FTDMAC020_LLI_DSTAD_CTL as zero
1927          */
1928         if (pl08x->vd->dualmaster)
1929                 cctl |= pl08x_select_bus(true,
1930                                          pl08x->mem_buses,
1931                                          pl08x->mem_buses);
1932
1933         return cctl;
1934 }
1935
1936 /*
1937  * Initialize a descriptor to be used by memcpy submit
1938  */
1939 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1940                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1941                 size_t len, unsigned long flags)
1942 {
1943         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1944         struct pl08x_driver_data *pl08x = plchan->host;
1945         struct pl08x_txd *txd;
1946         struct pl08x_sg *dsg;
1947         int ret;
1948         //printk("this is debug for lophyel %s %s %d\n",__FILE__,__func__,__LINE__);
1949         txd = pl08x_get_txd(plchan);
1950         if (!txd) {
1951                 dev_err(&pl08x->adev->dev,
1952                         "%s no memory for descriptor\n", __func__);
1953                 return NULL;
1954         }
1955         //printk("this is debug for lophyel %s %s %d\n",__FILE__,__func__,__LINE__);
1956         dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1957         if (!dsg) {
1958                 pl08x_free_txd(pl08x, txd);
1959                 return NULL;
1960         }
1961         list_add_tail(&dsg->node, &txd->dsg_list);
1962         //printk("this is debug for lophyel %s %s %d\n",__FILE__,__func__,__LINE__);
1963         dsg->src_addr = src;
1964         dsg->dst_addr = dest;
1965         dsg->len = len;
1966         if (pl08x->vd->ftdmac020) {
1967                 /* Writing CCFG zero ENABLES all interrupts */
1968                 txd->ccfg = 0;
1969                 txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x);
1970         } else {
1971                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1972                         PL080_CONFIG_TC_IRQ_MASK |
1973                         PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1974                 txd->cctl = pl08x_memcpy_cctl(pl08x);
1975         }
1976         //printk("this is debug for lophyel %s %s %d\n",__FILE__,__func__,__LINE__);
1977         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
1978         if (!ret) {
1979                 pl08x_free_txd(pl08x, txd);
1980                 return NULL;
1981         }
1982         //printk("this is debug for lophyel %s %s %d\n",__FILE__,__func__,__LINE__);
1983         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
1984 }
1985
1986 static struct pl08x_txd *pl08x_init_txd(
1987                 struct dma_chan *chan,
1988                 enum dma_transfer_direction direction,
1989                 dma_addr_t *slave_addr)
1990 {
1991         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1992         struct pl08x_driver_data *pl08x = plchan->host;
1993         struct pl08x_txd *txd;
1994         enum dma_slave_buswidth addr_width;
1995         int ret, tmp;
1996         u8 src_buses, dst_buses;
1997         u32 maxburst, cctl;
1998
1999         txd = pl08x_get_txd(plchan);
2000         if (!txd) {
2001                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
2002                 return NULL;
2003         }
2004
2005         /*
2006          * Set up addresses, the PrimeCell configured address
2007          * will take precedence since this may configure the
2008          * channel target address dynamically at runtime.
2009          */
2010         if (direction == DMA_MEM_TO_DEV) {
2011                 //printk("this is debug  %s %s %d\n",__FILE__,__func__,__LINE__);
2012                 cctl = PL080_CONTROL_SRC_INCR;
2013                 *slave_addr = plchan->cfg.dst_addr;
2014                 addr_width = plchan->cfg.dst_addr_width;
2015                 maxburst = plchan->cfg.dst_maxburst;
2016                 src_buses = pl08x->mem_buses;
2017                 dst_buses = plchan->cd->periph_buses;
2018         } else if (direction == DMA_DEV_TO_MEM) {
2019                 //printk("this is debug  %s %s %d\n",__FILE__,__func__,__LINE__);
2020                 cctl = PL080_CONTROL_DST_INCR;
2021                 *slave_addr = plchan->cfg.src_addr;
2022                 addr_width = plchan->cfg.src_addr_width;
2023                 maxburst = plchan->cfg.src_maxburst;
2024                 src_buses = plchan->cd->periph_buses;
2025                 dst_buses = pl08x->mem_buses;
2026         } else {
2027                 pl08x_free_txd(pl08x, txd);
2028                 dev_err(&pl08x->adev->dev,
2029                         "%s direction unsupported\n", __func__);
2030                 return NULL;
2031         }
2032
2033         cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
2034         if (cctl == ~0) {
2035                 pl08x_free_txd(pl08x, txd);
2036                 dev_err(&pl08x->adev->dev,
2037                         "DMA slave configuration botched?\n");
2038                 return NULL;
2039         }
2040
2041         txd->cctl = cctl | pl08x_select_bus(false, src_buses, dst_buses);
2042
2043         if (plchan->cfg.device_fc)
2044                 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
2045                         PL080_FLOW_PER2MEM_PER;
2046         else
2047                 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
2048                         PL080_FLOW_PER2MEM;
2049
2050         txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
2051                 PL080_CONFIG_TC_IRQ_MASK |
2052                 tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
2053         //printk("this is debug cctl = %x ccfg = %x %s %s %d\n",txd->cctl,txd->ccfg,__FILE__,__func__,__LINE__);
2054
2055         ret = pl08x_request_mux(plchan);
2056         if (ret < 0) {
2057                 pl08x_free_txd(pl08x, txd);
2058                 dev_dbg(&pl08x->adev->dev,
2059                         "unable to mux for transfer on %s due to platform restrictions\n",
2060                         plchan->name);
2061                 return NULL;
2062         }
2063
2064         dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
2065                  plchan->signal, plchan->name);
2066
2067         /* Assign the flow control signal to this channel */
2068         if (direction == DMA_MEM_TO_DEV)
2069                 txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT;
2070         else
2071                 txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
2072
2073         return txd;
2074 }
2075
2076 static int pl08x_tx_add_sg(struct pl08x_txd *txd,
2077                            enum dma_transfer_direction direction,
2078                            dma_addr_t slave_addr,
2079                            dma_addr_t buf_addr,
2080                            unsigned int len)
2081 {
2082         struct pl08x_sg *dsg;
2083
2084         dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
2085         if (!dsg)
2086                 return -ENOMEM;
2087
2088         list_add_tail(&dsg->node, &txd->dsg_list);
2089
2090         dsg->len = len;
2091         if (direction == DMA_MEM_TO_DEV) {
2092                 dsg->src_addr = buf_addr;
2093                 dsg->dst_addr = slave_addr;
2094         } else {
2095                 dsg->src_addr = slave_addr;
2096                 dsg->dst_addr = buf_addr;
2097         }
2098
2099         return 0;
2100 }
2101
2102 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
2103                 struct dma_chan *chan, struct scatterlist *sgl,
2104                 unsigned int sg_len, enum dma_transfer_direction direction,
2105                 unsigned long flags, void *context)
2106 {
2107         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2108         struct pl08x_driver_data *pl08x = plchan->host;
2109         struct pl08x_txd *txd;
2110         struct scatterlist *sg;
2111         int ret, tmp;
2112         dma_addr_t slave_addr;
2113
2114         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
2115                         __func__, sg_dma_len(sgl), plchan->name);
2116
2117         txd = pl08x_init_txd(chan, direction, &slave_addr);
2118         if (!txd)
2119                 return NULL;
2120
2121         for_each_sg(sgl, sg, sg_len, tmp) {
2122                 ret = pl08x_tx_add_sg(txd, direction, slave_addr,
2123                                       sg_dma_address(sg),
2124                                       sg_dma_len(sg));
2125                 /*
2126                 printk("this is debug direction = %x slave_addr = %x addr = %x len = %x %s %s %d\n",
2127                        direction,slave_addr,sg_dma_address(sg),sg_dma_len(sg),
2128                        __FILE__,__func__,__LINE__);
2129                 */
2130                 if (ret) {
2131                         pl08x_release_mux(plchan);
2132                         pl08x_free_txd(pl08x, txd);
2133                         dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
2134                                         __func__);
2135                         return NULL;
2136                 }
2137         }
2138
2139         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
2140         if (!ret) {
2141                 pl08x_release_mux(plchan);
2142                 pl08x_free_txd(pl08x, txd);
2143                 return NULL;
2144         }
2145
2146         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
2147 }
2148
2149 static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
2150                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
2151                 size_t period_len, enum dma_transfer_direction direction,
2152                 unsigned long flags)
2153 {
2154         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2155         struct pl08x_driver_data *pl08x = plchan->host;
2156         struct pl08x_txd *txd;
2157         int ret, tmp;
2158         dma_addr_t slave_addr;
2159
2160         dev_dbg(&pl08x->adev->dev,
2161                 "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n",
2162                 __func__, period_len, buf_len,
2163                 direction == DMA_MEM_TO_DEV ? "to" : "from",
2164                 plchan->name);
2165
2166         txd = pl08x_init_txd(chan, direction, &slave_addr);
2167         if (!txd)
2168                 return NULL;
2169
2170         txd->cyclic = true;
2171         txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
2172         for (tmp = 0; tmp < buf_len; tmp += period_len) {
2173                 ret = pl08x_tx_add_sg(txd, direction, slave_addr,
2174                                       buf_addr + tmp, period_len);
2175                 if (ret) {
2176                         pl08x_release_mux(plchan);
2177                         pl08x_free_txd(pl08x, txd);
2178                         return NULL;
2179                 }
2180         }
2181
2182         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
2183         if (!ret) {
2184                 pl08x_release_mux(plchan);
2185                 pl08x_free_txd(pl08x, txd);
2186                 return NULL;
2187         }
2188
2189         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
2190 }
2191
2192 static int pl08x_config(struct dma_chan *chan,
2193                         struct dma_slave_config *config)
2194 {
2195         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2196         struct pl08x_driver_data *pl08x = plchan->host;
2197
2198         if (!plchan->slave)
2199                 return -EINVAL;
2200
2201         /* Reject definitely invalid configurations */
2202         if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
2203             config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
2204                 return -EINVAL;
2205
2206         if (config->device_fc && pl08x->vd->pl080s) {
2207                 dev_err(&pl08x->adev->dev,
2208                         "%s: PL080S does not support peripheral flow control\n",
2209                         __func__);
2210                 return -EINVAL;
2211         }
2212
2213         /*
2214         printk("this is debug chan = %x chan-id = %d plchan = %x plchan->signal = %d %s %s %d\n",
2215                chan,chan->chan_id,plchan,plchan->signal,__FILE__,__func__,__LINE__);
2216         */
2217         plchan->cfg = *config;
2218
2219         return 0;
2220 }
2221
2222 static int pl08x_terminate_all(struct dma_chan *chan)
2223 {
2224         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2225         struct pl08x_driver_data *pl08x = plchan->host;
2226         unsigned long flags;
2227
2228         spin_lock_irqsave(&plchan->vc.lock, flags);
2229         if (!plchan->phychan && !plchan->at) {
2230                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2231                 return 0;
2232         }
2233
2234         plchan->state = PL08X_CHAN_IDLE;
2235
2236         if (plchan->phychan) {
2237                 /*
2238                  * Mark physical channel as free and free any slave
2239                  * signal
2240                  */
2241                 pl08x_phy_free(plchan);
2242         }
2243         /* Dequeue jobs and free LLIs */
2244         if (plchan->at) {
2245                 vchan_terminate_vdesc(&plchan->at->vd);
2246                 plchan->at = NULL;
2247         }
2248         /* Dequeue jobs not yet fired as well */
2249         pl08x_free_txd_list(pl08x, plchan);
2250
2251         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2252
2253         return 0;
2254 }
2255
2256 static void pl08x_synchronize(struct dma_chan *chan)
2257 {
2258         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2259
2260         printk("this is debug %s %s %d \n",__FILE__,__func__,__LINE__);
2261         vchan_synchronize(&plchan->vc);
2262 }
2263
2264 static int pl08x_pause(struct dma_chan *chan)
2265 {
2266         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2267         unsigned long flags;
2268
2269         /*
2270          * Anything succeeds on channels with no physical allocation and
2271          * no queued transfers.
2272          */
2273         printk("this is debug %s %s %d \n",__FILE__,__func__,__LINE__);
2274         spin_lock_irqsave(&plchan->vc.lock, flags);
2275         if (!plchan->phychan && !plchan->at) {
2276                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2277                 return 0;
2278         }
2279
2280         pl08x_pause_phy_chan(plchan->phychan);
2281         plchan->state = PL08X_CHAN_PAUSED;
2282
2283         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2284
2285         return 0;
2286 }
2287
2288 static int pl08x_resume(struct dma_chan *chan)
2289 {
2290         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2291         unsigned long flags;
2292
2293         /*
2294          * Anything succeeds on channels with no physical allocation and
2295          * no queued transfers.
2296          */
2297         printk("this is debug %s %s %d \n",__FILE__,__func__,__LINE__);
2298         spin_lock_irqsave(&plchan->vc.lock, flags);
2299         if (!plchan->phychan && !plchan->at) {
2300                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2301                 return 0;
2302         }
2303
2304         pl08x_resume_phy_chan(plchan->phychan);
2305         plchan->state = PL08X_CHAN_RUNNING;
2306
2307         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2308
2309         return 0;
2310 }
2311 #if 0
2312 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
2313 {
2314         struct pl08x_dma_chan *plchan;
2315         char *name = chan_id;
2316
2317         /* Reject channels for devices not bound to this driver */
2318         if (chan->device->dev->driver != &pl08x_amba_driver.drv)
2319                 return false;
2320
2321         plchan = to_pl08x_chan(chan);
2322
2323         /* Check that the channel is not taken! */
2324         if (!strcmp(plchan->name, name))
2325                 return true;
2326
2327         return false;
2328 }
2329 EXPORT_SYMBOL_GPL(pl08x_filter_id);
2330 #endif
2331 static bool pl08x_filter_fn(struct dma_chan *chan, void *chan_id)
2332 {
2333         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2334
2335         return plchan->cd == chan_id;
2336 }
2337
2338 /*
2339  * Just check that the device is there and active
2340  * TODO: turn this bit on/off depending on the number of physical channels
2341  * actually used, if it is zero... well shut it off. That will save some
2342  * power. Cut the clock at the same time.
2343  */
2344 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
2345 {
2346         /* The Nomadik variant does not have the config register */
2347         if (pl08x->vd->nomadik)
2348                 return;
2349         /* The FTDMAC020 variant does this in another register */
2350         if (pl08x->vd->ftdmac020) {
2351                 writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
2352                 return;
2353         }
2354         writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
2355 }
2356
2357 static irqreturn_t pl08x_irq(int irq, void *dev)
2358 {
2359         struct pl08x_driver_data *pl08x = dev;
2360         u32 mask = 0, err, tc, i;
2361
2362         /* check & clear - ERR & TC interrupts */
2363         err = readl(pl08x->base + PL080_ERR_STATUS);
2364         if (err) {
2365                 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
2366                         __func__, err);
2367                 writel(err, pl08x->base + PL080_ERR_CLEAR);
2368         }
2369         tc = readl(pl08x->base + PL080_TC_STATUS);
2370         if (tc) {
2371                 writel(tc, pl08x->base + PL080_TC_CLEAR);
2372         }
2373
2374         if (!err && !tc) {
2375                 return IRQ_NONE;
2376         }
2377
2378         for (i = 0; i < pl08x->vd->channels; i++) {
2379                 if ((BIT(i) & err) || (BIT(i) & tc)) {
2380                         /* Locate physical channel */
2381                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
2382                         struct pl08x_dma_chan *plchan = phychan->serving;
2383                         struct pl08x_txd *tx;
2384
2385                         if (!plchan) {
2386                                 dev_err(&pl08x->adev->dev,
2387                                         "%s Error TC interrupt on unused channel: 0x%08x\n",
2388                                         __func__, i);
2389                                 continue;
2390                         }
2391
2392                         spin_lock(&plchan->vc.lock);
2393                         tx = plchan->at;
2394                         if (tx && tx->cyclic) {
2395                                 vchan_cyclic_callback(&tx->vd);
2396                         } else if (tx) {
2397                                 plchan->at = NULL;
2398                                 /*
2399                                  * This descriptor is done, release its mux
2400                                  * reservation.
2401                                  */
2402                                 pl08x_release_mux(plchan);
2403                                 tx->done = true;
2404                                 vchan_cookie_complete(&tx->vd);
2405
2406                                 /*
2407                                  * And start the next descriptor (if any),
2408                                  * otherwise free this channel.
2409                                  */
2410                                 if (vchan_next_desc(&plchan->vc))
2411                                         pl08x_start_next_txd(plchan);
2412                                 else
2413                                         pl08x_phy_free(plchan);
2414                         }
2415                         spin_unlock(&plchan->vc.lock);
2416
2417                         mask |= BIT(i);
2418                 }
2419         }
2420
2421         return mask ? IRQ_HANDLED : IRQ_NONE;
2422 }
2423
2424 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
2425 {
2426         chan->slave = true;
2427         chan->name = chan->cd->bus_id;
2428         chan->cfg.src_addr = chan->cd->addr;
2429         chan->cfg.dst_addr = chan->cd->addr;
2430 }
2431
2432 /*
2433  * Initialise the DMAC memcpy/slave channels.
2434  * Make a local wrapper to hold required data
2435  */
2436 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
2437                 struct dma_device *dmadev, unsigned int channels, bool slave)
2438 {
2439         struct pl08x_dma_chan *chan;
2440         int i;
2441
2442         INIT_LIST_HEAD(&dmadev->channels);
2443
2444         /*
2445          * Register as many many memcpy as we have physical channels,
2446          * we won't always be able to use all but the code will have
2447          * to cope with that situation.
2448          */
2449         for (i = 0; i < channels; i++) {
2450                 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
2451                 if (!chan)
2452                         return -ENOMEM;
2453
2454                 chan->host = pl08x;
2455                 chan->state = PL08X_CHAN_IDLE;
2456                 chan->signal = -1;
2457
2458                 if (slave) {
2459                         chan->cd = &pl08x->pd->slave_channels[i];
2460                         /*
2461                          * Some implementations have muxed signals, whereas some
2462                          * use a mux in front of the signals and need dynamic
2463                          * assignment of signals.
2464                          */
2465                         chan->signal = i;
2466                         pl08x_dma_slave_init(chan);
2467                 } else {
2468                         chan->cd = kzalloc(sizeof(*chan->cd), GFP_KERNEL);
2469                         if (!chan->cd) {
2470                                 kfree(chan);
2471                                 return -ENOMEM;
2472                         }
2473                         chan->cd->bus_id = "memcpy";
2474                         chan->cd->periph_buses = pl08x->pd->mem_buses;
2475                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
2476                         if (!chan->name) {
2477                                 kfree(chan->cd);
2478                                 kfree(chan);
2479                                 return -ENOMEM;
2480                         }
2481                 }
2482                 dev_dbg(&pl08x->adev->dev,
2483                          "initialize virtual channel \"%s\"\n",
2484                          chan->name);
2485
2486                 chan->vc.desc_free = pl08x_desc_free;
2487                 vchan_init(&chan->vc, dmadev);
2488         }
2489         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
2490                  i, slave ? "slave" : "memcpy");
2491         return i;
2492 }
2493
2494 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
2495 {
2496         struct pl08x_dma_chan *chan = NULL;
2497         struct pl08x_dma_chan *next;
2498
2499         list_for_each_entry_safe(chan,
2500                                  next, &dmadev->channels, vc.chan.device_node) {
2501                 list_del(&chan->vc.chan.device_node);
2502                 kfree(chan);
2503         }
2504 }
2505
2506 #ifdef CONFIG_DEBUG_FS
2507 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
2508 {
2509         switch (state) {
2510         case PL08X_CHAN_IDLE:
2511                 return "idle";
2512         case PL08X_CHAN_RUNNING:
2513                 return "running";
2514         case PL08X_CHAN_PAUSED:
2515                 return "paused";
2516         case PL08X_CHAN_WAITING:
2517                 return "waiting";
2518         default:
2519                 break;
2520         }
2521         return "UNKNOWN STATE";
2522 }
2523
2524 static int pl08x_debugfs_show(struct seq_file *s, void *data)
2525 {
2526         struct pl08x_driver_data *pl08x = s->private;
2527         struct pl08x_dma_chan *chan;
2528         struct pl08x_phy_chan *ch;
2529         unsigned long flags;
2530         int i;
2531
2532         seq_printf(s, "PL08x physical channels:\n");
2533         seq_printf(s, "CHANNEL:\tUSER:\n");
2534         seq_printf(s, "--------\t-----\n");
2535         for (i = 0; i < pl08x->vd->channels; i++) {
2536                 struct pl08x_dma_chan *virt_chan;
2537
2538                 ch = &pl08x->phy_chans[i];
2539
2540                 spin_lock_irqsave(&ch->lock, flags);
2541                 virt_chan = ch->serving;
2542
2543                 seq_printf(s, "%d\t\t%s%s\n",
2544                            ch->id,
2545                            virt_chan ? virt_chan->name : "(none)",
2546                            ch->locked ? " LOCKED" : "");
2547
2548                 spin_unlock_irqrestore(&ch->lock, flags);
2549         }
2550
2551         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
2552         seq_printf(s, "CHANNEL:\tSTATE:\n");
2553         seq_printf(s, "--------\t------\n");
2554         list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
2555                 seq_printf(s, "%s\t\t%s\n", chan->name,
2556                            pl08x_state_str(chan->state));
2557         }
2558
2559         if (pl08x->has_slave) {
2560                 seq_printf(s, "\nPL08x virtual slave channels:\n");
2561                 seq_printf(s, "CHANNEL:\tSTATE:\n");
2562                 seq_printf(s, "--------\t------\n");
2563                 list_for_each_entry(chan, &pl08x->slave.channels,
2564                                     vc.chan.device_node) {
2565                         seq_printf(s, "%s\t\t%s\n", chan->name,
2566                                    pl08x_state_str(chan->state));
2567                 }
2568         }
2569
2570         return 0;
2571 }
2572
2573 DEFINE_SHOW_ATTRIBUTE(pl08x_debugfs);
2574
2575 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2576 {
2577         /* Expose a simple debugfs interface to view all clocks */
2578         debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
2579                             NULL, pl08x, &pl08x_debugfs_fops);
2580 }
2581
2582 #else
2583 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2584 {
2585 }
2586 #endif
2587
2588 #ifdef CONFIG_OF
2589 static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x,
2590                                          u32 id)
2591 {
2592         struct pl08x_dma_chan *chan;
2593
2594         /* Trying to get a slave channel from something with no slave support */
2595         if (!pl08x->has_slave)
2596                 return NULL;
2597
2598         list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
2599                 if (chan->signal == id)
2600                         return &chan->vc.chan;
2601         }
2602
2603         return NULL;
2604 }
2605
2606 static struct dma_chan *pl08x_of_xlate(struct of_phandle_args *dma_spec,
2607                                        struct of_dma *ofdma)
2608 {
2609         struct pl08x_driver_data *pl08x = ofdma->of_dma_data;
2610         struct dma_chan *dma_chan;
2611         struct pl08x_dma_chan *plchan;
2612
2613         if (!pl08x)
2614                 return NULL;
2615
2616         if (dma_spec->args_count != 2) {
2617                 dev_err(&pl08x->adev->dev,
2618                         "DMA channel translation requires two cells\n");
2619                 return NULL;
2620         }
2621
2622         dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);
2623         if (!dma_chan) {
2624                 dev_err(&pl08x->adev->dev,
2625                         "DMA slave channel not found\n");
2626                 return NULL;
2627         }
2628
2629         plchan = to_pl08x_chan(dma_chan);
2630         dev_dbg(&pl08x->adev->dev,
2631                 "translated channel for signal %d\n",
2632                 dma_spec->args[0]);
2633
2634         /* Augment channel data for applicable AHB buses */
2635         plchan->cd->periph_buses = dma_spec->args[1];
2636         return dma_get_slave_channel(dma_chan);
2637 }
2638
2639 static int pl08x_of_probe(struct platform_device *adev,
2640                           struct pl08x_driver_data *pl08x,
2641                           struct device_node *np)
2642 {
2643         struct pl08x_platform_data *pd;
2644         struct pl08x_channel_data *chanp = NULL;
2645         u32 val;
2646         int ret;
2647         int i;
2648
2649         pd = devm_kzalloc(&adev->dev, sizeof(*pd), GFP_KERNEL);
2650         if (!pd)
2651                 return -ENOMEM;
2652
2653         /* Eligible bus masters for fetching LLIs */
2654         if (of_property_read_bool(np, "lli-bus-interface-ahb1"))
2655                 pd->lli_buses |= PL08X_AHB1;
2656         if (of_property_read_bool(np, "lli-bus-interface-ahb2"))
2657                 pd->lli_buses |= PL08X_AHB2;
2658         if (!pd->lli_buses) {
2659                 dev_info(&adev->dev, "no bus masters for LLIs stated, assume all\n");
2660                 pd->lli_buses |= PL08X_AHB1 | PL08X_AHB2;
2661         }
2662
2663         /* Eligible bus masters for memory access */
2664         if (of_property_read_bool(np, "mem-bus-interface-ahb1"))
2665                 pd->mem_buses |= PL08X_AHB1;
2666         if (of_property_read_bool(np, "mem-bus-interface-ahb2"))
2667                 pd->mem_buses |= PL08X_AHB2;
2668         if (!pd->mem_buses) {
2669                 dev_info(&adev->dev, "no bus masters for memory stated, assume all\n");
2670                 pd->mem_buses |= PL08X_AHB1 | PL08X_AHB2;
2671         }
2672
2673         /* Parse the memcpy channel properties */
2674         ret = of_property_read_u32(np, "memcpy-burst-size", &val);
2675         if (ret) {
2676                 dev_info(&adev->dev, "no memcpy burst size specified, using 1 byte\n");
2677                 val = 1;
2678         }
2679         switch (val) {
2680         default:
2681                 dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");
2682                 fallthrough;
2683         case 1:
2684                 pd->memcpy_burst_size = PL08X_BURST_SZ_1;
2685                 break;
2686         case 4:
2687                 pd->memcpy_burst_size = PL08X_BURST_SZ_4;
2688                 break;
2689         case 8:
2690                 pd->memcpy_burst_size = PL08X_BURST_SZ_8;
2691                 break;
2692         case 16:
2693                 pd->memcpy_burst_size = PL08X_BURST_SZ_16;
2694                 break;
2695         case 32:
2696                 pd->memcpy_burst_size = PL08X_BURST_SZ_32;
2697                 break;
2698         case 64:
2699                 pd->memcpy_burst_size = PL08X_BURST_SZ_64;
2700                 break;
2701         case 128:
2702                 pd->memcpy_burst_size = PL08X_BURST_SZ_128;
2703                 break;
2704         case 256:
2705                 pd->memcpy_burst_size = PL08X_BURST_SZ_256;
2706                 break;
2707         }
2708
2709         ret = of_property_read_u32(np, "memcpy-bus-width", &val);
2710         if (ret) {
2711                 dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n");
2712                 val = 8;
2713         }
2714         switch (val) {
2715         default:
2716                 dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");
2717                 fallthrough;
2718         case 8:
2719                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS;
2720                 break;
2721         case 16:
2722                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_16_BITS;
2723                 break;
2724         case 32:
2725                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS;
2726                 break;
2727         }
2728
2729         /*
2730          * Allocate channel data for all possible slave channels (one
2731          * for each possible signal), channels will then be allocated
2732          * for a device and have it's AHB interfaces set up at
2733          * translation time.
2734          */
2735         if (pl08x->vd->signals) {
2736                 chanp = devm_kcalloc(&adev->dev,
2737                                      pl08x->vd->signals,
2738                                      sizeof(struct pl08x_channel_data),
2739                                      GFP_KERNEL);
2740                 if (!chanp)
2741                         return -ENOMEM;
2742
2743                 pd->slave_channels = chanp;
2744                 for (i = 0; i < pl08x->vd->signals; i++) {
2745                         /*
2746                          * chanp->periph_buses will be assigned at translation
2747                          */
2748                         chanp->bus_id = kasprintf(GFP_KERNEL, "slave%d", i);
2749                         chanp++;
2750                 }
2751                 pd->num_slave_channels = pl08x->vd->signals;
2752         }
2753
2754         pl08x->pd = pd;
2755
2756         return of_dma_controller_register(adev->dev.of_node, pl08x_of_xlate,
2757                                           pl08x);
2758 }
2759 #else
2760 static inline int pl08x_of_probe(struct platform_device *adev,
2761                                  struct pl08x_driver_data *pl08x,
2762                                  struct device_node *np)
2763 {
2764         return -EINVAL;
2765 }
2766 #endif
2767
2768 static int pl08x_probe(struct platform_device *adev) //, const struct amba_id *id)
2769 {
2770         struct pl08x_driver_data *pl08x;
2771         struct vendor_data *vd;
2772         struct device_node *np = adev->dev.of_node;
2773         struct resource *res;
2774         u32 tsfr_size;
2775         int irq, ret = 0;
2776         int i;
2777
2778         //printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2779 #if 0
2780         ret = amba_request_regions(adev, NULL);
2781         if (ret){
2782                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2783                 return ret;
2784         }
2785 #endif
2786         /* Ensure that we can do DMA */
2787         ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2788         if (ret){
2789                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2790                 return ret;
2791         }
2792
2793         /* Create the driver state holder */
2794         pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
2795         if (!pl08x) {
2796                 ret = -ENOMEM;
2797                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2798                 return ret;
2799         }
2800
2801         /* Assign useful pointers to the driver state */
2802         pl08x->adev = adev;
2803         vd = of_device_get_match_data(&adev->dev);
2804         if(!vd)
2805                 return -ENODEV;
2806         pl08x->vd = vd;
2807
2808         res = platform_get_resource_byname(adev, IORESOURCE_MEM, "sec_dma");
2809         pl08x->base = devm_ioremap_resource(&adev->dev, res);
2810         if (!pl08x->base) {
2811                 ret = -ENOMEM;
2812                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2813                 goto out_no_ioremap;
2814         }
2815
2816         if (vd->ftdmac020) {
2817                 u32 val;
2818
2819                 val = readl(pl08x->base + FTDMAC020_REVISION);
2820                 dev_dbg(&pl08x->adev->dev, "FTDMAC020 %d.%d rel %d\n",
2821                          (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
2822                 val = readl(pl08x->base + FTDMAC020_FEATURE);
2823                 dev_dbg(&pl08x->adev->dev, "FTDMAC020 %d channels, "
2824                          "%s built-in bridge, %s, %s linked lists\n",
2825                          (val >> 12) & 0x0f,
2826                          (val & BIT(10)) ? "no" : "has",
2827                          (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0",
2828                          (val & BIT(8)) ? "supports" : "does not support");
2829
2830                 /* Vendor data from feature register */
2831                 if (!(val & BIT(8)))
2832                         dev_warn(&pl08x->adev->dev,
2833                                  "linked lists not supported, required\n");
2834                 vd->channels = (val >> 12) & 0x0f;
2835                 vd->dualmaster = !!(val & BIT(9));
2836         }
2837
2838         /* Initialize memcpy engine */
2839         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
2840         pl08x->memcpy.dev = &adev->dev;
2841         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
2842         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
2843         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
2844         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
2845         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
2846         pl08x->memcpy.device_config = pl08x_config;
2847         pl08x->memcpy.device_pause = pl08x_pause;
2848         pl08x->memcpy.device_resume = pl08x_resume;
2849         pl08x->memcpy.device_terminate_all = pl08x_terminate_all;
2850         pl08x->memcpy.device_synchronize = pl08x_synchronize;
2851         pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2852         pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2853         pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM);
2854         pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2855         if (vd->ftdmac020)
2856                 pl08x->memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2857
2858
2859         /*
2860          * Initialize slave engine, if the block has no signals, that means
2861          * we have no slave support.
2862          */
2863         if (vd->signals) {
2864                 pl08x->has_slave = true;
2865                 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
2866                 dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
2867                 pl08x->slave.dev = &adev->dev;
2868                 pl08x->slave.device_free_chan_resources =
2869                         pl08x_free_chan_resources;
2870                 pl08x->slave.device_prep_dma_interrupt =
2871                         pl08x_prep_dma_interrupt;
2872                 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
2873                 pl08x->slave.device_issue_pending = pl08x_issue_pending;
2874                 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
2875                 pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
2876                 pl08x->slave.device_config = pl08x_config;
2877                 pl08x->slave.device_pause = pl08x_pause;
2878                 pl08x->slave.device_resume = pl08x_resume;
2879                 pl08x->slave.device_terminate_all = pl08x_terminate_all;
2880                 pl08x->slave.device_synchronize = pl08x_synchronize;
2881                 pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2882                 pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2883                 pl08x->slave.directions =
2884                         BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2885                 pl08x->slave.residue_granularity =
2886                         DMA_RESIDUE_GRANULARITY_SEGMENT;
2887         }
2888
2889         /* Get the platform data */
2890         pl08x->pd = dev_get_platdata(&adev->dev);
2891         if (!pl08x->pd) {
2892                 if (np) {
2893                         ret = pl08x_of_probe(adev, pl08x, np);
2894                         if (ret) {
2895                                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2896                                 goto out_no_platdata;
2897                         }
2898                 } else {
2899                         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2900                         dev_err(&adev->dev, "no platform data supplied\n");
2901                         ret = -EINVAL;
2902                         goto out_no_platdata;
2903                 }
2904         } else {
2905                 pl08x->slave.filter.map = pl08x->pd->slave_map;
2906                 pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len;
2907                 pl08x->slave.filter.fn = pl08x_filter_fn;
2908         }
2909
2910         /* By default, AHB1 only.  If dualmaster, from platform */
2911         pl08x->lli_buses = PL08X_AHB1;
2912         pl08x->mem_buses = PL08X_AHB1;
2913         if (pl08x->vd->dualmaster) {
2914                 pl08x->lli_buses = pl08x->pd->lli_buses;
2915                 pl08x->mem_buses = pl08x->pd->mem_buses;
2916         }
2917
2918         if (vd->pl080s)
2919                 pl08x->lli_words = PL080S_LLI_WORDS;
2920         else
2921                 pl08x->lli_words = PL080_LLI_WORDS;
2922         tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32);
2923
2924         /* A DMA memory pool for LLIs, align on 1-byte boundary */
2925         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
2926                                                 tsfr_size, PL08X_ALIGN, 0);
2927         if (!pl08x->pool) {
2928                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2929                 ret = -ENOMEM;
2930                 goto out_no_lli_pool;
2931         }
2932
2933         /* Turn on the PL08x */
2934         pl08x_ensure_on(pl08x);
2935
2936         /* Clear any pending interrupts */
2937         if (vd->ftdmac020)
2938                 /* This variant has error IRQs in bits 16-19 */
2939                 writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
2940         else
2941                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2942         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2943
2944         /* Attach the interrupt handler */
2945         irq = platform_get_irq(adev, 0);
2946         if (irq < 0) {
2947                 dev_err(&adev->dev, "Cannot get IRQ resource\n");
2948                 return irq;
2949         }
2950
2951         ret = request_irq(irq, pl08x_irq, 0, DRIVER_NAME, pl08x);
2952         if (ret) {
2953                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2954                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2955                         __func__, irq);
2956                 goto out_no_irq;
2957         }
2958
2959         /* Initialize physical channels */
2960         pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2961                         GFP_KERNEL);
2962         if (!pl08x->phy_chans) {
2963                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
2964                 ret = -ENOMEM;
2965                 goto out_no_phychans;
2966         }
2967
2968         for (i = 0; i < vd->channels; i++) {
2969                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2970
2971                 ch->id = i;
2972                 ch->base = pl08x->base + PL080_Cx_BASE(i);
2973                 if (vd->ftdmac020) {
2974                         /* FTDMA020 has a special channel busy register */
2975                         ch->reg_busy = ch->base + FTDMAC020_CH_BUSY;
2976                         ch->reg_config = ch->base + FTDMAC020_CH_CFG;
2977                         ch->reg_control = ch->base + FTDMAC020_CH_CSR;
2978                         ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR;
2979                         ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR;
2980                         ch->reg_lli = ch->base + FTDMAC020_CH_LLP;
2981                         ch->ftdmac020 = true;
2982                 } else {
2983                         printk("this is debug i = %d  ch->base = %x  %s %s %d\n",i,ch->base,__FILE__,__func__,__LINE__);
2984                         ch->reg_config = ch->base + vd->config_offset;
2985                         ch->reg_control = ch->base + PL080_CH_CONTROL;
2986                         ch->reg_src = ch->base + PL080_CH_SRC_ADDR;
2987                         ch->reg_dst = ch->base + PL080_CH_DST_ADDR;
2988                         ch->reg_lli = ch->base + PL080_CH_LLI;
2989                 }
2990                 if (vd->pl080s)
2991                         ch->pl080s = true;
2992
2993                 spin_lock_init(&ch->lock);
2994
2995                 /*
2996                  * Nomadik variants can have channels that are locked
2997                  * down for the secure world only. Lock up these channels
2998                  * by perpetually serving a dummy virtual channel.
2999                  */
3000                 if (vd->nomadik) {
3001                         u32 val;
3002
3003                         val = readl(ch->reg_config);
3004                         if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
3005                                 dev_dbg(&adev->dev, "physical channel %d reserved for secure access only\n", i);
3006                                 ch->locked = true;
3007                         }
3008                 }
3009
3010                 //dev_dbg(&adev->dev, "physical channel %d is %s\n",
3011                 dev_dbg(&adev->dev, "physical channel %d is %s\n",
3012                         i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
3013         }
3014
3015         /* Register as many memcpy channels as there are physical channels */
3016         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
3017                                               pl08x->vd->channels, false);
3018         if (ret <= 0) {
3019                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3020                 dev_warn(&pl08x->adev->dev,
3021                          "%s failed to enumerate memcpy channels - %d\n",
3022                          __func__, ret);
3023                 goto out_no_memcpy;
3024         }
3025
3026         /* Register slave channels */
3027         if (pl08x->has_slave) {
3028                 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
3029                                         pl08x->pd->num_slave_channels, true);
3030                 if (ret < 0) {
3031                         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3032                         dev_warn(&pl08x->adev->dev,
3033                                  "%s failed to enumerate slave channels - %d\n",
3034                                  __func__, ret);
3035                         goto out_no_slave;
3036                 }
3037         }
3038
3039         ret = dma_async_device_register(&pl08x->memcpy);
3040         if (ret) {
3041                 printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3042                 dev_warn(&pl08x->adev->dev,
3043                         "%s failed to register memcpy as an async device - %d\n",
3044                         __func__, ret);
3045                 goto out_no_memcpy_reg;
3046         }
3047
3048         if (pl08x->has_slave) {
3049                 ret = dma_async_device_register(&pl08x->slave);
3050                 if (ret) {
3051                         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3052                         dev_warn(&pl08x->adev->dev,
3053                         "%s failed to register slave as an async device - %d\n",
3054                         __func__, ret);
3055                         goto out_no_slave_reg;
3056                 }
3057         }
3058
3059         platform_set_drvdata(adev, pl08x);
3060         init_pl08x_debugfs(pl08x);
3061         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3062         {
3063                 int loop;
3064
3065                 for (loop = 0xfe0;loop <= 0xffc; loop += 4) {
3066                         dev_dbg(&pl08x->adev->dev, "periphid[0x%x] = %x ",
3067                                  loop,readl(pl08x->base + loop));
3068                 }
3069         }
3070         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3071         dev_dbg(&pl08x->adev->dev, "DMA: PL080  at 0x%08llx irq %d\n",
3072                  (unsigned long long)res->start, irq);
3073
3074         return 0;
3075
3076 out_no_slave_reg:
3077         dma_async_device_unregister(&pl08x->memcpy);
3078 out_no_memcpy_reg:
3079         if (pl08x->has_slave)
3080                 pl08x_free_virtual_channels(&pl08x->slave);
3081 out_no_slave:
3082         pl08x_free_virtual_channels(&pl08x->memcpy);
3083 out_no_memcpy:
3084         kfree(pl08x->phy_chans);
3085 out_no_phychans:
3086         free_irq(irq, pl08x);
3087 out_no_irq:
3088         dma_pool_destroy(pl08x->pool);
3089 out_no_lli_pool:
3090 out_no_platdata:
3091         iounmap(pl08x->base);
3092 out_no_ioremap:
3093         kfree(pl08x);
3094         //out_no_pl08x:
3095         //amba_release_regions(adev);
3096         printk("this is debug %s %s %d\n",__FILE__,__func__,__LINE__);
3097         return ret;
3098 }
3099
3100 /* PL080 has 8 channels and the PL080 have just 2 */
3101 static struct vendor_data vendor_pl080 = {
3102         .config_offset = PL080_CH_CONFIG,
3103         .channels = 8,
3104         .signals = 16,
3105         .dualmaster = true,
3106         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3107 };
3108 #if 0
3109 static struct vendor_data vendor_nomadik = {
3110         .config_offset = PL080_CH_CONFIG,
3111         .channels = 8,
3112         .signals = 32,
3113         .dualmaster = true,
3114         .nomadik = true,
3115         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3116 };
3117
3118 static struct vendor_data vendor_pl080s = {
3119         .config_offset = PL080S_CH_CONFIG,
3120         .channels = 8,
3121         .signals = 32,
3122         .pl080s = true,
3123         .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
3124 };
3125
3126 static struct vendor_data vendor_pl081 = {
3127         .config_offset = PL080_CH_CONFIG,
3128         .channels = 2,
3129         .signals = 16,
3130         .dualmaster = false,
3131         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3132 };
3133
3134 static struct vendor_data vendor_ftdmac020 = {
3135         .config_offset = PL080_CH_CONFIG,
3136         .ftdmac020 = true,
3137         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3138 };
3139
3140 static const struct amba_id pl08x_ids[] = {
3141         /* Samsung PL080S variant */
3142         {
3143                 .id     = 0x0a141080,
3144                 .mask   = 0xffffffff,
3145                 .data   = &vendor_pl080s,
3146         },
3147         /* PL080 */
3148         {
3149                 .id     = 0x00041080,
3150                 .mask   = 0x000fffff,
3151                 .data   = &vendor_pl080,
3152         },
3153         /* PL081 */
3154         {
3155                 .id     = 0x00041081,
3156                 .mask   = 0x000fffff,
3157                 .data   = &vendor_pl081,
3158         },
3159         /* Nomadik 8815 PL080 variant */
3160         {
3161                 .id     = 0x00280080,
3162                 .mask   = 0x00ffffff,
3163                 .data   = &vendor_nomadik,
3164         },
3165         /* Faraday Technology FTDMAC020 */
3166         {
3167                 .id     = 0x0003b080,
3168                 .mask   = 0x000fffff,
3169                 .data   = &vendor_ftdmac020,
3170         },
3171         { 0, 0 },
3172 };
3173
3174 MODULE_DEVICE_TABLE(amba, pl08x_ids);
3175
3176 static struct amba_driver pl08x_amba_driver = {
3177         .drv.name       = DRIVER_NAME,
3178         .id_table       = pl08x_ids,
3179         .probe          = pl08x_probe,
3180 };
3181 #endif
3182 static const struct of_device_id vic7110_dma_ids[] = {
3183         { .compatible = "starfive,pl080", .data = &vendor_pl080},
3184         {},
3185 };
3186 MODULE_DEVICE_TABLE(of, vic7110_dma_ids);
3187
3188 static struct platform_driver vic7110_pl08x_driver = {
3189         .probe  = pl08x_probe,
3190         .driver = {
3191                 .name           = DRIVER_NAME,
3192                 .of_match_table = vic7110_dma_ids,
3193         },
3194 };
3195
3196 module_platform_driver(vic7110_pl08x_driver);
3197
3198 MODULE_LICENSE("GPL");
3199 MODULE_AUTHOR("Huan Feng <huan.feng@starfivetech.com>");
3200 MODULE_DESCRIPTION("Starfive VIC7110 CRYP DMA driver");