2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2009 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
24 * This driver supports an Intel I/OAT DMA engine, which does asynchronous
28 #include <linux/init.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/interrupt.h>
33 #include <linux/dmaengine.h>
34 #include <linux/delay.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/workqueue.h>
37 #include <linux/prefetch.h>
38 #include <linux/i7300_idle.h>
40 #include "registers.h"
43 #include "../dmaengine.h"
45 int ioat_pending_level = 4;
46 module_param(ioat_pending_level, int, 0644);
47 MODULE_PARM_DESC(ioat_pending_level,
48 "high-water mark for pushing ioat descriptors (default: 4)");
50 /* internal functions */
51 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
52 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
55 * ioat_dma_do_interrupt - handler used for single vector interrupt mode
57 * @data: interrupt data
59 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
61 struct ioatdma_device *instance = data;
62 struct ioat_chan_common *chan;
63 unsigned long attnstatus;
67 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
69 if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
72 if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
73 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
77 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
78 for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
79 chan = ioat_chan_by_index(instance, bit);
80 tasklet_schedule(&chan->cleanup_task);
83 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
88 * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
90 * @data: interrupt data
92 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
94 struct ioat_chan_common *chan = data;
96 tasklet_schedule(&chan->cleanup_task);
101 /* common channel initialization */
102 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
104 struct dma_device *dma = &device->common;
105 struct dma_chan *c = &chan->common;
106 unsigned long data = (unsigned long) c;
108 chan->device = device;
109 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
110 spin_lock_init(&chan->cleanup_lock);
111 chan->common.device = dma;
112 dma_cookie_init(&chan->common);
113 list_add_tail(&chan->common.device_node, &dma->channels);
114 device->idx[idx] = chan;
115 init_timer(&chan->timer);
116 chan->timer.function = device->timer_fn;
117 chan->timer.data = data;
118 tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
119 tasklet_disable(&chan->cleanup_task);
123 * ioat1_dma_enumerate_channels - find and initialize the device's channels
124 * @device: the device to be enumerated
126 static int ioat1_enumerate_channels(struct ioatdma_device *device)
131 struct ioat_dma_chan *ioat;
132 struct device *dev = &device->pdev->dev;
133 struct dma_device *dma = &device->common;
135 INIT_LIST_HEAD(&dma->channels);
136 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
137 dma->chancnt &= 0x1f; /* bits [4:0] valid */
138 if (dma->chancnt > ARRAY_SIZE(device->idx)) {
139 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
140 dma->chancnt, ARRAY_SIZE(device->idx));
141 dma->chancnt = ARRAY_SIZE(device->idx);
143 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
144 xfercap_scale &= 0x1f; /* bits [4:0] valid */
145 xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
146 dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
148 #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
149 if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
152 for (i = 0; i < dma->chancnt; i++) {
153 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
157 ioat_init_channel(device, &ioat->base, i);
158 ioat->xfercap = xfercap;
159 spin_lock_init(&ioat->desc_lock);
160 INIT_LIST_HEAD(&ioat->free_desc);
161 INIT_LIST_HEAD(&ioat->used_desc);
168 * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
170 * @chan: DMA channel handle
173 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
175 void __iomem *reg_base = ioat->base.reg_base;
177 dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
178 __func__, ioat->pending);
180 writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
183 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
185 struct ioat_dma_chan *ioat = to_ioat_chan(chan);
187 if (ioat->pending > 0) {
188 spin_lock_bh(&ioat->desc_lock);
189 __ioat1_dma_memcpy_issue_pending(ioat);
190 spin_unlock_bh(&ioat->desc_lock);
195 * ioat1_reset_channel - restart a channel
196 * @ioat: IOAT DMA channel handle
198 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
200 struct ioat_chan_common *chan = &ioat->base;
201 void __iomem *reg_base = chan->reg_base;
202 u32 chansts, chanerr;
204 dev_warn(to_dev(chan), "reset\n");
205 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
206 chansts = *chan->completion & IOAT_CHANSTS_STATUS;
208 dev_err(to_dev(chan),
209 "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
210 chan_num(chan), chansts, chanerr);
211 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
215 * whack it upside the head with a reset
216 * and wait for things to settle out.
217 * force the pending count to a really big negative
218 * to make sure no one forces an issue_pending
219 * while we're waiting.
222 ioat->pending = INT_MIN;
223 writeb(IOAT_CHANCMD_RESET,
224 reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
225 set_bit(IOAT_RESET_PENDING, &chan->state);
226 mod_timer(&chan->timer, jiffies + RESET_DELAY);
229 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
231 struct dma_chan *c = tx->chan;
232 struct ioat_dma_chan *ioat = to_ioat_chan(c);
233 struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
234 struct ioat_chan_common *chan = &ioat->base;
235 struct ioat_desc_sw *first;
236 struct ioat_desc_sw *chain_tail;
239 spin_lock_bh(&ioat->desc_lock);
240 /* cookie incr and addition to used_list must be atomic */
241 cookie = dma_cookie_assign(tx);
242 dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
244 /* write address into NextDescriptor field of last desc in chain */
245 first = to_ioat_desc(desc->tx_list.next);
246 chain_tail = to_ioat_desc(ioat->used_desc.prev);
247 /* make descriptor updates globally visible before chaining */
249 chain_tail->hw->next = first->txd.phys;
250 list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
251 dump_desc_dbg(ioat, chain_tail);
252 dump_desc_dbg(ioat, first);
254 if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
255 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
257 ioat->active += desc->hw->tx_cnt;
258 ioat->pending += desc->hw->tx_cnt;
259 if (ioat->pending >= ioat_pending_level)
260 __ioat1_dma_memcpy_issue_pending(ioat);
261 spin_unlock_bh(&ioat->desc_lock);
267 * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
268 * @ioat: the channel supplying the memory pool for the descriptors
269 * @flags: allocation flags
271 static struct ioat_desc_sw *
272 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
274 struct ioat_dma_descriptor *desc;
275 struct ioat_desc_sw *desc_sw;
276 struct ioatdma_device *ioatdma_device;
279 ioatdma_device = ioat->base.device;
280 desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
284 desc_sw = kzalloc(sizeof(*desc_sw), flags);
285 if (unlikely(!desc_sw)) {
286 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
290 memset(desc, 0, sizeof(*desc));
292 INIT_LIST_HEAD(&desc_sw->tx_list);
293 dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
294 desc_sw->txd.tx_submit = ioat1_tx_submit;
296 desc_sw->txd.phys = phys;
297 set_desc_id(desc_sw, -1);
302 static int ioat_initial_desc_count = 256;
303 module_param(ioat_initial_desc_count, int, 0644);
304 MODULE_PARM_DESC(ioat_initial_desc_count,
305 "ioat1: initial descriptors per channel (default: 256)");
307 * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
308 * @chan: the channel to be filled out
310 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
312 struct ioat_dma_chan *ioat = to_ioat_chan(c);
313 struct ioat_chan_common *chan = &ioat->base;
314 struct ioat_desc_sw *desc;
319 /* have we already been set up? */
320 if (!list_empty(&ioat->free_desc))
321 return ioat->desccount;
323 /* Setup register to interrupt and write completion status on error */
324 writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
326 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
328 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
329 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
332 /* Allocate descriptors */
333 for (i = 0; i < ioat_initial_desc_count; i++) {
334 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
336 dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
339 set_desc_id(desc, i);
340 list_add_tail(&desc->node, &tmp_list);
342 spin_lock_bh(&ioat->desc_lock);
344 list_splice(&tmp_list, &ioat->free_desc);
345 spin_unlock_bh(&ioat->desc_lock);
347 /* allocate a completion writeback area */
348 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
349 chan->completion = pci_pool_alloc(chan->device->completion_pool,
350 GFP_KERNEL, &chan->completion_dma);
351 memset(chan->completion, 0, sizeof(*chan->completion));
352 writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
353 chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
354 writel(((u64) chan->completion_dma) >> 32,
355 chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
357 tasklet_enable(&chan->cleanup_task);
358 ioat1_dma_start_null_desc(ioat); /* give chain to dma device */
359 dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
360 __func__, ioat->desccount);
361 return ioat->desccount;
365 * ioat1_dma_free_chan_resources - release all the descriptors
366 * @chan: the channel to be cleaned
368 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
370 struct ioat_dma_chan *ioat = to_ioat_chan(c);
371 struct ioat_chan_common *chan = &ioat->base;
372 struct ioatdma_device *ioatdma_device = chan->device;
373 struct ioat_desc_sw *desc, *_desc;
374 int in_use_descs = 0;
376 /* Before freeing channel resources first check
377 * if they have been previously allocated for this channel.
379 if (ioat->desccount == 0)
382 tasklet_disable(&chan->cleanup_task);
383 del_timer_sync(&chan->timer);
386 /* Delay 100ms after reset to allow internal DMA logic to quiesce
387 * before removing DMA descriptor resources.
389 writeb(IOAT_CHANCMD_RESET,
390 chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
393 spin_lock_bh(&ioat->desc_lock);
394 list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
395 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
396 __func__, desc_id(desc));
397 dump_desc_dbg(ioat, desc);
399 list_del(&desc->node);
400 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
404 list_for_each_entry_safe(desc, _desc,
405 &ioat->free_desc, node) {
406 list_del(&desc->node);
407 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
411 spin_unlock_bh(&ioat->desc_lock);
413 pci_pool_free(ioatdma_device->completion_pool,
415 chan->completion_dma);
417 /* one is ok since we left it on there on purpose */
418 if (in_use_descs > 1)
419 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
422 chan->last_completion = 0;
423 chan->completion_dma = 0;
429 * ioat1_dma_get_next_descriptor - return the next available descriptor
430 * @ioat: IOAT DMA channel handle
432 * Gets the next descriptor from the chain, and must be called with the
433 * channel's desc_lock held. Allocates more descriptors if the channel
436 static struct ioat_desc_sw *
437 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
439 struct ioat_desc_sw *new;
441 if (!list_empty(&ioat->free_desc)) {
442 new = to_ioat_desc(ioat->free_desc.next);
443 list_del(&new->node);
445 /* try to get another desc */
446 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
448 dev_err(to_dev(&ioat->base), "alloc failed\n");
452 dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
453 __func__, desc_id(new));
458 static struct dma_async_tx_descriptor *
459 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
460 dma_addr_t dma_src, size_t len, unsigned long flags)
462 struct ioat_dma_chan *ioat = to_ioat_chan(c);
463 struct ioat_desc_sw *desc;
466 dma_addr_t src = dma_src;
467 dma_addr_t dest = dma_dest;
468 size_t total_len = len;
469 struct ioat_dma_descriptor *hw = NULL;
472 spin_lock_bh(&ioat->desc_lock);
473 desc = ioat1_dma_get_next_descriptor(ioat);
479 copy = min_t(size_t, len, ioat->xfercap);
487 list_add_tail(&desc->node, &chain);
493 struct ioat_desc_sw *next;
495 async_tx_ack(&desc->txd);
496 next = ioat1_dma_get_next_descriptor(ioat);
497 hw->next = next ? next->txd.phys : 0;
498 dump_desc_dbg(ioat, desc);
505 struct ioat_chan_common *chan = &ioat->base;
507 dev_err(to_dev(chan),
508 "chan%d - get_next_desc failed\n", chan_num(chan));
509 list_splice(&chain, &ioat->free_desc);
510 spin_unlock_bh(&ioat->desc_lock);
513 spin_unlock_bh(&ioat->desc_lock);
515 desc->txd.flags = flags;
516 desc->len = total_len;
517 list_splice(&chain, &desc->tx_list);
518 hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
519 hw->ctl_f.compl_write = 1;
521 dump_desc_dbg(ioat, desc);
526 static void ioat1_cleanup_event(unsigned long data)
528 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
531 writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
534 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
535 size_t len, struct ioat_dma_descriptor *hw)
537 struct pci_dev *pdev = chan->device->pdev;
538 size_t offset = len - hw->size;
540 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
541 ioat_unmap(pdev, hw->dst_addr - offset, len,
542 PCI_DMA_FROMDEVICE, flags, 1);
544 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
545 ioat_unmap(pdev, hw->src_addr - offset, len,
546 PCI_DMA_TODEVICE, flags, 0);
549 dma_addr_t ioat_get_current_completion(struct ioat_chan_common *chan)
551 dma_addr_t phys_complete;
554 completion = *chan->completion;
555 phys_complete = ioat_chansts_to_addr(completion);
557 dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
558 (unsigned long long) phys_complete);
560 if (is_ioat_halted(completion)) {
561 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
562 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
565 /* TODO do something to salvage the situation */
568 return phys_complete;
571 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
572 dma_addr_t *phys_complete)
574 *phys_complete = ioat_get_current_completion(chan);
575 if (*phys_complete == chan->last_completion)
577 clear_bit(IOAT_COMPLETION_ACK, &chan->state);
578 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
583 static void __cleanup(struct ioat_dma_chan *ioat, dma_addr_t phys_complete)
585 struct ioat_chan_common *chan = &ioat->base;
586 struct list_head *_desc, *n;
587 struct dma_async_tx_descriptor *tx;
589 dev_dbg(to_dev(chan), "%s: phys_complete: %llx\n",
590 __func__, (unsigned long long) phys_complete);
591 list_for_each_safe(_desc, n, &ioat->used_desc) {
592 struct ioat_desc_sw *desc;
595 desc = list_entry(_desc, typeof(*desc), node);
598 * Incoming DMA requests may use multiple descriptors,
599 * due to exceeding xfercap, perhaps. If so, only the
600 * last one will have a cookie, and require unmapping.
602 dump_desc_dbg(ioat, desc);
604 dma_cookie_complete(tx);
605 ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
606 ioat->active -= desc->hw->tx_cnt;
608 tx->callback(tx->callback_param);
613 if (tx->phys != phys_complete) {
615 * a completed entry, but not the last, so clean
616 * up if the client is done with the descriptor
618 if (async_tx_test_ack(tx))
619 list_move_tail(&desc->node, &ioat->free_desc);
622 * last used desc. Do not remove, so we can
626 /* if nothing else is pending, cancel the
629 if (n == &ioat->used_desc) {
630 dev_dbg(to_dev(chan),
631 "%s cancel completion timeout\n",
633 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
636 /* TODO check status bits? */
641 chan->last_completion = phys_complete;
645 * ioat1_cleanup - cleanup up finished descriptors
646 * @chan: ioat channel to be cleaned up
648 * To prevent lock contention we defer cleanup when the locks are
649 * contended with a terminal timeout that forces cleanup and catches
650 * completion notification errors.
652 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
654 struct ioat_chan_common *chan = &ioat->base;
655 dma_addr_t phys_complete;
657 prefetch(chan->completion);
659 if (!spin_trylock_bh(&chan->cleanup_lock))
662 if (!ioat_cleanup_preamble(chan, &phys_complete)) {
663 spin_unlock_bh(&chan->cleanup_lock);
667 if (!spin_trylock_bh(&ioat->desc_lock)) {
668 spin_unlock_bh(&chan->cleanup_lock);
672 __cleanup(ioat, phys_complete);
674 spin_unlock_bh(&ioat->desc_lock);
675 spin_unlock_bh(&chan->cleanup_lock);
678 static void ioat1_timer_event(unsigned long data)
680 struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
681 struct ioat_chan_common *chan = &ioat->base;
683 dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
685 spin_lock_bh(&chan->cleanup_lock);
686 if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
687 struct ioat_desc_sw *desc;
689 spin_lock_bh(&ioat->desc_lock);
691 /* restart active descriptors */
692 desc = to_ioat_desc(ioat->used_desc.prev);
693 ioat_set_chainaddr(ioat, desc->txd.phys);
697 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
698 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
699 spin_unlock_bh(&ioat->desc_lock);
700 } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
701 dma_addr_t phys_complete;
703 spin_lock_bh(&ioat->desc_lock);
704 /* if we haven't made progress and we have already
705 * acknowledged a pending completion once, then be more
706 * forceful with a restart
708 if (ioat_cleanup_preamble(chan, &phys_complete))
709 __cleanup(ioat, phys_complete);
710 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
711 ioat1_reset_channel(ioat);
713 u64 status = ioat_chansts(chan);
715 /* manually update the last completion address */
716 if (ioat_chansts_to_addr(status) != 0)
717 *chan->completion = status;
719 set_bit(IOAT_COMPLETION_ACK, &chan->state);
720 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
722 spin_unlock_bh(&ioat->desc_lock);
724 spin_unlock_bh(&chan->cleanup_lock);
728 ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
729 struct dma_tx_state *txstate)
731 struct ioat_chan_common *chan = to_chan_common(c);
732 struct ioatdma_device *device = chan->device;
735 ret = dma_cookie_status(c, cookie, txstate);
736 if (ret == DMA_SUCCESS)
739 device->cleanup_fn((unsigned long) c);
741 return dma_cookie_status(c, cookie, txstate);
744 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
746 struct ioat_chan_common *chan = &ioat->base;
747 struct ioat_desc_sw *desc;
748 struct ioat_dma_descriptor *hw;
750 spin_lock_bh(&ioat->desc_lock);
752 desc = ioat1_dma_get_next_descriptor(ioat);
755 dev_err(to_dev(chan),
756 "Unable to start null desc - get next desc failed\n");
757 spin_unlock_bh(&ioat->desc_lock);
764 hw->ctl_f.int_en = 1;
765 hw->ctl_f.compl_write = 1;
766 /* set size to non-zero value (channel returns error when size is 0) */
767 hw->size = NULL_DESC_BUFFER_SIZE;
770 async_tx_ack(&desc->txd);
772 list_add_tail(&desc->node, &ioat->used_desc);
773 dump_desc_dbg(ioat, desc);
775 ioat_set_chainaddr(ioat, desc->txd.phys);
777 spin_unlock_bh(&ioat->desc_lock);
781 * Perform a IOAT transaction to verify the HW works.
783 #define IOAT_TEST_SIZE 2000
785 static void ioat_dma_test_callback(void *dma_async_param)
787 struct completion *cmp = dma_async_param;
793 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
794 * @device: device to be tested
796 int ioat_dma_self_test(struct ioatdma_device *device)
801 struct dma_device *dma = &device->common;
802 struct device *dev = &device->pdev->dev;
803 struct dma_chan *dma_chan;
804 struct dma_async_tx_descriptor *tx;
805 dma_addr_t dma_dest, dma_src;
808 struct completion cmp;
812 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
815 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
821 /* Fill in src buffer */
822 for (i = 0; i < IOAT_TEST_SIZE; i++)
825 /* Start copy, using first DMA channel */
826 dma_chan = container_of(dma->channels.next, struct dma_chan,
828 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
829 dev_err(dev, "selftest cannot allocate chan resource\n");
834 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
835 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
836 flags = DMA_COMPL_SKIP_SRC_UNMAP | DMA_COMPL_SKIP_DEST_UNMAP |
838 tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
839 IOAT_TEST_SIZE, flags);
841 dev_err(dev, "Self-test prep failed, disabling\n");
847 init_completion(&cmp);
848 tx->callback = ioat_dma_test_callback;
849 tx->callback_param = &cmp;
850 cookie = tx->tx_submit(tx);
852 dev_err(dev, "Self-test setup failed, disabling\n");
856 dma->device_issue_pending(dma_chan);
858 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
861 dma->device_tx_status(dma_chan, cookie, NULL)
863 dev_err(dev, "Self-test copy timed out, disabling\n");
867 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
868 dev_err(dev, "Self-test copy failed compare, disabling\n");
874 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
875 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
877 dma->device_free_chan_resources(dma_chan);
884 static char ioat_interrupt_style[32] = "msix";
885 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
886 sizeof(ioat_interrupt_style), 0644);
887 MODULE_PARM_DESC(ioat_interrupt_style,
888 "set ioat interrupt style: msix (default), "
889 "msix-single-vector, msi, intx)");
892 * ioat_dma_setup_interrupts - setup interrupt handler
893 * @device: ioat device
895 int ioat_dma_setup_interrupts(struct ioatdma_device *device)
897 struct ioat_chan_common *chan;
898 struct pci_dev *pdev = device->pdev;
899 struct device *dev = &pdev->dev;
900 struct msix_entry *msix;
905 if (!strcmp(ioat_interrupt_style, "msix"))
907 if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
908 goto msix_single_vector;
909 if (!strcmp(ioat_interrupt_style, "msi"))
911 if (!strcmp(ioat_interrupt_style, "intx"))
913 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
917 /* The number of MSI-X vectors should equal the number of channels */
918 msixcnt = device->common.chancnt;
919 for (i = 0; i < msixcnt; i++)
920 device->msix_entries[i].entry = i;
922 err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
926 goto msix_single_vector;
928 for (i = 0; i < msixcnt; i++) {
929 msix = &device->msix_entries[i];
930 chan = ioat_chan_by_index(device, i);
931 err = devm_request_irq(dev, msix->vector,
932 ioat_dma_do_interrupt_msix, 0,
935 for (j = 0; j < i; j++) {
936 msix = &device->msix_entries[j];
937 chan = ioat_chan_by_index(device, j);
938 devm_free_irq(dev, msix->vector, chan);
940 goto msix_single_vector;
943 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
944 device->irq_mode = IOAT_MSIX;
948 msix = &device->msix_entries[0];
950 err = pci_enable_msix(pdev, device->msix_entries, 1);
954 err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
955 "ioat-msix", device);
957 pci_disable_msix(pdev);
960 device->irq_mode = IOAT_MSIX_SINGLE;
964 err = pci_enable_msi(pdev);
968 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
971 pci_disable_msi(pdev);
974 device->irq_mode = IOAT_MSIX;
978 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
979 IRQF_SHARED, "ioat-intx", device);
983 device->irq_mode = IOAT_INTX;
985 if (device->intr_quirk)
986 device->intr_quirk(device);
987 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
988 writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
992 /* Disable all interrupt generation */
993 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
994 device->irq_mode = IOAT_NOIRQ;
995 dev_err(dev, "no usable interrupts\n");
998 EXPORT_SYMBOL(ioat_dma_setup_interrupts);
1000 static void ioat_disable_interrupts(struct ioatdma_device *device)
1002 /* Disable all interrupt generation */
1003 writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
1006 int ioat_probe(struct ioatdma_device *device)
1009 struct dma_device *dma = &device->common;
1010 struct pci_dev *pdev = device->pdev;
1011 struct device *dev = &pdev->dev;
1013 /* DMA coherent memory pool for DMA descriptor allocations */
1014 device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1015 sizeof(struct ioat_dma_descriptor),
1017 if (!device->dma_pool) {
1022 device->completion_pool = pci_pool_create("completion_pool", pdev,
1023 sizeof(u64), SMP_CACHE_BYTES,
1026 if (!device->completion_pool) {
1028 goto err_completion_pool;
1031 device->enumerate_channels(device);
1033 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1034 dma->dev = &pdev->dev;
1036 if (!dma->chancnt) {
1037 dev_err(dev, "channel enumeration error\n");
1038 goto err_setup_interrupts;
1041 err = ioat_dma_setup_interrupts(device);
1043 goto err_setup_interrupts;
1045 err = device->self_test(device);
1052 ioat_disable_interrupts(device);
1053 err_setup_interrupts:
1054 pci_pool_destroy(device->completion_pool);
1055 err_completion_pool:
1056 pci_pool_destroy(device->dma_pool);
1061 int ioat_register(struct ioatdma_device *device)
1063 int err = dma_async_device_register(&device->common);
1066 ioat_disable_interrupts(device);
1067 pci_pool_destroy(device->completion_pool);
1068 pci_pool_destroy(device->dma_pool);
1074 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1075 static void ioat1_intr_quirk(struct ioatdma_device *device)
1077 struct pci_dev *pdev = device->pdev;
1080 pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1081 if (pdev->msi_enabled)
1082 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1084 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1085 pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1088 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1090 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1092 return sprintf(page, "%d\n", ioat->desccount);
1094 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1096 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1098 struct ioat_dma_chan *ioat = to_ioat_chan(c);
1100 return sprintf(page, "%d\n", ioat->active);
1102 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1104 static ssize_t cap_show(struct dma_chan *c, char *page)
1106 struct dma_device *dma = c->device;
1108 return sprintf(page, "copy%s%s%s%s%s\n",
1109 dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1110 dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1111 dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1112 dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1113 dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1116 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1118 static ssize_t version_show(struct dma_chan *c, char *page)
1120 struct dma_device *dma = c->device;
1121 struct ioatdma_device *device = to_ioatdma_device(dma);
1123 return sprintf(page, "%d.%d\n",
1124 device->version >> 4, device->version & 0xf);
1126 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1128 static struct attribute *ioat1_attrs[] = {
1129 &ring_size_attr.attr,
1130 &ring_active_attr.attr,
1131 &ioat_cap_attr.attr,
1132 &ioat_version_attr.attr,
1137 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1139 struct ioat_sysfs_entry *entry;
1140 struct ioat_chan_common *chan;
1142 entry = container_of(attr, struct ioat_sysfs_entry, attr);
1143 chan = container_of(kobj, struct ioat_chan_common, kobj);
1147 return entry->show(&chan->common, page);
1150 const struct sysfs_ops ioat_sysfs_ops = {
1151 .show = ioat_attr_show,
1154 static struct kobj_type ioat1_ktype = {
1155 .sysfs_ops = &ioat_sysfs_ops,
1156 .default_attrs = ioat1_attrs,
1159 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1161 struct dma_device *dma = &device->common;
1164 list_for_each_entry(c, &dma->channels, device_node) {
1165 struct ioat_chan_common *chan = to_chan_common(c);
1166 struct kobject *parent = &c->dev->device.kobj;
1169 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1171 dev_warn(to_dev(chan),
1172 "sysfs init error (%d), continuing...\n", err);
1173 kobject_put(&chan->kobj);
1174 set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1179 void ioat_kobject_del(struct ioatdma_device *device)
1181 struct dma_device *dma = &device->common;
1184 list_for_each_entry(c, &dma->channels, device_node) {
1185 struct ioat_chan_common *chan = to_chan_common(c);
1187 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1188 kobject_del(&chan->kobj);
1189 kobject_put(&chan->kobj);
1194 int ioat1_dma_probe(struct ioatdma_device *device, int dca)
1196 struct pci_dev *pdev = device->pdev;
1197 struct dma_device *dma;
1200 device->intr_quirk = ioat1_intr_quirk;
1201 device->enumerate_channels = ioat1_enumerate_channels;
1202 device->self_test = ioat_dma_self_test;
1203 device->timer_fn = ioat1_timer_event;
1204 device->cleanup_fn = ioat1_cleanup_event;
1205 dma = &device->common;
1206 dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1207 dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1208 dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1209 dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1210 dma->device_tx_status = ioat_dma_tx_status;
1212 err = ioat_probe(device);
1215 ioat_set_tcp_copy_break(4096);
1216 err = ioat_register(device);
1219 ioat_kobject_add(device, &ioat1_ktype);
1222 device->dca = ioat_dca_init(pdev, device->reg_base);
1227 void ioat_dma_remove(struct ioatdma_device *device)
1229 struct dma_device *dma = &device->common;
1231 ioat_disable_interrupts(device);
1233 ioat_kobject_del(device);
1235 dma_async_device_unregister(dma);
1237 pci_pool_destroy(device->dma_pool);
1238 pci_pool_destroy(device->completion_pool);
1240 INIT_LIST_HEAD(&dma->channels);