drivers/dma/imx-sdma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-sdma.c
   4 //
   5 // This file contains a driver for the Freescale Smart DMA engine
   6 //
   7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8 //
   9 // Based on code from Freescale:
  10 //
  11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  12
  13 #include <linux/init.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/bitops.h>
  18 #include <linux/mm.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched.h>
  23 #include <linux/semaphore.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firmware.h>
  28 #include <linux/slab.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_dma.h>
  35 #include <linux/workqueue.h>
  36
  37 #include <asm/irq.h>
  38 #include <linux/platform_data/dma-imx.h>
  39 #include <linux/regmap.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  42
  43 #include "dmaengine.h"
  44 #include "virt-dma.h"
  45
  46 /* SDMA registers */
  47 #define SDMA_H_C0PTR            0x000
  48 #define SDMA_H_INTR             0x004
  49 #define SDMA_H_STATSTOP         0x008
  50 #define SDMA_H_START            0x00c
  51 #define SDMA_H_EVTOVR           0x010
  52 #define SDMA_H_DSPOVR           0x014
  53 #define SDMA_H_HOSTOVR          0x018
  54 #define SDMA_H_EVTPEND          0x01c
  55 #define SDMA_H_DSPENBL          0x020
  56 #define SDMA_H_RESET            0x024
  57 #define SDMA_H_EVTERR           0x028
  58 #define SDMA_H_INTRMSK          0x02c
  59 #define SDMA_H_PSW              0x030
  60 #define SDMA_H_EVTERRDBG        0x034
  61 #define SDMA_H_CONFIG           0x038
  62 #define SDMA_ONCE_ENB           0x040
  63 #define SDMA_ONCE_DATA          0x044
  64 #define SDMA_ONCE_INSTR         0x048
  65 #define SDMA_ONCE_STAT          0x04c
  66 #define SDMA_ONCE_CMD           0x050
  67 #define SDMA_EVT_MIRROR         0x054
  68 #define SDMA_ILLINSTADDR        0x058
  69 #define SDMA_CHN0ADDR           0x05c
  70 #define SDMA_ONCE_RTB           0x060
  71 #define SDMA_XTRIG_CONF1        0x070
  72 #define SDMA_XTRIG_CONF2        0x074
  73 #define SDMA_CHNENBL0_IMX35     0x200
  74 #define SDMA_CHNENBL0_IMX31     0x080
  75 #define SDMA_CHNPRI_0           0x100
  76
  77 /*
  78  * Buffer descriptor status values.
  79  */
  80 #define BD_DONE  0x01
  81 #define BD_WRAP  0x02
  82 #define BD_CONT  0x04
  83 #define BD_INTR  0x08
  84 #define BD_RROR  0x10
  85 #define BD_LAST  0x20
  86 #define BD_EXTD  0x80
  87
  88 /*
  89  * Data Node descriptor status values.
  90  */
  91 #define DND_END_OF_FRAME  0x80
  92 #define DND_END_OF_XFER   0x40
  93 #define DND_DONE          0x20
  94 #define DND_UNUSED        0x01
  95
  96 /*
  97  * IPCV2 descriptor status values.
  98  */
  99 #define BD_IPCV2_END_OF_FRAME  0x40
 100
 101 #define IPCV2_MAX_NODES        50
 102 /*
 103  * Error bit set in the CCB status field by the SDMA,
 104  * in setbd routine, in case of a transfer error
 105  */
 106 #define DATA_ERROR  0x10000000
 107
 108 /*
 109  * Buffer descriptor commands.
 110  */
 111 #define C0_ADDR             0x01
 112 #define C0_LOAD             0x02
 113 #define C0_DUMP             0x03
 114 #define C0_SETCTX           0x07
 115 #define C0_GETCTX           0x03
 116 #define C0_SETDM            0x01
 117 #define C0_SETPM            0x04
 118 #define C0_GETDM            0x02
 119 #define C0_GETPM            0x08
 120 /*
 121  * Change endianness indicator in the BD command field
 122  */
 123 #define CHANGE_ENDIANNESS   0x80
 124
 125 /*
 126  *  p_2_p watermark_level description
 127  *      Bits            Name                    Description
 128  *      0-7             Lower WML               Lower watermark level
 129  *      8               PS                      1: Pad Swallowing
 130  *                                              0: No Pad Swallowing
 131  *      9               PA                      1: Pad Adding
 132  *                                              0: No Pad Adding
 133  *      10              SPDIF                   If this bit is set both source
 134  *                                              and destination are on SPBA
 135  *      11              Source Bit(SP)          1: Source on SPBA
 136  *                                              0: Source on AIPS
 137  *      12              Destination Bit(DP)     1: Destination on SPBA
 138  *                                              0: Destination on AIPS
 139  *      13-15           ---------               MUST BE 0
 140  *      16-23           Higher WML              HWML
 141  *      24-27           N                       Total number of samples after
 142  *                                              which Pad adding/Swallowing
 143  *                                              must be done. It must be odd.
 144  *      28              Lower WML Event(LWE)    SDMA events reg to check for
 145  *                                              LWML event mask
 146  *                                              0: LWE in EVENTS register
 147  *                                              1: LWE in EVENTS2 register
 148  *      29              Higher WML Event(HWE)   SDMA events reg to check for
 149  *                                              HWML event mask
 150  *                                              0: HWE in EVENTS register
 151  *                                              1: HWE in EVENTS2 register
 152  *      30              ---------               MUST BE 0
 153  *      31              CONT                    1: Amount of samples to be
 154  *                                              transferred is unknown and
 155  *                                              script will keep on
 156  *                                              transferring samples as long as
 157  *                                              both events are detected and
 158  *                                              script must be manually stopped
 159  *                                              by the application
 160  *                                              0: The amount of samples to be
 161  *                                              transferred is equal to the
 162  *                                              count field of mode word
 163  */
 164 #define SDMA_WATERMARK_LEVEL_LWML       0xFF
 165 #define SDMA_WATERMARK_LEVEL_PS         BIT(8)
 166 #define SDMA_WATERMARK_LEVEL_PA         BIT(9)
 167 #define SDMA_WATERMARK_LEVEL_SPDIF      BIT(10)
 168 #define SDMA_WATERMARK_LEVEL_SP         BIT(11)
 169 #define SDMA_WATERMARK_LEVEL_DP         BIT(12)
 170 #define SDMA_WATERMARK_LEVEL_HWML       (0xFF << 16)
 171 #define SDMA_WATERMARK_LEVEL_LWE        BIT(28)
 172 #define SDMA_WATERMARK_LEVEL_HWE        BIT(29)
 173 #define SDMA_WATERMARK_LEVEL_CONT       BIT(31)
 174
 175 #define SDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 176                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 177                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
 178
 179 #define SDMA_DMA_DIRECTIONS     (BIT(DMA_DEV_TO_MEM) | \
 180                                  BIT(DMA_MEM_TO_DEV) | \
 181                                  BIT(DMA_DEV_TO_DEV))
 182
 183 /**
 184  * struct sdma_script_start_addrs - SDMA script start pointers
 185  *
 186  * start addresses of the different functions in the physical
 187  * address space of the SDMA engine.
 188  */
 189 struct sdma_script_start_addrs {
 190         s32 ap_2_ap_addr;
 191         s32 ap_2_bp_addr;
 192         s32 ap_2_ap_fixed_addr;
 193         s32 bp_2_ap_addr;
 194         s32 loopback_on_dsp_side_addr;
 195         s32 mcu_interrupt_only_addr;
 196         s32 firi_2_per_addr;
 197         s32 firi_2_mcu_addr;
 198         s32 per_2_firi_addr;
 199         s32 mcu_2_firi_addr;
 200         s32 uart_2_per_addr;
 201         s32 uart_2_mcu_addr;
 202         s32 per_2_app_addr;
 203         s32 mcu_2_app_addr;
 204         s32 per_2_per_addr;
 205         s32 uartsh_2_per_addr;
 206         s32 uartsh_2_mcu_addr;
 207         s32 per_2_shp_addr;
 208         s32 mcu_2_shp_addr;
 209         s32 ata_2_mcu_addr;
 210         s32 mcu_2_ata_addr;
 211         s32 app_2_per_addr;
 212         s32 app_2_mcu_addr;
 213         s32 shp_2_per_addr;
 214         s32 shp_2_mcu_addr;
 215         s32 mshc_2_mcu_addr;
 216         s32 mcu_2_mshc_addr;
 217         s32 spdif_2_mcu_addr;
 218         s32 mcu_2_spdif_addr;
 219         s32 asrc_2_mcu_addr;
 220         s32 ext_mem_2_ipu_addr;
 221         s32 descrambler_addr;
 222         s32 dptc_dvfs_addr;
 223         s32 utra_addr;
 224         s32 ram_code_start_addr;
 225         /* End of v1 array */
 226         s32 mcu_2_ssish_addr;
 227         s32 ssish_2_mcu_addr;
 228         s32 hdmi_dma_addr;
 229         /* End of v2 array */
 230         s32 zcanfd_2_mcu_addr;
 231         s32 zqspi_2_mcu_addr;
 232         s32 mcu_2_ecspi_addr;
 233         s32 mcu_2_sai_addr;
 234         s32 sai_2_mcu_addr;
 235         s32 uart_2_mcu_rom_addr;
 236         s32 uartsh_2_mcu_rom_addr;
 237         /* End of v3 array */
 238         s32 mcu_2_zqspi_addr;
 239         /* End of v4 array */
 240 };
 241
 242 /*
 243  * Mode/Count of data node descriptors - IPCv2
 244  */
 245 struct sdma_mode_count {
 246 #define SDMA_BD_MAX_CNT 0xffff
 247         u32 count   : 16; /* size of the buffer pointed by this BD */
 248         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 249         u32 command :  8; /* command mostly used for channel 0 */
 250 };
 251
 252 /*
 253  * Buffer descriptor
 254  */
 255 struct sdma_buffer_descriptor {
 256         struct sdma_mode_count  mode;
 257         u32 buffer_addr;        /* address of the buffer described */
 258         u32 ext_buffer_addr;    /* extended buffer address */
 259 } __attribute__ ((packed));
 260
 261 /**
 262  * struct sdma_channel_control - Channel control Block
 263  *
 264  * @current_bd_ptr:     current buffer descriptor processed
 265  * @base_bd_ptr:        first element of buffer descriptor array
 266  * @unused:             padding. The SDMA engine expects an array of 128 byte
 267  *                      control blocks
 268  */
 269 struct sdma_channel_control {
 270         u32 current_bd_ptr;
 271         u32 base_bd_ptr;
 272         u32 unused[2];
 273 } __attribute__ ((packed));
 274
 275 /**
 276  * struct sdma_state_registers - SDMA context for a channel
 277  *
 278  * @pc:         program counter
 279  * @unused1:    unused
 280  * @t:          test bit: status of arithmetic & test instruction
 281  * @rpc:        return program counter
 282  * @unused0:    unused
 283  * @sf:         source fault while loading data
 284  * @spc:        loop start program counter
 285  * @unused2:    unused
 286  * @df:         destination fault while storing data
 287  * @epc:        loop end program counter
 288  * @lm:         loop mode
 289  */
 290 struct sdma_state_registers {
 291         u32 pc     :14;
 292         u32 unused1: 1;
 293         u32 t      : 1;
 294         u32 rpc    :14;
 295         u32 unused0: 1;
 296         u32 sf     : 1;
 297         u32 spc    :14;
 298         u32 unused2: 1;
 299         u32 df     : 1;
 300         u32 epc    :14;
 301         u32 lm     : 2;
 302 } __attribute__ ((packed));
 303
 304 /**
 305  * struct sdma_context_data - sdma context specific to a channel
 306  *
 307  * @channel_state:      channel state bits
 308  * @gReg:               general registers
 309  * @mda:                burst dma destination address register
 310  * @msa:                burst dma source address register
 311  * @ms:                 burst dma status register
 312  * @md:                 burst dma data register
 313  * @pda:                peripheral dma destination address register
 314  * @psa:                peripheral dma source address register
 315  * @ps:                 peripheral dma status register
 316  * @pd:                 peripheral dma data register
 317  * @ca:                 CRC polynomial register
 318  * @cs:                 CRC accumulator register
 319  * @dda:                dedicated core destination address register
 320  * @dsa:                dedicated core source address register
 321  * @ds:                 dedicated core status register
 322  * @dd:                 dedicated core data register
 323  * @scratch0:           1st word of dedicated ram for context switch
 324  * @scratch1:           2nd word of dedicated ram for context switch
 325  * @scratch2:           3rd word of dedicated ram for context switch
 326  * @scratch3:           4th word of dedicated ram for context switch
 327  * @scratch4:           5th word of dedicated ram for context switch
 328  * @scratch5:           6th word of dedicated ram for context switch
 329  * @scratch6:           7th word of dedicated ram for context switch
 330  * @scratch7:           8th word of dedicated ram for context switch
 331  */
 332 struct sdma_context_data {
 333         struct sdma_state_registers  channel_state;
 334         u32  gReg[8];
 335         u32  mda;
 336         u32  msa;
 337         u32  ms;
 338         u32  md;
 339         u32  pda;
 340         u32  psa;
 341         u32  ps;
 342         u32  pd;
 343         u32  ca;
 344         u32  cs;
 345         u32  dda;
 346         u32  dsa;
 347         u32  ds;
 348         u32  dd;
 349         u32  scratch0;
 350         u32  scratch1;
 351         u32  scratch2;
 352         u32  scratch3;
 353         u32  scratch4;
 354         u32  scratch5;
 355         u32  scratch6;
 356         u32  scratch7;
 357 } __attribute__ ((packed));
 358
 359
 360 struct sdma_engine;
 361
 362 /**
 363  * struct sdma_desc - descriptor structor for one transfer
 364  * @vd:                 descriptor for virt dma
 365  * @num_bd:             number of descriptors currently handling
 366  * @bd_phys:            physical address of bd
 367  * @buf_tail:           ID of the buffer that was processed
 368  * @buf_ptail:          ID of the previous buffer that was processed
 369  * @period_len:         period length, used in cyclic.
 370  * @chn_real_count:     the real count updated from bd->mode.count
 371  * @chn_count:          the transfer count set
 372  * @sdmac:              sdma_channel pointer
 373  * @bd:                 pointer of allocate bd
 374  */
 375 struct sdma_desc {
 376         struct virt_dma_desc    vd;
 377         unsigned int            num_bd;
 378         dma_addr_t              bd_phys;
 379         unsigned int            buf_tail;
 380         unsigned int            buf_ptail;
 381         unsigned int            period_len;
 382         unsigned int            chn_real_count;
 383         unsigned int            chn_count;
 384         struct sdma_channel     *sdmac;
 385         struct sdma_buffer_descriptor *bd;
 386 };
 387
 388 /**
 389  * struct sdma_channel - housekeeping for a SDMA channel
 390  *
 391  * @vc:                 virt_dma base structure
 392  * @desc:               sdma description including vd and other special member
 393  * @sdma:               pointer to the SDMA engine for this channel
 394  * @channel:            the channel number, matches dmaengine chan_id + 1
 395  * @direction:          transfer type. Needed for setting SDMA script
 396  * @slave_config:       Slave configuration
 397  * @peripheral_type:    Peripheral type. Needed for setting SDMA script
 398  * @event_id0:          aka dma request line
 399  * @event_id1:          for channels that use 2 events
 400  * @word_size:          peripheral access size
 401  * @pc_from_device:     script address for those device_2_memory
 402  * @pc_to_device:       script address for those memory_2_device
 403  * @device_to_device:   script address for those device_2_device
 404  * @pc_to_pc:           script address for those memory_2_memory
 405  * @flags:              loop mode or not
 406  * @per_address:        peripheral source or destination address in common case
 407  *                      destination address in p_2_p case
 408  * @per_address2:       peripheral source address in p_2_p case
 409  * @event_mask:         event mask used in p_2_p script
 410  * @watermark_level:    value for gReg[7], some script will extend it from
 411  *                      basic watermark such as p_2_p
 412  * @shp_addr:           value for gReg[6]
 413  * @per_addr:           value for gReg[2]
 414  * @status:             status of dma channel
 415  * @context_loaded:     ensure context is only loaded once
 416  * @data:               specific sdma interface structure
 417  * @bd_pool:            dma_pool for bd
 418  * @terminate_worker:   used to call back into terminate work function
 419  */
 420 struct sdma_channel {
 421         struct virt_dma_chan            vc;
 422         struct sdma_desc                *desc;
 423         struct sdma_engine              *sdma;
 424         unsigned int                    channel;
 425         enum dma_transfer_direction             direction;
 426         struct dma_slave_config         slave_config;
 427         enum sdma_peripheral_type       peripheral_type;
 428         unsigned int                    event_id0;
 429         unsigned int                    event_id1;
 430         enum dma_slave_buswidth         word_size;
 431         unsigned int                    pc_from_device, pc_to_device;
 432         unsigned int                    device_to_device;
 433         unsigned int                    pc_to_pc;
 434         unsigned long                   flags;
 435         dma_addr_t                      per_address, per_address2;
 436         unsigned long                   event_mask[2];
 437         unsigned long                   watermark_level;
 438         u32                             shp_addr, per_addr;
 439         enum dma_status                 status;
 440         struct imx_dma_data             data;
 441         struct work_struct              terminate_worker;
 442         struct list_head                terminated;
 443         bool                            is_ram_script;
 444 };
 445
 446 #define IMX_DMA_SG_LOOP         BIT(0)
 447
 448 #define MAX_DMA_CHANNELS 32
 449 #define MXC_SDMA_DEFAULT_PRIORITY 1
 450 #define MXC_SDMA_MIN_PRIORITY 1
 451 #define MXC_SDMA_MAX_PRIORITY 7
 452
 453 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 454
 455 /**
 456  * struct sdma_firmware_header - Layout of the firmware image
 457  *
 458  * @magic:              "SDMA"
 459  * @version_major:      increased whenever layout of struct
 460  *                      sdma_script_start_addrs changes.
 461  * @version_minor:      firmware minor version (for binary compatible changes)
 462  * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
 463  * @num_script_addrs:   Number of script addresses in this image
 464  * @ram_code_start:     offset of SDMA ram image in this firmware image
 465  * @ram_code_size:      size of SDMA ram image
 466  * @script_addrs:       Stores the start address of the SDMA scripts
 467  *                      (in SDMA memory space)
 468  */
 469 struct sdma_firmware_header {
 470         u32     magic;
 471         u32     version_major;
 472         u32     version_minor;
 473         u32     script_addrs_start;
 474         u32     num_script_addrs;
 475         u32     ram_code_start;
 476         u32     ram_code_size;
 477 };
 478
 479 struct sdma_driver_data {
 480         int chnenbl0;
 481         int num_events;
 482         struct sdma_script_start_addrs  *script_addrs;
 483         bool check_ratio;
 484         /*
 485          * ecspi ERR009165 fixed should be done in sdma script
 486          * and it has been fixed in soc from i.mx6ul.
 487          * please get more information from the below link:
 488          * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
 489          */
 490         bool ecspi_fixed;
 491 };
 492
 493 struct sdma_engine {
 494         struct device                   *dev;
 495         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 496         struct sdma_channel_control     *channel_control;
 497         void __iomem                    *regs;
 498         struct sdma_context_data        *context;
 499         dma_addr_t                      context_phys;
 500         struct dma_device               dma_device;
 501         struct clk                      *clk_ipg;
 502         struct clk                      *clk_ahb;
 503         spinlock_t                      channel_0_lock;
 504         u32                             script_number;
 505         struct sdma_script_start_addrs  *script_addrs;
 506         const struct sdma_driver_data   *drvdata;
 507         u32                             spba_start_addr;
 508         u32                             spba_end_addr;
 509         unsigned int                    irq;
 510         dma_addr_t                      bd0_phys;
 511         struct sdma_buffer_descriptor   *bd0;
 512         /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
 513         bool                            clk_ratio;
 514         bool                            fw_loaded;
 515 };
 516
 517 static int sdma_config_write(struct dma_chan *chan,
 518                        struct dma_slave_config *dmaengine_cfg,
 519                        enum dma_transfer_direction direction);
 520
 521 static struct sdma_driver_data sdma_imx31 = {
 522         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 523         .num_events = 32,
 524 };
 525
 526 static struct sdma_script_start_addrs sdma_script_imx25 = {
 527         .ap_2_ap_addr = 729,
 528         .uart_2_mcu_addr = 904,
 529         .per_2_app_addr = 1255,
 530         .mcu_2_app_addr = 834,
 531         .uartsh_2_mcu_addr = 1120,
 532         .per_2_shp_addr = 1329,
 533         .mcu_2_shp_addr = 1048,
 534         .ata_2_mcu_addr = 1560,
 535         .mcu_2_ata_addr = 1479,
 536         .app_2_per_addr = 1189,
 537         .app_2_mcu_addr = 770,
 538         .shp_2_per_addr = 1407,
 539         .shp_2_mcu_addr = 979,
 540 };
 541
 542 static struct sdma_driver_data sdma_imx25 = {
 543         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 544         .num_events = 48,
 545         .script_addrs = &sdma_script_imx25,
 546 };
 547
 548 static struct sdma_driver_data sdma_imx35 = {
 549         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 550         .num_events = 48,
 551 };
 552
 553 static struct sdma_script_start_addrs sdma_script_imx51 = {
 554         .ap_2_ap_addr = 642,
 555         .uart_2_mcu_addr = 817,
 556         .mcu_2_app_addr = 747,
 557         .mcu_2_shp_addr = 961,
 558         .ata_2_mcu_addr = 1473,
 559         .mcu_2_ata_addr = 1392,
 560         .app_2_per_addr = 1033,
 561         .app_2_mcu_addr = 683,
 562         .shp_2_per_addr = 1251,
 563         .shp_2_mcu_addr = 892,
 564 };
 565
 566 static struct sdma_driver_data sdma_imx51 = {
 567         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 568         .num_events = 48,
 569         .script_addrs = &sdma_script_imx51,
 570 };
 571
 572 static struct sdma_script_start_addrs sdma_script_imx53 = {
 573         .ap_2_ap_addr = 642,
 574         .app_2_mcu_addr = 683,
 575         .mcu_2_app_addr = 747,
 576         .uart_2_mcu_addr = 817,
 577         .shp_2_mcu_addr = 891,
 578         .mcu_2_shp_addr = 960,
 579         .uartsh_2_mcu_addr = 1032,
 580         .spdif_2_mcu_addr = 1100,
 581         .mcu_2_spdif_addr = 1134,
 582         .firi_2_mcu_addr = 1193,
 583         .mcu_2_firi_addr = 1290,
 584 };
 585
 586 static struct sdma_driver_data sdma_imx53 = {
 587         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 588         .num_events = 48,
 589         .script_addrs = &sdma_script_imx53,
 590 };
 591
 592 static struct sdma_script_start_addrs sdma_script_imx6q = {
 593         .ap_2_ap_addr = 642,
 594         .uart_2_mcu_addr = 817,
 595         .mcu_2_app_addr = 747,
 596         .per_2_per_addr = 6331,
 597         .uartsh_2_mcu_addr = 1032,
 598         .mcu_2_shp_addr = 960,
 599         .app_2_mcu_addr = 683,
 600         .shp_2_mcu_addr = 891,
 601         .spdif_2_mcu_addr = 1100,
 602         .mcu_2_spdif_addr = 1134,
 603 };
 604
 605 static struct sdma_driver_data sdma_imx6q = {
 606         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 607         .num_events = 48,
 608         .script_addrs = &sdma_script_imx6q,
 609 };
 610
 611 static struct sdma_driver_data sdma_imx6ul = {
 612         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 613         .num_events = 48,
 614         .script_addrs = &sdma_script_imx6q,
 615         .ecspi_fixed = true,
 616 };
 617
 618 static struct sdma_script_start_addrs sdma_script_imx7d = {
 619         .ap_2_ap_addr = 644,
 620         .uart_2_mcu_addr = 819,
 621         .mcu_2_app_addr = 749,
 622         .uartsh_2_mcu_addr = 1034,
 623         .mcu_2_shp_addr = 962,
 624         .app_2_mcu_addr = 685,
 625         .shp_2_mcu_addr = 893,
 626         .spdif_2_mcu_addr = 1102,
 627         .mcu_2_spdif_addr = 1136,
 628 };
 629
 630 static struct sdma_driver_data sdma_imx7d = {
 631         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 632         .num_events = 48,
 633         .script_addrs = &sdma_script_imx7d,
 634 };
 635
 636 static struct sdma_driver_data sdma_imx8mq = {
 637         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 638         .num_events = 48,
 639         .script_addrs = &sdma_script_imx7d,
 640         .check_ratio = 1,
 641 };
 642
 643 static const struct of_device_id sdma_dt_ids[] = {
 644         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 645         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 646         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 647         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 648         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 649         { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
 650         { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
 651         { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
 652         { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
 653         { /* sentinel */ }
 654 };
 655 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 656
 657 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 658 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 659 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 660 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 661
 662 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 663 {
 664         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 665         return chnenbl0 + event * 4;
 666 }
 667
 668 static int sdma_config_ownership(struct sdma_channel *sdmac,
 669                 bool event_override, bool mcu_override, bool dsp_override)
 670 {
 671         struct sdma_engine *sdma = sdmac->sdma;
 672         int channel = sdmac->channel;
 673         unsigned long evt, mcu, dsp;
 674
 675         if (event_override && mcu_override && dsp_override)
 676                 return -EINVAL;
 677
 678         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 679         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 680         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 681
 682         if (dsp_override)
 683                 __clear_bit(channel, &dsp);
 684         else
 685                 __set_bit(channel, &dsp);
 686
 687         if (event_override)
 688                 __clear_bit(channel, &evt);
 689         else
 690                 __set_bit(channel, &evt);
 691
 692         if (mcu_override)
 693                 __clear_bit(channel, &mcu);
 694         else
 695                 __set_bit(channel, &mcu);
 696
 697         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 698         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 699         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 700
 701         return 0;
 702 }
 703
 704 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 705 {
 706         writel(BIT(channel), sdma->regs + SDMA_H_START);
 707 }
 708
 709 /*
 710  * sdma_run_channel0 - run a channel and wait till it's done
 711  */
 712 static int sdma_run_channel0(struct sdma_engine *sdma)
 713 {
 714         int ret;
 715         u32 reg;
 716
 717         sdma_enable_channel(sdma, 0);
 718
 719         ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
 720                                                 reg, !(reg & 1), 1, 500);
 721         if (ret)
 722                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 723
 724         /* Set bits of CONFIG register with dynamic context switching */
 725         reg = readl(sdma->regs + SDMA_H_CONFIG);
 726         if ((reg & SDMA_H_CONFIG_CSM) == 0) {
 727                 reg |= SDMA_H_CONFIG_CSM;
 728                 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
 729         }
 730
 731         return ret;
 732 }
 733
 734 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 735                 u32 address)
 736 {
 737         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
 738         void *buf_virt;
 739         dma_addr_t buf_phys;
 740         int ret;
 741         unsigned long flags;
 742
 743         buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
 744         if (!buf_virt) {
 745                 return -ENOMEM;
 746         }
 747
 748         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 749
 750         bd0->mode.command = C0_SETPM;
 751         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
 752         bd0->mode.count = size / 2;
 753         bd0->buffer_addr = buf_phys;
 754         bd0->ext_buffer_addr = address;
 755
 756         memcpy(buf_virt, buf, size);
 757
 758         ret = sdma_run_channel0(sdma);
 759
 760         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 761
 762         dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
 763
 764         return ret;
 765 }
 766
 767 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 768 {
 769         struct sdma_engine *sdma = sdmac->sdma;
 770         int channel = sdmac->channel;
 771         unsigned long val;
 772         u32 chnenbl = chnenbl_ofs(sdma, event);
 773
 774         val = readl_relaxed(sdma->regs + chnenbl);
 775         __set_bit(channel, &val);
 776         writel_relaxed(val, sdma->regs + chnenbl);
 777 }
 778
 779 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 780 {
 781         struct sdma_engine *sdma = sdmac->sdma;
 782         int channel = sdmac->channel;
 783         u32 chnenbl = chnenbl_ofs(sdma, event);
 784         unsigned long val;
 785
 786         val = readl_relaxed(sdma->regs + chnenbl);
 787         __clear_bit(channel, &val);
 788         writel_relaxed(val, sdma->regs + chnenbl);
 789 }
 790
 791 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
 792 {
 793         return container_of(t, struct sdma_desc, vd.tx);
 794 }
 795
 796 static void sdma_start_desc(struct sdma_channel *sdmac)
 797 {
 798         struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
 799         struct sdma_desc *desc;
 800         struct sdma_engine *sdma = sdmac->sdma;
 801         int channel = sdmac->channel;
 802
 803         if (!vd) {
 804                 sdmac->desc = NULL;
 805                 return;
 806         }
 807         sdmac->desc = desc = to_sdma_desc(&vd->tx);
 808
 809         list_del(&vd->node);
 810
 811         sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
 812         sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
 813         sdma_enable_channel(sdma, sdmac->channel);
 814 }
 815
 816 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
 817 {
 818         struct sdma_buffer_descriptor *bd;
 819         int error = 0;
 820         enum dma_status old_status = sdmac->status;
 821
 822         /*
 823          * loop mode. Iterate over descriptors, re-setup them and
 824          * call callback function.
 825          */
 826         while (sdmac->desc) {
 827                 struct sdma_desc *desc = sdmac->desc;
 828
 829                 bd = &desc->bd[desc->buf_tail];
 830
 831                 if (bd->mode.status & BD_DONE)
 832                         break;
 833
 834                 if (bd->mode.status & BD_RROR) {
 835                         bd->mode.status &= ~BD_RROR;
 836                         sdmac->status = DMA_ERROR;
 837                         error = -EIO;
 838                 }
 839
 840                /*
 841                 * We use bd->mode.count to calculate the residue, since contains
 842                 * the number of bytes present in the current buffer descriptor.
 843                 */
 844
 845                 desc->chn_real_count = bd->mode.count;
 846                 bd->mode.status |= BD_DONE;
 847                 bd->mode.count = desc->period_len;
 848                 desc->buf_ptail = desc->buf_tail;
 849                 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
 850
 851                 /*
 852                  * The callback is called from the interrupt context in order
 853                  * to reduce latency and to avoid the risk of altering the
 854                  * SDMA transaction status by the time the client tasklet is
 855                  * executed.
 856                  */
 857                 spin_unlock(&sdmac->vc.lock);
 858                 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
 859                 spin_lock(&sdmac->vc.lock);
 860
 861                 if (error)
 862                         sdmac->status = old_status;
 863         }
 864 }
 865
 866 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
 867 {
 868         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 869         struct sdma_buffer_descriptor *bd;
 870         int i, error = 0;
 871
 872         sdmac->desc->chn_real_count = 0;
 873         /*
 874          * non loop mode. Iterate over all descriptors, collect
 875          * errors and call callback function
 876          */
 877         for (i = 0; i < sdmac->desc->num_bd; i++) {
 878                 bd = &sdmac->desc->bd[i];
 879
 880                  if (bd->mode.status & (BD_DONE | BD_RROR))
 881                         error = -EIO;
 882                  sdmac->desc->chn_real_count += bd->mode.count;
 883         }
 884
 885         if (error)
 886                 sdmac->status = DMA_ERROR;
 887         else
 888                 sdmac->status = DMA_COMPLETE;
 889 }
 890
 891 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 892 {
 893         struct sdma_engine *sdma = dev_id;
 894         unsigned long stat;
 895
 896         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 897         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 898         /* channel 0 is special and not handled here, see run_channel0() */
 899         stat &= ~1;
 900
 901         while (stat) {
 902                 int channel = fls(stat) - 1;
 903                 struct sdma_channel *sdmac = &sdma->channel[channel];
 904                 struct sdma_desc *desc;
 905
 906                 spin_lock(&sdmac->vc.lock);
 907                 desc = sdmac->desc;
 908                 if (desc) {
 909                         if (sdmac->flags & IMX_DMA_SG_LOOP) {
 910                                 sdma_update_channel_loop(sdmac);
 911                         } else {
 912                                 mxc_sdma_handle_channel_normal(sdmac);
 913                                 vchan_cookie_complete(&desc->vd);
 914                                 sdma_start_desc(sdmac);
 915                         }
 916                 }
 917
 918                 spin_unlock(&sdmac->vc.lock);
 919                 __clear_bit(channel, &stat);
 920         }
 921
 922         return IRQ_HANDLED;
 923 }
 924
 925 /*
 926  * sets the pc of SDMA script according to the peripheral type
 927  */
 928 static void sdma_get_pc(struct sdma_channel *sdmac,
 929                 enum sdma_peripheral_type peripheral_type)
 930 {
 931         struct sdma_engine *sdma = sdmac->sdma;
 932         int per_2_emi = 0, emi_2_per = 0;
 933         /*
 934          * These are needed once we start to support transfers between
 935          * two peripherals or memory-to-memory transfers
 936          */
 937         int per_2_per = 0, emi_2_emi = 0;
 938
 939         sdmac->pc_from_device = 0;
 940         sdmac->pc_to_device = 0;
 941         sdmac->device_to_device = 0;
 942         sdmac->pc_to_pc = 0;
 943         sdmac->is_ram_script = false;
 944
 945         switch (peripheral_type) {
 946         case IMX_DMATYPE_MEMORY:
 947                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 948                 break;
 949         case IMX_DMATYPE_DSP:
 950                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 951                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 952                 break;
 953         case IMX_DMATYPE_FIRI:
 954                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 955                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 956                 break;
 957         case IMX_DMATYPE_UART:
 958                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 959                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 960                 break;
 961         case IMX_DMATYPE_UART_SP:
 962                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 963                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 964                 break;
 965         case IMX_DMATYPE_ATA:
 966                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 967                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 968                 break;
 969         case IMX_DMATYPE_CSPI:
 970                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 971
 972                 /* Use rom script mcu_2_app if ERR009165 fixed */
 973                 if (sdmac->sdma->drvdata->ecspi_fixed) {
 974                         emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 975                 } else {
 976                         emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
 977                         sdmac->is_ram_script = true;
 978                 }
 979
 980                 break;
 981         case IMX_DMATYPE_EXT:
 982         case IMX_DMATYPE_SSI:
 983         case IMX_DMATYPE_SAI:
 984                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 985                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 986                 break;
 987         case IMX_DMATYPE_SSI_DUAL:
 988                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 989                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 990                 sdmac->is_ram_script = true;
 991                 break;
 992         case IMX_DMATYPE_SSI_SP:
 993         case IMX_DMATYPE_MMC:
 994         case IMX_DMATYPE_SDHC:
 995         case IMX_DMATYPE_CSPI_SP:
 996         case IMX_DMATYPE_ESAI:
 997         case IMX_DMATYPE_MSHC_SP:
 998                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 999                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1000                 break;
1001         case IMX_DMATYPE_ASRC:
1002                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
1003                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
1004                 per_2_per = sdma->script_addrs->per_2_per_addr;
1005                 sdmac->is_ram_script = true;
1006                 break;
1007         case IMX_DMATYPE_ASRC_SP:
1008                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
1009                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
1010                 per_2_per = sdma->script_addrs->per_2_per_addr;
1011                 break;
1012         case IMX_DMATYPE_MSHC:
1013                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
1014                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
1015                 break;
1016         case IMX_DMATYPE_CCM:
1017                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
1018                 break;
1019         case IMX_DMATYPE_SPDIF:
1020                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
1021                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
1022                 break;
1023         case IMX_DMATYPE_IPU_MEMORY:
1024                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
1025                 break;
1026         default:
1027                 break;
1028         }
1029
1030         sdmac->pc_from_device = per_2_emi;
1031         sdmac->pc_to_device = emi_2_per;
1032         sdmac->device_to_device = per_2_per;
1033         sdmac->pc_to_pc = emi_2_emi;
1034 }
1035
1036 static int sdma_load_context(struct sdma_channel *sdmac)
1037 {
1038         struct sdma_engine *sdma = sdmac->sdma;
1039         int channel = sdmac->channel;
1040         int load_address;
1041         struct sdma_context_data *context = sdma->context;
1042         struct sdma_buffer_descriptor *bd0 = sdma->bd0;
1043         int ret;
1044         unsigned long flags;
1045
1046         if (sdmac->direction == DMA_DEV_TO_MEM)
1047                 load_address = sdmac->pc_from_device;
1048         else if (sdmac->direction == DMA_DEV_TO_DEV)
1049                 load_address = sdmac->device_to_device;
1050         else if (sdmac->direction == DMA_MEM_TO_MEM)
1051                 load_address = sdmac->pc_to_pc;
1052         else
1053                 load_address = sdmac->pc_to_device;
1054
1055         if (load_address < 0)
1056                 return load_address;
1057
1058         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1059         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1060         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1061         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1062         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1063         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1064
1065         spin_lock_irqsave(&sdma->channel_0_lock, flags);
1066
1067         memset(context, 0, sizeof(*context));
1068         context->channel_state.pc = load_address;
1069
1070         /* Send by context the event mask,base address for peripheral
1071          * and watermark level
1072          */
1073         context->gReg[0] = sdmac->event_mask[1];
1074         context->gReg[1] = sdmac->event_mask[0];
1075         context->gReg[2] = sdmac->per_addr;
1076         context->gReg[6] = sdmac->shp_addr;
1077         context->gReg[7] = sdmac->watermark_level;
1078
1079         bd0->mode.command = C0_SETDM;
1080         bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1081         bd0->mode.count = sizeof(*context) / 4;
1082         bd0->buffer_addr = sdma->context_phys;
1083         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1084         ret = sdma_run_channel0(sdma);
1085
1086         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1087
1088         return ret;
1089 }
1090
1091 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1092 {
1093         return container_of(chan, struct sdma_channel, vc.chan);
1094 }
1095
1096 static int sdma_disable_channel(struct dma_chan *chan)
1097 {
1098         struct sdma_channel *sdmac = to_sdma_chan(chan);
1099         struct sdma_engine *sdma = sdmac->sdma;
1100         int channel = sdmac->channel;
1101
1102         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1103         sdmac->status = DMA_ERROR;
1104
1105         return 0;
1106 }
1107 static void sdma_channel_terminate_work(struct work_struct *work)
1108 {
1109         struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1110                                                   terminate_worker);
1111         /*
1112          * According to NXP R&D team a delay of one BD SDMA cost time
1113          * (maximum is 1ms) should be added after disable of the channel
1114          * bit, to ensure SDMA core has really been stopped after SDMA
1115          * clients call .device_terminate_all.
1116          */
1117         usleep_range(1000, 2000);
1118
1119         vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
1120 }
1121
1122 static int sdma_terminate_all(struct dma_chan *chan)
1123 {
1124         struct sdma_channel *sdmac = to_sdma_chan(chan);
1125         unsigned long flags;
1126
1127         spin_lock_irqsave(&sdmac->vc.lock, flags);
1128
1129         sdma_disable_channel(chan);
1130
1131         if (sdmac->desc) {
1132                 vchan_terminate_vdesc(&sdmac->desc->vd);
1133                 /*
1134                  * move out current descriptor into terminated list so that
1135                  * it could be free in sdma_channel_terminate_work alone
1136                  * later without potential involving next descriptor raised
1137                  * up before the last descriptor terminated.
1138                  */
1139                 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
1140                 sdmac->desc = NULL;
1141                 schedule_work(&sdmac->terminate_worker);
1142         }
1143
1144         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1145
1146         return 0;
1147 }
1148
1149 static void sdma_channel_synchronize(struct dma_chan *chan)
1150 {
1151         struct sdma_channel *sdmac = to_sdma_chan(chan);
1152
1153         vchan_synchronize(&sdmac->vc);
1154
1155         flush_work(&sdmac->terminate_worker);
1156 }
1157
1158 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1159 {
1160         struct sdma_engine *sdma = sdmac->sdma;
1161
1162         int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1163         int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1164
1165         set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1166         set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1167
1168         if (sdmac->event_id0 > 31)
1169                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1170
1171         if (sdmac->event_id1 > 31)
1172                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1173
1174         /*
1175          * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1176          * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1177          * r0(event_mask[1]) and r1(event_mask[0]).
1178          */
1179         if (lwml > hwml) {
1180                 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1181                                                 SDMA_WATERMARK_LEVEL_HWML);
1182                 sdmac->watermark_level |= hwml;
1183                 sdmac->watermark_level |= lwml << 16;
1184                 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1185         }
1186
1187         if (sdmac->per_address2 >= sdma->spba_start_addr &&
1188                         sdmac->per_address2 <= sdma->spba_end_addr)
1189                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1190
1191         if (sdmac->per_address >= sdma->spba_start_addr &&
1192                         sdmac->per_address <= sdma->spba_end_addr)
1193                 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1194
1195         sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1196 }
1197
1198 static int sdma_config_channel(struct dma_chan *chan)
1199 {
1200         struct sdma_channel *sdmac = to_sdma_chan(chan);
1201
1202         sdma_disable_channel(chan);
1203
1204         sdmac->event_mask[0] = 0;
1205         sdmac->event_mask[1] = 0;
1206         sdmac->shp_addr = 0;
1207         sdmac->per_addr = 0;
1208
1209         switch (sdmac->peripheral_type) {
1210         case IMX_DMATYPE_DSP:
1211                 sdma_config_ownership(sdmac, false, true, true);
1212                 break;
1213         case IMX_DMATYPE_MEMORY:
1214                 sdma_config_ownership(sdmac, false, true, false);
1215                 break;
1216         default:
1217                 sdma_config_ownership(sdmac, true, true, false);
1218                 break;
1219         }
1220
1221         sdma_get_pc(sdmac, sdmac->peripheral_type);
1222
1223         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1224                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1225                 /* Handle multiple event channels differently */
1226                 if (sdmac->event_id1) {
1227                         if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1228                             sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1229                                 sdma_set_watermarklevel_for_p2p(sdmac);
1230                 } else
1231                         __set_bit(sdmac->event_id0, sdmac->event_mask);
1232
1233                 /* Address */
1234                 sdmac->shp_addr = sdmac->per_address;
1235                 sdmac->per_addr = sdmac->per_address2;
1236         } else {
1237                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1244                 unsigned int priority)
1245 {
1246         struct sdma_engine *sdma = sdmac->sdma;
1247         int channel = sdmac->channel;
1248
1249         if (priority < MXC_SDMA_MIN_PRIORITY
1250             || priority > MXC_SDMA_MAX_PRIORITY) {
1251                 return -EINVAL;
1252         }
1253
1254         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1255
1256         return 0;
1257 }
1258
1259 static int sdma_request_channel0(struct sdma_engine *sdma)
1260 {
1261         int ret = -EBUSY;
1262
1263         sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1264                                         GFP_NOWAIT);
1265         if (!sdma->bd0) {
1266                 ret = -ENOMEM;
1267                 goto out;
1268         }
1269
1270         sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1271         sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1272
1273         sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1274         return 0;
1275 out:
1276
1277         return ret;
1278 }
1279
1280
1281 static int sdma_alloc_bd(struct sdma_desc *desc)
1282 {
1283         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1284         int ret = 0;
1285
1286         desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1287                                        &desc->bd_phys, GFP_NOWAIT);
1288         if (!desc->bd) {
1289                 ret = -ENOMEM;
1290                 goto out;
1291         }
1292 out:
1293         return ret;
1294 }
1295
1296 static void sdma_free_bd(struct sdma_desc *desc)
1297 {
1298         u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1299
1300         dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1301                           desc->bd_phys);
1302 }
1303
1304 static void sdma_desc_free(struct virt_dma_desc *vd)
1305 {
1306         struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1307
1308         sdma_free_bd(desc);
1309         kfree(desc);
1310 }
1311
1312 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1313 {
1314         struct sdma_channel *sdmac = to_sdma_chan(chan);
1315         struct imx_dma_data *data = chan->private;
1316         struct imx_dma_data mem_data;
1317         int prio, ret;
1318
1319         /*
1320          * MEMCPY may never setup chan->private by filter function such as
1321          * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1322          * Please note in any other slave case, you have to setup chan->private
1323          * with 'struct imx_dma_data' in your own filter function if you want to
1324          * request dma channel by dma_request_channel() rather than
1325          * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1326          * to warn you to correct your filter function.
1327          */
1328         if (!data) {
1329                 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1330                 mem_data.priority = 2;
1331                 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1332                 mem_data.dma_request = 0;
1333                 mem_data.dma_request2 = 0;
1334                 data = &mem_data;
1335
1336                 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1337         }
1338
1339         switch (data->priority) {
1340         case DMA_PRIO_HIGH:
1341                 prio = 3;
1342                 break;
1343         case DMA_PRIO_MEDIUM:
1344                 prio = 2;
1345                 break;
1346         case DMA_PRIO_LOW:
1347         default:
1348                 prio = 1;
1349                 break;
1350         }
1351
1352         sdmac->peripheral_type = data->peripheral_type;
1353         sdmac->event_id0 = data->dma_request;
1354         sdmac->event_id1 = data->dma_request2;
1355
1356         ret = clk_enable(sdmac->sdma->clk_ipg);
1357         if (ret)
1358                 return ret;
1359         ret = clk_enable(sdmac->sdma->clk_ahb);
1360         if (ret)
1361                 goto disable_clk_ipg;
1362
1363         ret = sdma_set_channel_priority(sdmac, prio);
1364         if (ret)
1365                 goto disable_clk_ahb;
1366
1367         return 0;
1368
1369 disable_clk_ahb:
1370         clk_disable(sdmac->sdma->clk_ahb);
1371 disable_clk_ipg:
1372         clk_disable(sdmac->sdma->clk_ipg);
1373         return ret;
1374 }
1375
1376 static void sdma_free_chan_resources(struct dma_chan *chan)
1377 {
1378         struct sdma_channel *sdmac = to_sdma_chan(chan);
1379         struct sdma_engine *sdma = sdmac->sdma;
1380
1381         sdma_terminate_all(chan);
1382
1383         sdma_channel_synchronize(chan);
1384
1385         sdma_event_disable(sdmac, sdmac->event_id0);
1386         if (sdmac->event_id1)
1387                 sdma_event_disable(sdmac, sdmac->event_id1);
1388
1389         sdmac->event_id0 = 0;
1390         sdmac->event_id1 = 0;
1391
1392         sdma_set_channel_priority(sdmac, 0);
1393
1394         clk_disable(sdma->clk_ipg);
1395         clk_disable(sdma->clk_ahb);
1396 }
1397
1398 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1399                                 enum dma_transfer_direction direction, u32 bds)
1400 {
1401         struct sdma_desc *desc;
1402
1403         if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
1404                 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
1405                 goto err_out;
1406         }
1407
1408         desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1409         if (!desc)
1410                 goto err_out;
1411
1412         sdmac->status = DMA_IN_PROGRESS;
1413         sdmac->direction = direction;
1414         sdmac->flags = 0;
1415
1416         desc->chn_count = 0;
1417         desc->chn_real_count = 0;
1418         desc->buf_tail = 0;
1419         desc->buf_ptail = 0;
1420         desc->sdmac = sdmac;
1421         desc->num_bd = bds;
1422
1423         if (sdma_alloc_bd(desc))
1424                 goto err_desc_out;
1425
1426         /* No slave_config called in MEMCPY case, so do here */
1427         if (direction == DMA_MEM_TO_MEM)
1428                 sdma_config_ownership(sdmac, false, true, false);
1429
1430         if (sdma_load_context(sdmac))
1431                 goto err_bd_out;
1432
1433         return desc;
1434
1435 err_bd_out:
1436         sdma_free_bd(desc);
1437 err_desc_out:
1438         kfree(desc);
1439 err_out:
1440         return NULL;
1441 }
1442
1443 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1444                 struct dma_chan *chan, dma_addr_t dma_dst,
1445                 dma_addr_t dma_src, size_t len, unsigned long flags)
1446 {
1447         struct sdma_channel *sdmac = to_sdma_chan(chan);
1448         struct sdma_engine *sdma = sdmac->sdma;
1449         int channel = sdmac->channel;
1450         size_t count;
1451         int i = 0, param;
1452         struct sdma_buffer_descriptor *bd;
1453         struct sdma_desc *desc;
1454
1455         if (!chan || !len)
1456                 return NULL;
1457
1458         dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1459                 &dma_src, &dma_dst, len, channel);
1460
1461         desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1462                                         len / SDMA_BD_MAX_CNT + 1);
1463         if (!desc)
1464                 return NULL;
1465
1466         do {
1467                 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1468                 bd = &desc->bd[i];
1469                 bd->buffer_addr = dma_src;
1470                 bd->ext_buffer_addr = dma_dst;
1471                 bd->mode.count = count;
1472                 desc->chn_count += count;
1473                 bd->mode.command = 0;
1474
1475                 dma_src += count;
1476                 dma_dst += count;
1477                 len -= count;
1478                 i++;
1479
1480                 param = BD_DONE | BD_EXTD | BD_CONT;
1481                 /* last bd */
1482                 if (!len) {
1483                         param |= BD_INTR;
1484                         param |= BD_LAST;
1485                         param &= ~BD_CONT;
1486                 }
1487
1488                 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1489                                 i, count, bd->buffer_addr,
1490                                 param & BD_WRAP ? "wrap" : "",
1491                                 param & BD_INTR ? " intr" : "");
1492
1493                 bd->mode.status = param;
1494         } while (len);
1495
1496         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1497 }
1498
1499 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1500                 struct dma_chan *chan, struct scatterlist *sgl,
1501                 unsigned int sg_len, enum dma_transfer_direction direction,
1502                 unsigned long flags, void *context)
1503 {
1504         struct sdma_channel *sdmac = to_sdma_chan(chan);
1505         struct sdma_engine *sdma = sdmac->sdma;
1506         int i, count;
1507         int channel = sdmac->channel;
1508         struct scatterlist *sg;
1509         struct sdma_desc *desc;
1510
1511         sdma_config_write(chan, &sdmac->slave_config, direction);
1512
1513         desc = sdma_transfer_init(sdmac, direction, sg_len);
1514         if (!desc)
1515                 goto err_out;
1516
1517         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1518                         sg_len, channel);
1519
1520         for_each_sg(sgl, sg, sg_len, i) {
1521                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1522                 int param;
1523
1524                 bd->buffer_addr = sg->dma_address;
1525
1526                 count = sg_dma_len(sg);
1527
1528                 if (count > SDMA_BD_MAX_CNT) {
1529                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1530                                         channel, count, SDMA_BD_MAX_CNT);
1531                         goto err_bd_out;
1532                 }
1533
1534                 bd->mode.count = count;
1535                 desc->chn_count += count;
1536
1537                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1538                         goto err_bd_out;
1539
1540                 switch (sdmac->word_size) {
1541                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1542                         bd->mode.command = 0;
1543                         if (count & 3 || sg->dma_address & 3)
1544                                 goto err_bd_out;
1545                         break;
1546                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1547                         bd->mode.command = 2;
1548                         if (count & 1 || sg->dma_address & 1)
1549                                 goto err_bd_out;
1550                         break;
1551                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1552                         bd->mode.command = 1;
1553                         break;
1554                 default:
1555                         goto err_bd_out;
1556                 }
1557
1558                 param = BD_DONE | BD_EXTD | BD_CONT;
1559
1560                 if (i + 1 == sg_len) {
1561                         param |= BD_INTR;
1562                         param |= BD_LAST;
1563                         param &= ~BD_CONT;
1564                 }
1565
1566                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1567                                 i, count, (u64)sg->dma_address,
1568                                 param & BD_WRAP ? "wrap" : "",
1569                                 param & BD_INTR ? " intr" : "");
1570
1571                 bd->mode.status = param;
1572         }
1573
1574         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1575 err_bd_out:
1576         sdma_free_bd(desc);
1577         kfree(desc);
1578 err_out:
1579         sdmac->status = DMA_ERROR;
1580         return NULL;
1581 }
1582
1583 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1584                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1585                 size_t period_len, enum dma_transfer_direction direction,
1586                 unsigned long flags)
1587 {
1588         struct sdma_channel *sdmac = to_sdma_chan(chan);
1589         struct sdma_engine *sdma = sdmac->sdma;
1590         int num_periods = buf_len / period_len;
1591         int channel = sdmac->channel;
1592         int i = 0, buf = 0;
1593         struct sdma_desc *desc;
1594
1595         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1596
1597         sdma_config_write(chan, &sdmac->slave_config, direction);
1598
1599         desc = sdma_transfer_init(sdmac, direction, num_periods);
1600         if (!desc)
1601                 goto err_out;
1602
1603         desc->period_len = period_len;
1604
1605         sdmac->flags |= IMX_DMA_SG_LOOP;
1606
1607         if (period_len > SDMA_BD_MAX_CNT) {
1608                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1609                                 channel, period_len, SDMA_BD_MAX_CNT);
1610                 goto err_bd_out;
1611         }
1612
1613         while (buf < buf_len) {
1614                 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1615                 int param;
1616
1617                 bd->buffer_addr = dma_addr;
1618
1619                 bd->mode.count = period_len;
1620
1621                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1622                         goto err_bd_out;
1623                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1624                         bd->mode.command = 0;
1625                 else
1626                         bd->mode.command = sdmac->word_size;
1627
1628                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1629                 if (i + 1 == num_periods)
1630                         param |= BD_WRAP;
1631
1632                 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1633                                 i, period_len, (u64)dma_addr,
1634                                 param & BD_WRAP ? "wrap" : "",
1635                                 param & BD_INTR ? " intr" : "");
1636
1637                 bd->mode.status = param;
1638
1639                 dma_addr += period_len;
1640                 buf += period_len;
1641
1642                 i++;
1643         }
1644
1645         return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1646 err_bd_out:
1647         sdma_free_bd(desc);
1648         kfree(desc);
1649 err_out:
1650         sdmac->status = DMA_ERROR;
1651         return NULL;
1652 }
1653
1654 static int sdma_config_write(struct dma_chan *chan,
1655                        struct dma_slave_config *dmaengine_cfg,
1656                        enum dma_transfer_direction direction)
1657 {
1658         struct sdma_channel *sdmac = to_sdma_chan(chan);
1659
1660         if (direction == DMA_DEV_TO_MEM) {
1661                 sdmac->per_address = dmaengine_cfg->src_addr;
1662                 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1663                         dmaengine_cfg->src_addr_width;
1664                 sdmac->word_size = dmaengine_cfg->src_addr_width;
1665         } else if (direction == DMA_DEV_TO_DEV) {
1666                 sdmac->per_address2 = dmaengine_cfg->src_addr;
1667                 sdmac->per_address = dmaengine_cfg->dst_addr;
1668                 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1669                         SDMA_WATERMARK_LEVEL_LWML;
1670                 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1671                         SDMA_WATERMARK_LEVEL_HWML;
1672                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1673         } else {
1674                 sdmac->per_address = dmaengine_cfg->dst_addr;
1675                 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1676                         dmaengine_cfg->dst_addr_width;
1677                 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1678         }
1679         sdmac->direction = direction;
1680         return sdma_config_channel(chan);
1681 }
1682
1683 static int sdma_config(struct dma_chan *chan,
1684                        struct dma_slave_config *dmaengine_cfg)
1685 {
1686         struct sdma_channel *sdmac = to_sdma_chan(chan);
1687
1688         memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1689
1690         /* Set ENBLn earlier to make sure dma request triggered after that */
1691         if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1692                 return -EINVAL;
1693         sdma_event_enable(sdmac, sdmac->event_id0);
1694
1695         if (sdmac->event_id1) {
1696                 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1697                         return -EINVAL;
1698                 sdma_event_enable(sdmac, sdmac->event_id1);
1699         }
1700
1701         return 0;
1702 }
1703
1704 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1705                                       dma_cookie_t cookie,
1706                                       struct dma_tx_state *txstate)
1707 {
1708         struct sdma_channel *sdmac = to_sdma_chan(chan);
1709         struct sdma_desc *desc = NULL;
1710         u32 residue;
1711         struct virt_dma_desc *vd;
1712         enum dma_status ret;
1713         unsigned long flags;
1714
1715         ret = dma_cookie_status(chan, cookie, txstate);
1716         if (ret == DMA_COMPLETE || !txstate)
1717                 return ret;
1718
1719         spin_lock_irqsave(&sdmac->vc.lock, flags);
1720
1721         vd = vchan_find_desc(&sdmac->vc, cookie);
1722         if (vd)
1723                 desc = to_sdma_desc(&vd->tx);
1724         else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
1725                 desc = sdmac->desc;
1726
1727         if (desc) {
1728                 if (sdmac->flags & IMX_DMA_SG_LOOP)
1729                         residue = (desc->num_bd - desc->buf_ptail) *
1730                                 desc->period_len - desc->chn_real_count;
1731                 else
1732                         residue = desc->chn_count - desc->chn_real_count;
1733         } else {
1734                 residue = 0;
1735         }
1736
1737         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1738
1739         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1740                          residue);
1741
1742         return sdmac->status;
1743 }
1744
1745 static void sdma_issue_pending(struct dma_chan *chan)
1746 {
1747         struct sdma_channel *sdmac = to_sdma_chan(chan);
1748         unsigned long flags;
1749
1750         spin_lock_irqsave(&sdmac->vc.lock, flags);
1751         if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1752                 sdma_start_desc(sdmac);
1753         spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1754 }
1755
1756 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1757 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1758 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
1759 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
1760
1761 static void sdma_add_scripts(struct sdma_engine *sdma,
1762                 const struct sdma_script_start_addrs *addr)
1763 {
1764         s32 *addr_arr = (u32 *)addr;
1765         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1766         int i;
1767
1768         /* use the default firmware in ROM if missing external firmware */
1769         if (!sdma->script_number)
1770                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1771
1772         if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1773                                   / sizeof(s32)) {
1774                 dev_err(sdma->dev,
1775                         "SDMA script number %d not match with firmware.\n",
1776                         sdma->script_number);
1777                 return;
1778         }
1779
1780         for (i = 0; i < sdma->script_number; i++)
1781                 if (addr_arr[i] > 0)
1782                         saddr_arr[i] = addr_arr[i];
1783
1784         /*
1785          * For compatibility with NXP internal legacy kernel before 4.19 which
1786          * is based on uart ram script and mainline kernel based on uart rom
1787          * script, both uart ram/rom scripts are present in newer sdma
1788          * firmware. Use the rom versions if they are present (V3 or newer).
1789          */
1790         if (sdma->script_number >= SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3) {
1791                 if (addr->uart_2_mcu_rom_addr)
1792                         sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_rom_addr;
1793                 if (addr->uartsh_2_mcu_rom_addr)
1794                         sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_rom_addr;
1795         }
1796 }
1797
1798 static void sdma_load_firmware(const struct firmware *fw, void *context)
1799 {
1800         struct sdma_engine *sdma = context;
1801         const struct sdma_firmware_header *header;
1802         const struct sdma_script_start_addrs *addr;
1803         unsigned short *ram_code;
1804
1805         if (!fw) {
1806                 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1807                 /* In this case we just use the ROM firmware. */
1808                 return;
1809         }
1810
1811         if (fw->size < sizeof(*header))
1812                 goto err_firmware;
1813
1814         header = (struct sdma_firmware_header *)fw->data;
1815
1816         if (header->magic != SDMA_FIRMWARE_MAGIC)
1817                 goto err_firmware;
1818         if (header->ram_code_start + header->ram_code_size > fw->size)
1819                 goto err_firmware;
1820         switch (header->version_major) {
1821         case 1:
1822                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1823                 break;
1824         case 2:
1825                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1826                 break;
1827         case 3:
1828                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1829                 break;
1830         case 4:
1831                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1832                 break;
1833         default:
1834                 dev_err(sdma->dev, "unknown firmware version\n");
1835                 goto err_firmware;
1836         }
1837
1838         addr = (void *)header + header->script_addrs_start;
1839         ram_code = (void *)header + header->ram_code_start;
1840
1841         clk_enable(sdma->clk_ipg);
1842         clk_enable(sdma->clk_ahb);
1843         /* download the RAM image for SDMA */
1844         sdma_load_script(sdma, ram_code,
1845                         header->ram_code_size,
1846                         addr->ram_code_start_addr);
1847         clk_disable(sdma->clk_ipg);
1848         clk_disable(sdma->clk_ahb);
1849
1850         sdma_add_scripts(sdma, addr);
1851
1852         sdma->fw_loaded = true;
1853
1854         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1855                         header->version_major,
1856                         header->version_minor);
1857
1858 err_firmware:
1859         release_firmware(fw);
1860 }
1861
1862 #define EVENT_REMAP_CELLS 3
1863
1864 static int sdma_event_remap(struct sdma_engine *sdma)
1865 {
1866         struct device_node *np = sdma->dev->of_node;
1867         struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1868         struct property *event_remap;
1869         struct regmap *gpr;
1870         char propname[] = "fsl,sdma-event-remap";
1871         u32 reg, val, shift, num_map, i;
1872         int ret = 0;
1873
1874         if (IS_ERR(np) || !gpr_np)
1875                 goto out;
1876
1877         event_remap = of_find_property(np, propname, NULL);
1878         num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1879         if (!num_map) {
1880                 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1881                 goto out;
1882         } else if (num_map % EVENT_REMAP_CELLS) {
1883                 dev_err(sdma->dev, "the property %s must modulo %d\n",
1884                                 propname, EVENT_REMAP_CELLS);
1885                 ret = -EINVAL;
1886                 goto out;
1887         }
1888
1889         gpr = syscon_node_to_regmap(gpr_np);
1890         if (IS_ERR(gpr)) {
1891                 dev_err(sdma->dev, "failed to get gpr regmap\n");
1892                 ret = PTR_ERR(gpr);
1893                 goto out;
1894         }
1895
1896         for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1897                 ret = of_property_read_u32_index(np, propname, i, &reg);
1898                 if (ret) {
1899                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1900                                         propname, i);
1901                         goto out;
1902                 }
1903
1904                 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1905                 if (ret) {
1906                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1907                                         propname, i + 1);
1908                         goto out;
1909                 }
1910
1911                 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1912                 if (ret) {
1913                         dev_err(sdma->dev, "failed to read property %s index %d\n",
1914                                         propname, i + 2);
1915                         goto out;
1916                 }
1917
1918                 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1919         }
1920
1921 out:
1922         if (gpr_np)
1923                 of_node_put(gpr_np);
1924
1925         return ret;
1926 }
1927
1928 static int sdma_get_firmware(struct sdma_engine *sdma,
1929                 const char *fw_name)
1930 {
1931         int ret;
1932
1933         ret = request_firmware_nowait(THIS_MODULE,
1934                         FW_ACTION_UEVENT, fw_name, sdma->dev,
1935                         GFP_KERNEL, sdma, sdma_load_firmware);
1936
1937         return ret;
1938 }
1939
1940 static int sdma_init(struct sdma_engine *sdma)
1941 {
1942         int i, ret;
1943         dma_addr_t ccb_phys;
1944
1945         ret = clk_enable(sdma->clk_ipg);
1946         if (ret)
1947                 return ret;
1948         ret = clk_enable(sdma->clk_ahb);
1949         if (ret)
1950                 goto disable_clk_ipg;
1951
1952         if (sdma->drvdata->check_ratio &&
1953             (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1954                 sdma->clk_ratio = 1;
1955
1956         /* Be sure SDMA has not started yet */
1957         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1958
1959         sdma->channel_control = dma_alloc_coherent(sdma->dev,
1960                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1961                         sizeof(struct sdma_context_data),
1962                         &ccb_phys, GFP_KERNEL);
1963
1964         if (!sdma->channel_control) {
1965                 ret = -ENOMEM;
1966                 goto err_dma_alloc;
1967         }
1968
1969         sdma->context = (void *)sdma->channel_control +
1970                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1971         sdma->context_phys = ccb_phys +
1972                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1973
1974         /* disable all channels */
1975         for (i = 0; i < sdma->drvdata->num_events; i++)
1976                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1977
1978         /* All channels have priority 0 */
1979         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1980                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1981
1982         ret = sdma_request_channel0(sdma);
1983         if (ret)
1984                 goto err_dma_alloc;
1985
1986         sdma_config_ownership(&sdma->channel[0], false, true, false);
1987
1988         /* Set Command Channel (Channel Zero) */
1989         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1990
1991         /* Set bits of CONFIG register but with static context switching */
1992         if (sdma->clk_ratio)
1993                 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1994         else
1995                 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1996
1997         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1998
1999         /* Initializes channel's priorities */
2000         sdma_set_channel_priority(&sdma->channel[0], 7);
2001
2002         clk_disable(sdma->clk_ipg);
2003         clk_disable(sdma->clk_ahb);
2004
2005         return 0;
2006
2007 err_dma_alloc:
2008         clk_disable(sdma->clk_ahb);
2009 disable_clk_ipg:
2010         clk_disable(sdma->clk_ipg);
2011         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
2012         return ret;
2013 }
2014
2015 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
2016 {
2017         struct sdma_channel *sdmac = to_sdma_chan(chan);
2018         struct imx_dma_data *data = fn_param;
2019
2020         if (!imx_dma_is_general_purpose(chan))
2021                 return false;
2022
2023         sdmac->data = *data;
2024         chan->private = &sdmac->data;
2025
2026         return true;
2027 }
2028
2029 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
2030                                    struct of_dma *ofdma)
2031 {
2032         struct sdma_engine *sdma = ofdma->of_dma_data;
2033         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
2034         struct imx_dma_data data;
2035
2036         if (dma_spec->args_count != 3)
2037                 return NULL;
2038
2039         data.dma_request = dma_spec->args[0];
2040         data.peripheral_type = dma_spec->args[1];
2041         data.priority = dma_spec->args[2];
2042         /*
2043          * init dma_request2 to zero, which is not used by the dts.
2044          * For P2P, dma_request2 is init from dma_request_channel(),
2045          * chan->private will point to the imx_dma_data, and in
2046          * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
2047          * be set to sdmac->event_id1.
2048          */
2049         data.dma_request2 = 0;
2050
2051         return __dma_request_channel(&mask, sdma_filter_fn, &data,
2052                                      ofdma->of_node);
2053 }
2054
2055 static int sdma_probe(struct platform_device *pdev)
2056 {
2057         struct device_node *np = pdev->dev.of_node;
2058         struct device_node *spba_bus;
2059         const char *fw_name;
2060         int ret;
2061         int irq;
2062         struct resource *iores;
2063         struct resource spba_res;
2064         int i;
2065         struct sdma_engine *sdma;
2066         s32 *saddr_arr;
2067
2068         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2069         if (ret)
2070                 return ret;
2071
2072         sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2073         if (!sdma)
2074                 return -ENOMEM;
2075
2076         spin_lock_init(&sdma->channel_0_lock);
2077
2078         sdma->dev = &pdev->dev;
2079         sdma->drvdata = of_device_get_match_data(sdma->dev);
2080
2081         irq = platform_get_irq(pdev, 0);
2082         if (irq < 0)
2083                 return irq;
2084
2085         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2086         sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2087         if (IS_ERR(sdma->regs))
2088                 return PTR_ERR(sdma->regs);
2089
2090         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2091         if (IS_ERR(sdma->clk_ipg))
2092                 return PTR_ERR(sdma->clk_ipg);
2093
2094         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2095         if (IS_ERR(sdma->clk_ahb))
2096                 return PTR_ERR(sdma->clk_ahb);
2097
2098         ret = clk_prepare(sdma->clk_ipg);
2099         if (ret)
2100                 return ret;
2101
2102         ret = clk_prepare(sdma->clk_ahb);
2103         if (ret)
2104                 goto err_clk;
2105
2106         ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2107                                sdma);
2108         if (ret)
2109                 goto err_irq;
2110
2111         sdma->irq = irq;
2112
2113         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2114         if (!sdma->script_addrs) {
2115                 ret = -ENOMEM;
2116                 goto err_irq;
2117         }
2118
2119         /* initially no scripts available */
2120         saddr_arr = (s32 *)sdma->script_addrs;
2121         for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
2122                 saddr_arr[i] = -EINVAL;
2123
2124         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2125         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2126         dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2127
2128         INIT_LIST_HEAD(&sdma->dma_device.channels);
2129         /* Initialize channel parameters */
2130         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2131                 struct sdma_channel *sdmac = &sdma->channel[i];
2132
2133                 sdmac->sdma = sdma;
2134
2135                 sdmac->channel = i;
2136                 sdmac->vc.desc_free = sdma_desc_free;
2137                 INIT_LIST_HEAD(&sdmac->terminated);
2138                 INIT_WORK(&sdmac->terminate_worker,
2139                                 sdma_channel_terminate_work);
2140                 /*
2141                  * Add the channel to the DMAC list. Do not add channel 0 though
2142                  * because we need it internally in the SDMA driver. This also means
2143                  * that channel 0 in dmaengine counting matches sdma channel 1.
2144                  */
2145                 if (i)
2146                         vchan_init(&sdmac->vc, &sdma->dma_device);
2147         }
2148
2149         ret = sdma_init(sdma);
2150         if (ret)
2151                 goto err_init;
2152
2153         ret = sdma_event_remap(sdma);
2154         if (ret)
2155                 goto err_init;
2156
2157         if (sdma->drvdata->script_addrs)
2158                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2159
2160         sdma->dma_device.dev = &pdev->dev;
2161
2162         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2163         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2164         sdma->dma_device.device_tx_status = sdma_tx_status;
2165         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2166         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2167         sdma->dma_device.device_config = sdma_config;
2168         sdma->dma_device.device_terminate_all = sdma_terminate_all;
2169         sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2170         sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2171         sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2172         sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2173         sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2174         sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2175         sdma->dma_device.device_issue_pending = sdma_issue_pending;
2176         sdma->dma_device.copy_align = 2;
2177         dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2178
2179         platform_set_drvdata(pdev, sdma);
2180
2181         ret = dma_async_device_register(&sdma->dma_device);
2182         if (ret) {
2183                 dev_err(&pdev->dev, "unable to register\n");
2184                 goto err_init;
2185         }
2186
2187         if (np) {
2188                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2189                 if (ret) {
2190                         dev_err(&pdev->dev, "failed to register controller\n");
2191                         goto err_register;
2192                 }
2193
2194                 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2195                 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2196                 if (!ret) {
2197                         sdma->spba_start_addr = spba_res.start;
2198                         sdma->spba_end_addr = spba_res.end;
2199                 }
2200                 of_node_put(spba_bus);
2201         }
2202
2203         /*
2204          * Because that device tree does not encode ROM script address,
2205          * the RAM script in firmware is mandatory for device tree
2206          * probe, otherwise it fails.
2207          */
2208         ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2209                                       &fw_name);
2210         if (ret) {
2211                 dev_warn(&pdev->dev, "failed to get firmware name\n");
2212         } else {
2213                 ret = sdma_get_firmware(sdma, fw_name);
2214                 if (ret)
2215                         dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2216         }
2217
2218         return 0;
2219
2220 err_register:
2221         dma_async_device_unregister(&sdma->dma_device);
2222 err_init:
2223         kfree(sdma->script_addrs);
2224 err_irq:
2225         clk_unprepare(sdma->clk_ahb);
2226 err_clk:
2227         clk_unprepare(sdma->clk_ipg);
2228         return ret;
2229 }
2230
2231 static int sdma_remove(struct platform_device *pdev)
2232 {
2233         struct sdma_engine *sdma = platform_get_drvdata(pdev);
2234         int i;
2235
2236         devm_free_irq(&pdev->dev, sdma->irq, sdma);
2237         dma_async_device_unregister(&sdma->dma_device);
2238         kfree(sdma->script_addrs);
2239         clk_unprepare(sdma->clk_ahb);
2240         clk_unprepare(sdma->clk_ipg);
2241         /* Kill the tasklet */
2242         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2243                 struct sdma_channel *sdmac = &sdma->channel[i];
2244
2245                 tasklet_kill(&sdmac->vc.task);
2246                 sdma_free_chan_resources(&sdmac->vc.chan);
2247         }
2248
2249         platform_set_drvdata(pdev, NULL);
2250         return 0;
2251 }
2252
2253 static struct platform_driver sdma_driver = {
2254         .driver         = {
2255                 .name   = "imx-sdma",
2256                 .of_match_table = sdma_dt_ids,
2257         },
2258         .remove         = sdma_remove,
2259         .probe          = sdma_probe,
2260 };
2261
2262 module_platform_driver(sdma_driver);
2263
2264 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2265 MODULE_DESCRIPTION("i.MX SDMA driver");
2266 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2267 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2268 #endif
2269 #if IS_ENABLED(CONFIG_SOC_IMX7D) || IS_ENABLED(CONFIG_SOC_IMX8M)
2270 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
2271 #endif
2272 MODULE_LICENSE("GPL");