1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/slab.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/workqueue.h>
12 #include <linux/aer.h>
14 #include <linux/io-64-nonatomic-lo-hi.h>
15 #include <linux/device.h>
16 #include <linux/idr.h>
17 #include <linux/intel-svm.h>
18 #include <linux/iommu.h>
19 #include <uapi/linux/idxd.h>
20 #include <linux/dmaengine.h>
21 #include "../dmaengine.h"
22 #include "registers.h"
25 MODULE_VERSION(IDXD_DRIVER_VERSION);
26 MODULE_LICENSE("GPL v2");
27 MODULE_AUTHOR("Intel Corporation");
29 static bool sva = true;
30 module_param(sva, bool, 0644);
31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
33 #define DRV_NAME "idxd"
38 static struct idxd_driver_data idxd_driver_data[] = {
41 .type = IDXD_TYPE_DSA,
42 .compl_size = sizeof(struct dsa_completion_record),
44 .dev_type = &dsa_device_type,
48 .type = IDXD_TYPE_IAX,
49 .compl_size = sizeof(struct iax_completion_record),
51 .dev_type = &iax_device_type,
55 static struct pci_device_id idxd_pci_tbl[] = {
56 /* DSA ver 1.0 platforms */
57 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
59 /* IAX ver 1.0 platforms */
60 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
63 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
65 static int idxd_setup_interrupts(struct idxd_device *idxd)
67 struct pci_dev *pdev = idxd->pdev;
68 struct device *dev = &pdev->dev;
69 struct idxd_irq_entry *irq_entry;
73 msixcnt = pci_msix_vec_count(pdev);
75 dev_err(dev, "Not MSI-X interrupt capable.\n");
79 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
81 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
84 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
87 * We implement 1 completion list per MSI-X entry except for
88 * entry 0, which is for errors and others.
90 idxd->irq_entries = kcalloc_node(msixcnt, sizeof(struct idxd_irq_entry),
91 GFP_KERNEL, dev_to_node(dev));
92 if (!idxd->irq_entries) {
97 for (i = 0; i < msixcnt; i++) {
98 idxd->irq_entries[i].id = i;
99 idxd->irq_entries[i].idxd = idxd;
100 idxd->irq_entries[i].vector = pci_irq_vector(pdev, i);
101 spin_lock_init(&idxd->irq_entries[i].list_lock);
104 irq_entry = &idxd->irq_entries[0];
105 rc = request_threaded_irq(irq_entry->vector, NULL, idxd_misc_thread,
106 0, "idxd-misc", irq_entry);
108 dev_err(dev, "Failed to allocate misc interrupt.\n");
112 dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", irq_entry->vector);
114 /* first MSI-X entry is not for wq interrupts */
115 idxd->num_wq_irqs = msixcnt - 1;
117 for (i = 1; i < msixcnt; i++) {
118 irq_entry = &idxd->irq_entries[i];
120 init_llist_head(&idxd->irq_entries[i].pending_llist);
121 INIT_LIST_HEAD(&idxd->irq_entries[i].work_list);
122 rc = request_threaded_irq(irq_entry->vector, NULL,
123 idxd_wq_thread, 0, "idxd-portal", irq_entry);
125 dev_err(dev, "Failed to allocate irq %d.\n", irq_entry->vector);
129 dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", i, irq_entry->vector);
130 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
132 * The MSIX vector enumeration starts at 1 with vector 0 being the
133 * misc interrupt that handles non I/O completion events. The
134 * interrupt handles are for IMS enumeration on guest. The misc
135 * interrupt vector does not require a handle and therefore we start
136 * the int_handles at index 0. Since 'i' starts at 1, the first
137 * int_handles index will be 0.
139 rc = idxd_device_request_int_handle(idxd, i, &idxd->int_handles[i - 1],
142 free_irq(irq_entry->vector, irq_entry);
145 dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i - 1]);
149 idxd_unmask_error_interrupts(idxd);
150 idxd_msix_perm_setup(idxd);
155 irq_entry = &idxd->irq_entries[i];
156 free_irq(irq_entry->vector, irq_entry);
158 idxd_device_release_int_handle(idxd,
159 idxd->int_handles[i], IDXD_IRQ_MSIX);
162 /* Disable error interrupt generation */
163 idxd_mask_error_interrupts(idxd);
165 pci_free_irq_vectors(pdev);
166 dev_err(dev, "No usable interrupts\n");
170 static int idxd_setup_wqs(struct idxd_device *idxd)
172 struct device *dev = &idxd->pdev->dev;
176 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
177 GFP_KERNEL, dev_to_node(dev));
181 for (i = 0; i < idxd->max_wqs; i++) {
182 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
190 device_initialize(&wq->conf_dev);
191 wq->conf_dev.parent = &idxd->conf_dev;
192 wq->conf_dev.bus = &dsa_bus_type;
193 wq->conf_dev.type = &idxd_wq_device_type;
194 rc = dev_set_name(&wq->conf_dev, "wq%d.%d", idxd->id, wq->id);
196 put_device(&wq->conf_dev);
200 mutex_init(&wq->wq_lock);
201 init_waitqueue_head(&wq->err_queue);
202 init_completion(&wq->wq_dead);
203 wq->max_xfer_bytes = idxd->max_xfer_bytes;
204 wq->max_batch_size = idxd->max_batch_size;
205 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
207 put_device(&wq->conf_dev);
218 put_device(&idxd->wqs[i]->conf_dev);
222 static int idxd_setup_engines(struct idxd_device *idxd)
224 struct idxd_engine *engine;
225 struct device *dev = &idxd->pdev->dev;
228 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
229 GFP_KERNEL, dev_to_node(dev));
233 for (i = 0; i < idxd->max_engines; i++) {
234 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
242 device_initialize(&engine->conf_dev);
243 engine->conf_dev.parent = &idxd->conf_dev;
244 engine->conf_dev.type = &idxd_engine_device_type;
245 rc = dev_set_name(&engine->conf_dev, "engine%d.%d", idxd->id, engine->id);
247 put_device(&engine->conf_dev);
251 idxd->engines[i] = engine;
258 put_device(&idxd->engines[i]->conf_dev);
262 static int idxd_setup_groups(struct idxd_device *idxd)
264 struct device *dev = &idxd->pdev->dev;
265 struct idxd_group *group;
268 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
269 GFP_KERNEL, dev_to_node(dev));
273 for (i = 0; i < idxd->max_groups; i++) {
274 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
282 device_initialize(&group->conf_dev);
283 group->conf_dev.parent = &idxd->conf_dev;
284 group->conf_dev.bus = &dsa_bus_type;
285 group->conf_dev.type = &idxd_group_device_type;
286 rc = dev_set_name(&group->conf_dev, "group%d.%d", idxd->id, group->id);
288 put_device(&group->conf_dev);
292 idxd->groups[i] = group;
301 put_device(&idxd->groups[i]->conf_dev);
305 static int idxd_setup_internals(struct idxd_device *idxd)
307 struct device *dev = &idxd->pdev->dev;
310 init_waitqueue_head(&idxd->cmd_waitq);
312 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
313 idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL);
314 if (!idxd->int_handles)
318 rc = idxd_setup_wqs(idxd);
322 rc = idxd_setup_engines(idxd);
326 rc = idxd_setup_groups(idxd);
330 idxd->wq = create_workqueue(dev_name(dev));
339 for (i = 0; i < idxd->max_groups; i++)
340 put_device(&idxd->groups[i]->conf_dev);
342 for (i = 0; i < idxd->max_engines; i++)
343 put_device(&idxd->engines[i]->conf_dev);
345 for (i = 0; i < idxd->max_wqs; i++)
346 put_device(&idxd->wqs[i]->conf_dev);
348 kfree(idxd->int_handles);
352 static void idxd_read_table_offsets(struct idxd_device *idxd)
354 union offsets_reg offsets;
355 struct device *dev = &idxd->pdev->dev;
357 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
358 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
359 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
360 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
361 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
362 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
363 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
364 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
365 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
366 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
369 static void idxd_read_caps(struct idxd_device *idxd)
371 struct device *dev = &idxd->pdev->dev;
374 /* reading generic capabilities */
375 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
376 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
378 if (idxd->hw.gen_cap.cmd_cap) {
379 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
380 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
383 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
384 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
385 idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
386 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
387 if (idxd->hw.gen_cap.config_en)
388 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
390 /* reading group capabilities */
391 idxd->hw.group_cap.bits =
392 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
393 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
394 idxd->max_groups = idxd->hw.group_cap.num_groups;
395 dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
396 idxd->max_tokens = idxd->hw.group_cap.total_tokens;
397 dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens);
398 idxd->nr_tokens = idxd->max_tokens;
400 /* read engine capabilities */
401 idxd->hw.engine_cap.bits =
402 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
403 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
404 idxd->max_engines = idxd->hw.engine_cap.num_engines;
405 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
407 /* read workqueue capabilities */
408 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
409 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
410 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
411 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
412 idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
413 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
414 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
415 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
417 /* reading operation capabilities */
418 for (i = 0; i < 4; i++) {
419 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
420 IDXD_OPCAP_OFFSET + i * sizeof(u64));
421 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
425 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
427 struct device *dev = &pdev->dev;
428 struct idxd_device *idxd;
431 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
437 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
441 device_initialize(&idxd->conf_dev);
442 idxd->conf_dev.parent = dev;
443 idxd->conf_dev.bus = &dsa_bus_type;
444 idxd->conf_dev.type = idxd->data->dev_type;
445 rc = dev_set_name(&idxd->conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
447 put_device(&idxd->conf_dev);
451 spin_lock_init(&idxd->dev_lock);
452 spin_lock_init(&idxd->cmd_lock);
457 static int idxd_enable_system_pasid(struct idxd_device *idxd)
461 struct iommu_sva *sva;
463 flags = SVM_FLAG_SUPERVISOR_MODE;
465 sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags);
467 dev_warn(&idxd->pdev->dev,
468 "iommu sva bind failed: %ld\n", PTR_ERR(sva));
472 pasid = iommu_sva_get_pasid(sva);
473 if (pasid == IOMMU_PASID_INVALID) {
474 iommu_sva_unbind_device(sva);
480 dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid);
484 static void idxd_disable_system_pasid(struct idxd_device *idxd)
487 iommu_sva_unbind_device(idxd->sva);
491 static int idxd_probe(struct idxd_device *idxd)
493 struct pci_dev *pdev = idxd->pdev;
494 struct device *dev = &pdev->dev;
497 dev_dbg(dev, "%s entered and resetting device\n", __func__);
498 rc = idxd_device_init_reset(idxd);
502 dev_dbg(dev, "IDXD reset complete\n");
504 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
505 rc = iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA);
507 rc = idxd_enable_system_pasid(idxd);
509 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
510 dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc);
512 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
515 dev_warn(dev, "Unable to turn on SVA feature.\n");
518 dev_warn(dev, "User forced SVA off via module param.\n");
521 idxd_read_caps(idxd);
522 idxd_read_table_offsets(idxd);
524 rc = idxd_setup_internals(idxd);
528 /* If the configs are readonly, then load them from device */
529 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
530 dev_dbg(dev, "Loading RO device config\n");
531 rc = idxd_device_load_config(idxd);
536 rc = idxd_setup_interrupts(idxd);
540 dev_dbg(dev, "IDXD interrupt setup complete.\n");
542 idxd->major = idxd_cdev_get_major(idxd);
544 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
548 if (device_pasid_enabled(idxd))
549 idxd_disable_system_pasid(idxd);
550 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
554 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
556 struct device *dev = &pdev->dev;
557 struct idxd_device *idxd;
558 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
561 rc = pci_enable_device(pdev);
565 dev_dbg(dev, "Alloc IDXD context\n");
566 idxd = idxd_alloc(pdev, data);
572 dev_dbg(dev, "Mapping BARs\n");
573 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
574 if (!idxd->reg_base) {
579 dev_dbg(dev, "Set DMA masks\n");
580 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
582 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
586 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
588 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
592 dev_dbg(dev, "Set PCI master\n");
593 pci_set_master(pdev);
594 pci_set_drvdata(pdev, idxd);
596 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
597 rc = idxd_probe(idxd);
599 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
603 rc = idxd_register_devices(idxd);
605 dev_err(dev, "IDXD sysfs setup failed\n");
609 idxd->state = IDXD_DEV_CONF_READY;
611 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
617 pci_iounmap(pdev, idxd->reg_base);
619 put_device(&idxd->conf_dev);
621 pci_disable_device(pdev);
625 static void idxd_flush_pending_llist(struct idxd_irq_entry *ie)
627 struct idxd_desc *desc, *itr;
628 struct llist_node *head;
630 head = llist_del_all(&ie->pending_llist);
634 llist_for_each_entry_safe(desc, itr, head, llnode) {
635 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
636 idxd_free_desc(desc->wq, desc);
640 static void idxd_flush_work_list(struct idxd_irq_entry *ie)
642 struct idxd_desc *desc, *iter;
644 list_for_each_entry_safe(desc, iter, &ie->work_list, list) {
645 list_del(&desc->list);
646 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
647 idxd_free_desc(desc->wq, desc);
651 void idxd_wqs_quiesce(struct idxd_device *idxd)
656 for (i = 0; i < idxd->max_wqs; i++) {
658 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
663 static void idxd_release_int_handles(struct idxd_device *idxd)
665 struct device *dev = &idxd->pdev->dev;
668 for (i = 0; i < idxd->num_wq_irqs; i++) {
669 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)) {
670 rc = idxd_device_release_int_handle(idxd, idxd->int_handles[i],
673 dev_warn(dev, "irq handle %d release failed\n",
674 idxd->int_handles[i]);
676 dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i]);
681 static void idxd_shutdown(struct pci_dev *pdev)
683 struct idxd_device *idxd = pci_get_drvdata(pdev);
685 struct idxd_irq_entry *irq_entry;
686 int msixcnt = pci_msix_vec_count(pdev);
688 rc = idxd_device_disable(idxd);
690 dev_err(&pdev->dev, "Disabling device failed\n");
692 dev_dbg(&pdev->dev, "%s called\n", __func__);
693 idxd_mask_msix_vectors(idxd);
694 idxd_mask_error_interrupts(idxd);
696 for (i = 0; i < msixcnt; i++) {
697 irq_entry = &idxd->irq_entries[i];
698 synchronize_irq(irq_entry->vector);
699 free_irq(irq_entry->vector, irq_entry);
702 idxd_flush_pending_llist(irq_entry);
703 idxd_flush_work_list(irq_entry);
706 idxd_msix_perm_clear(idxd);
707 idxd_release_int_handles(idxd);
708 pci_free_irq_vectors(pdev);
709 pci_iounmap(pdev, idxd->reg_base);
710 pci_disable_device(pdev);
711 destroy_workqueue(idxd->wq);
714 static void idxd_remove(struct pci_dev *pdev)
716 struct idxd_device *idxd = pci_get_drvdata(pdev);
718 dev_dbg(&pdev->dev, "%s called\n", __func__);
720 if (device_pasid_enabled(idxd))
721 idxd_disable_system_pasid(idxd);
722 idxd_unregister_devices(idxd);
723 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
726 static struct pci_driver idxd_pci_driver = {
728 .id_table = idxd_pci_tbl,
729 .probe = idxd_pci_probe,
730 .remove = idxd_remove,
731 .shutdown = idxd_shutdown,
734 static int __init idxd_init_module(void)
739 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
740 * enumerating the device. We can not utilize it.
742 if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) {
743 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
747 if (!boot_cpu_has(X86_FEATURE_ENQCMD))
748 pr_warn("Platform does not have ENQCMD(S) support.\n");
750 support_enqcmd = true;
752 err = idxd_register_bus_type();
756 err = idxd_register_driver();
758 goto err_idxd_driver_register;
760 err = idxd_cdev_register();
762 goto err_cdev_register;
764 err = pci_register_driver(&idxd_pci_driver);
766 goto err_pci_register;
773 idxd_unregister_driver();
774 err_idxd_driver_register:
775 idxd_unregister_bus_type();
778 module_init(idxd_init_module);
780 static void __exit idxd_exit_module(void)
782 pci_unregister_driver(&idxd_pci_driver);
784 idxd_unregister_bus_type();
786 module_exit(idxd_exit_module);