drivers/dma/idxd/init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #include <linux/init.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/slab.h>
   7 #include <linux/pci.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/workqueue.h>
  12 #include <linux/aer.h>
  13 #include <linux/fs.h>
  14 #include <linux/io-64-nonatomic-lo-hi.h>
  15 #include <linux/device.h>
  16 #include <linux/idr.h>
  17 #include <linux/intel-svm.h>
  18 #include <linux/iommu.h>
  19 #include <uapi/linux/idxd.h>
  20 #include <linux/dmaengine.h>
  21 #include "../dmaengine.h"
  22 #include "registers.h"
  23 #include "idxd.h"
  24
  25 MODULE_VERSION(IDXD_DRIVER_VERSION);
  26 MODULE_LICENSE("GPL v2");
  27 MODULE_AUTHOR("Intel Corporation");
  28
  29 static bool sva = true;
  30 module_param(sva, bool, 0644);
  31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
  32
  33 #define DRV_NAME "idxd"
  34
  35 bool support_enqcmd;
  36 DEFINE_IDA(idxd_ida);
  37
  38 static struct idxd_driver_data idxd_driver_data[] = {
  39         [IDXD_TYPE_DSA] = {
  40                 .name_prefix = "dsa",
  41                 .type = IDXD_TYPE_DSA,
  42                 .compl_size = sizeof(struct dsa_completion_record),
  43                 .align = 32,
  44                 .dev_type = &dsa_device_type,
  45         },
  46         [IDXD_TYPE_IAX] = {
  47                 .name_prefix = "iax",
  48                 .type = IDXD_TYPE_IAX,
  49                 .compl_size = sizeof(struct iax_completion_record),
  50                 .align = 64,
  51                 .dev_type = &iax_device_type,
  52         },
  53 };
  54
  55 static struct pci_device_id idxd_pci_tbl[] = {
  56         /* DSA ver 1.0 platforms */
  57         { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
  58
  59         /* IAX ver 1.0 platforms */
  60         { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
  61         { 0, }
  62 };
  63 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
  64
  65 static int idxd_setup_interrupts(struct idxd_device *idxd)
  66 {
  67         struct pci_dev *pdev = idxd->pdev;
  68         struct device *dev = &pdev->dev;
  69         struct idxd_irq_entry *irq_entry;
  70         int i, msixcnt;
  71         int rc = 0;
  72
  73         msixcnt = pci_msix_vec_count(pdev);
  74         if (msixcnt < 0) {
  75                 dev_err(dev, "Not MSI-X interrupt capable.\n");
  76                 return -ENOSPC;
  77         }
  78
  79         rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
  80         if (rc != msixcnt) {
  81                 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
  82                 return -ENOSPC;
  83         }
  84         dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
  85
  86         /*
  87          * We implement 1 completion list per MSI-X entry except for
  88          * entry 0, which is for errors and others.
  89          */
  90         idxd->irq_entries = kcalloc_node(msixcnt, sizeof(struct idxd_irq_entry),
  91                                          GFP_KERNEL, dev_to_node(dev));
  92         if (!idxd->irq_entries) {
  93                 rc = -ENOMEM;
  94                 goto err_irq_entries;
  95         }
  96
  97         for (i = 0; i < msixcnt; i++) {
  98                 idxd->irq_entries[i].id = i;
  99                 idxd->irq_entries[i].idxd = idxd;
 100                 idxd->irq_entries[i].vector = pci_irq_vector(pdev, i);
 101                 spin_lock_init(&idxd->irq_entries[i].list_lock);
 102         }
 103
 104         irq_entry = &idxd->irq_entries[0];
 105         rc = request_threaded_irq(irq_entry->vector, NULL, idxd_misc_thread,
 106                                   0, "idxd-misc", irq_entry);
 107         if (rc < 0) {
 108                 dev_err(dev, "Failed to allocate misc interrupt.\n");
 109                 goto err_misc_irq;
 110         }
 111
 112         dev_dbg(dev, "Allocated idxd-misc handler on msix vector %d\n", irq_entry->vector);
 113
 114         /* first MSI-X entry is not for wq interrupts */
 115         idxd->num_wq_irqs = msixcnt - 1;
 116
 117         for (i = 1; i < msixcnt; i++) {
 118                 irq_entry = &idxd->irq_entries[i];
 119
 120                 init_llist_head(&idxd->irq_entries[i].pending_llist);
 121                 INIT_LIST_HEAD(&idxd->irq_entries[i].work_list);
 122                 rc = request_threaded_irq(irq_entry->vector, NULL,
 123                                           idxd_wq_thread, 0, "idxd-portal", irq_entry);
 124                 if (rc < 0) {
 125                         dev_err(dev, "Failed to allocate irq %d.\n", irq_entry->vector);
 126                         goto err_wq_irqs;
 127                 }
 128
 129                 dev_dbg(dev, "Allocated idxd-msix %d for vector %d\n", i, irq_entry->vector);
 130                 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
 131                         /*
 132                          * The MSIX vector enumeration starts at 1 with vector 0 being the
 133                          * misc interrupt that handles non I/O completion events. The
 134                          * interrupt handles are for IMS enumeration on guest. The misc
 135                          * interrupt vector does not require a handle and therefore we start
 136                          * the int_handles at index 0. Since 'i' starts at 1, the first
 137                          * int_handles index will be 0.
 138                          */
 139                         rc = idxd_device_request_int_handle(idxd, i, &idxd->int_handles[i - 1],
 140                                                             IDXD_IRQ_MSIX);
 141                         if (rc < 0) {
 142                                 free_irq(irq_entry->vector, irq_entry);
 143                                 goto err_wq_irqs;
 144                         }
 145                         dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i - 1]);
 146                 }
 147         }
 148
 149         idxd_unmask_error_interrupts(idxd);
 150         idxd_msix_perm_setup(idxd);
 151         return 0;
 152
 153  err_wq_irqs:
 154         while (--i >= 0) {
 155                 irq_entry = &idxd->irq_entries[i];
 156                 free_irq(irq_entry->vector, irq_entry);
 157                 if (i != 0)
 158                         idxd_device_release_int_handle(idxd,
 159                                                        idxd->int_handles[i], IDXD_IRQ_MSIX);
 160         }
 161  err_misc_irq:
 162         /* Disable error interrupt generation */
 163         idxd_mask_error_interrupts(idxd);
 164  err_irq_entries:
 165         pci_free_irq_vectors(pdev);
 166         dev_err(dev, "No usable interrupts\n");
 167         return rc;
 168 }
 169
 170 static int idxd_setup_wqs(struct idxd_device *idxd)
 171 {
 172         struct device *dev = &idxd->pdev->dev;
 173         struct idxd_wq *wq;
 174         int i, rc;
 175
 176         idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
 177                                  GFP_KERNEL, dev_to_node(dev));
 178         if (!idxd->wqs)
 179                 return -ENOMEM;
 180
 181         for (i = 0; i < idxd->max_wqs; i++) {
 182                 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
 183                 if (!wq) {
 184                         rc = -ENOMEM;
 185                         goto err;
 186                 }
 187
 188                 wq->id = i;
 189                 wq->idxd = idxd;
 190                 device_initialize(&wq->conf_dev);
 191                 wq->conf_dev.parent = &idxd->conf_dev;
 192                 wq->conf_dev.bus = &dsa_bus_type;
 193                 wq->conf_dev.type = &idxd_wq_device_type;
 194                 rc = dev_set_name(&wq->conf_dev, "wq%d.%d", idxd->id, wq->id);
 195                 if (rc < 0) {
 196                         put_device(&wq->conf_dev);
 197                         goto err;
 198                 }
 199
 200                 mutex_init(&wq->wq_lock);
 201                 init_waitqueue_head(&wq->err_queue);
 202                 init_completion(&wq->wq_dead);
 203                 wq->max_xfer_bytes = idxd->max_xfer_bytes;
 204                 wq->max_batch_size = idxd->max_batch_size;
 205                 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
 206                 if (!wq->wqcfg) {
 207                         put_device(&wq->conf_dev);
 208                         rc = -ENOMEM;
 209                         goto err;
 210                 }
 211                 idxd->wqs[i] = wq;
 212         }
 213
 214         return 0;
 215
 216  err:
 217         while (--i >= 0)
 218                 put_device(&idxd->wqs[i]->conf_dev);
 219         return rc;
 220 }
 221
 222 static int idxd_setup_engines(struct idxd_device *idxd)
 223 {
 224         struct idxd_engine *engine;
 225         struct device *dev = &idxd->pdev->dev;
 226         int i, rc;
 227
 228         idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
 229                                      GFP_KERNEL, dev_to_node(dev));
 230         if (!idxd->engines)
 231                 return -ENOMEM;
 232
 233         for (i = 0; i < idxd->max_engines; i++) {
 234                 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
 235                 if (!engine) {
 236                         rc = -ENOMEM;
 237                         goto err;
 238                 }
 239
 240                 engine->id = i;
 241                 engine->idxd = idxd;
 242                 device_initialize(&engine->conf_dev);
 243                 engine->conf_dev.parent = &idxd->conf_dev;
 244                 engine->conf_dev.type = &idxd_engine_device_type;
 245                 rc = dev_set_name(&engine->conf_dev, "engine%d.%d", idxd->id, engine->id);
 246                 if (rc < 0) {
 247                         put_device(&engine->conf_dev);
 248                         goto err;
 249                 }
 250
 251                 idxd->engines[i] = engine;
 252         }
 253
 254         return 0;
 255
 256  err:
 257         while (--i >= 0)
 258                 put_device(&idxd->engines[i]->conf_dev);
 259         return rc;
 260 }
 261
 262 static int idxd_setup_groups(struct idxd_device *idxd)
 263 {
 264         struct device *dev = &idxd->pdev->dev;
 265         struct idxd_group *group;
 266         int i, rc;
 267
 268         idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
 269                                     GFP_KERNEL, dev_to_node(dev));
 270         if (!idxd->groups)
 271                 return -ENOMEM;
 272
 273         for (i = 0; i < idxd->max_groups; i++) {
 274                 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
 275                 if (!group) {
 276                         rc = -ENOMEM;
 277                         goto err;
 278                 }
 279
 280                 group->id = i;
 281                 group->idxd = idxd;
 282                 device_initialize(&group->conf_dev);
 283                 group->conf_dev.parent = &idxd->conf_dev;
 284                 group->conf_dev.bus = &dsa_bus_type;
 285                 group->conf_dev.type = &idxd_group_device_type;
 286                 rc = dev_set_name(&group->conf_dev, "group%d.%d", idxd->id, group->id);
 287                 if (rc < 0) {
 288                         put_device(&group->conf_dev);
 289                         goto err;
 290                 }
 291
 292                 idxd->groups[i] = group;
 293                 group->tc_a = -1;
 294                 group->tc_b = -1;
 295         }
 296
 297         return 0;
 298
 299  err:
 300         while (--i >= 0)
 301                 put_device(&idxd->groups[i]->conf_dev);
 302         return rc;
 303 }
 304
 305 static int idxd_setup_internals(struct idxd_device *idxd)
 306 {
 307         struct device *dev = &idxd->pdev->dev;
 308         int rc, i;
 309
 310         init_waitqueue_head(&idxd->cmd_waitq);
 311
 312         if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) {
 313                 idxd->int_handles = devm_kcalloc(dev, idxd->max_wqs, sizeof(int), GFP_KERNEL);
 314                 if (!idxd->int_handles)
 315                         return -ENOMEM;
 316         }
 317
 318         rc = idxd_setup_wqs(idxd);
 319         if (rc < 0)
 320                 goto err_wqs;
 321
 322         rc = idxd_setup_engines(idxd);
 323         if (rc < 0)
 324                 goto err_engine;
 325
 326         rc = idxd_setup_groups(idxd);
 327         if (rc < 0)
 328                 goto err_group;
 329
 330         idxd->wq = create_workqueue(dev_name(dev));
 331         if (!idxd->wq) {
 332                 rc = -ENOMEM;
 333                 goto err_wkq_create;
 334         }
 335
 336         return 0;
 337
 338  err_wkq_create:
 339         for (i = 0; i < idxd->max_groups; i++)
 340                 put_device(&idxd->groups[i]->conf_dev);
 341  err_group:
 342         for (i = 0; i < idxd->max_engines; i++)
 343                 put_device(&idxd->engines[i]->conf_dev);
 344  err_engine:
 345         for (i = 0; i < idxd->max_wqs; i++)
 346                 put_device(&idxd->wqs[i]->conf_dev);
 347  err_wqs:
 348         kfree(idxd->int_handles);
 349         return rc;
 350 }
 351
 352 static void idxd_read_table_offsets(struct idxd_device *idxd)
 353 {
 354         union offsets_reg offsets;
 355         struct device *dev = &idxd->pdev->dev;
 356
 357         offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
 358         offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
 359         idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
 360         dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
 361         idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
 362         dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
 363         idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
 364         dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
 365         idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
 366         dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
 367 }
 368
 369 static void idxd_read_caps(struct idxd_device *idxd)
 370 {
 371         struct device *dev = &idxd->pdev->dev;
 372         int i;
 373
 374         /* reading generic capabilities */
 375         idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
 376         dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
 377
 378         if (idxd->hw.gen_cap.cmd_cap) {
 379                 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
 380                 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
 381         }
 382
 383         idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
 384         dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
 385         idxd->max_batch_size = 1U << idxd->hw.gen_cap.max_batch_shift;
 386         dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
 387         if (idxd->hw.gen_cap.config_en)
 388                 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
 389
 390         /* reading group capabilities */
 391         idxd->hw.group_cap.bits =
 392                 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
 393         dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
 394         idxd->max_groups = idxd->hw.group_cap.num_groups;
 395         dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
 396         idxd->max_tokens = idxd->hw.group_cap.total_tokens;
 397         dev_dbg(dev, "max tokens: %u\n", idxd->max_tokens);
 398         idxd->nr_tokens = idxd->max_tokens;
 399
 400         /* read engine capabilities */
 401         idxd->hw.engine_cap.bits =
 402                 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
 403         dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
 404         idxd->max_engines = idxd->hw.engine_cap.num_engines;
 405         dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
 406
 407         /* read workqueue capabilities */
 408         idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
 409         dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
 410         idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
 411         dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
 412         idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
 413         dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
 414         idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
 415         dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
 416
 417         /* reading operation capabilities */
 418         for (i = 0; i < 4; i++) {
 419                 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
 420                                 IDXD_OPCAP_OFFSET + i * sizeof(u64));
 421                 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
 422         }
 423 }
 424
 425 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
 426 {
 427         struct device *dev = &pdev->dev;
 428         struct idxd_device *idxd;
 429         int rc;
 430
 431         idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
 432         if (!idxd)
 433                 return NULL;
 434
 435         idxd->pdev = pdev;
 436         idxd->data = data;
 437         idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
 438         if (idxd->id < 0)
 439                 return NULL;
 440
 441         device_initialize(&idxd->conf_dev);
 442         idxd->conf_dev.parent = dev;
 443         idxd->conf_dev.bus = &dsa_bus_type;
 444         idxd->conf_dev.type = idxd->data->dev_type;
 445         rc = dev_set_name(&idxd->conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
 446         if (rc < 0) {
 447                 put_device(&idxd->conf_dev);
 448                 return NULL;
 449         }
 450
 451         spin_lock_init(&idxd->dev_lock);
 452         spin_lock_init(&idxd->cmd_lock);
 453
 454         return idxd;
 455 }
 456
 457 static int idxd_enable_system_pasid(struct idxd_device *idxd)
 458 {
 459         int flags;
 460         unsigned int pasid;
 461         struct iommu_sva *sva;
 462
 463         flags = SVM_FLAG_SUPERVISOR_MODE;
 464
 465         sva = iommu_sva_bind_device(&idxd->pdev->dev, NULL, &flags);
 466         if (IS_ERR(sva)) {
 467                 dev_warn(&idxd->pdev->dev,
 468                          "iommu sva bind failed: %ld\n", PTR_ERR(sva));
 469                 return PTR_ERR(sva);
 470         }
 471
 472         pasid = iommu_sva_get_pasid(sva);
 473         if (pasid == IOMMU_PASID_INVALID) {
 474                 iommu_sva_unbind_device(sva);
 475                 return -ENODEV;
 476         }
 477
 478         idxd->sva = sva;
 479         idxd->pasid = pasid;
 480         dev_dbg(&idxd->pdev->dev, "system pasid: %u\n", pasid);
 481         return 0;
 482 }
 483
 484 static void idxd_disable_system_pasid(struct idxd_device *idxd)
 485 {
 486
 487         iommu_sva_unbind_device(idxd->sva);
 488         idxd->sva = NULL;
 489 }
 490
 491 static int idxd_probe(struct idxd_device *idxd)
 492 {
 493         struct pci_dev *pdev = idxd->pdev;
 494         struct device *dev = &pdev->dev;
 495         int rc;
 496
 497         dev_dbg(dev, "%s entered and resetting device\n", __func__);
 498         rc = idxd_device_init_reset(idxd);
 499         if (rc < 0)
 500                 return rc;
 501
 502         dev_dbg(dev, "IDXD reset complete\n");
 503
 504         if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
 505                 rc = iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA);
 506                 if (rc == 0) {
 507                         rc = idxd_enable_system_pasid(idxd);
 508                         if (rc < 0) {
 509                                 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
 510                                 dev_warn(dev, "Failed to enable PASID. No SVA support: %d\n", rc);
 511                         } else {
 512                                 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
 513                         }
 514                 } else {
 515                         dev_warn(dev, "Unable to turn on SVA feature.\n");
 516                 }
 517         } else if (!sva) {
 518                 dev_warn(dev, "User forced SVA off via module param.\n");
 519         }
 520
 521         idxd_read_caps(idxd);
 522         idxd_read_table_offsets(idxd);
 523
 524         rc = idxd_setup_internals(idxd);
 525         if (rc)
 526                 goto err;
 527
 528         /* If the configs are readonly, then load them from device */
 529         if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
 530                 dev_dbg(dev, "Loading RO device config\n");
 531                 rc = idxd_device_load_config(idxd);
 532                 if (rc < 0)
 533                         goto err;
 534         }
 535
 536         rc = idxd_setup_interrupts(idxd);
 537         if (rc)
 538                 goto err;
 539
 540         dev_dbg(dev, "IDXD interrupt setup complete.\n");
 541
 542         idxd->major = idxd_cdev_get_major(idxd);
 543
 544         dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
 545         return 0;
 546
 547  err:
 548         if (device_pasid_enabled(idxd))
 549                 idxd_disable_system_pasid(idxd);
 550         iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA);
 551         return rc;
 552 }
 553
 554 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 555 {
 556         struct device *dev = &pdev->dev;
 557         struct idxd_device *idxd;
 558         struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
 559         int rc;
 560
 561         rc = pci_enable_device(pdev);
 562         if (rc)
 563                 return rc;
 564
 565         dev_dbg(dev, "Alloc IDXD context\n");
 566         idxd = idxd_alloc(pdev, data);
 567         if (!idxd) {
 568                 rc = -ENOMEM;
 569                 goto err_idxd_alloc;
 570         }
 571
 572         dev_dbg(dev, "Mapping BARs\n");
 573         idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
 574         if (!idxd->reg_base) {
 575                 rc = -ENOMEM;
 576                 goto err_iomap;
 577         }
 578
 579         dev_dbg(dev, "Set DMA masks\n");
 580         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 581         if (rc)
 582                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 583         if (rc)
 584                 goto err;
 585
 586         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 587         if (rc)
 588                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 589         if (rc)
 590                 goto err;
 591
 592         dev_dbg(dev, "Set PCI master\n");
 593         pci_set_master(pdev);
 594         pci_set_drvdata(pdev, idxd);
 595
 596         idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
 597         rc = idxd_probe(idxd);
 598         if (rc) {
 599                 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
 600                 goto err;
 601         }
 602
 603         rc = idxd_register_devices(idxd);
 604         if (rc) {
 605                 dev_err(dev, "IDXD sysfs setup failed\n");
 606                 goto err;
 607         }
 608
 609         idxd->state = IDXD_DEV_CONF_READY;
 610
 611         dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
 612                  idxd->hw.version);
 613
 614         return 0;
 615
 616  err:
 617         pci_iounmap(pdev, idxd->reg_base);
 618  err_iomap:
 619         put_device(&idxd->conf_dev);
 620  err_idxd_alloc:
 621         pci_disable_device(pdev);
 622         return rc;
 623 }
 624
 625 static void idxd_flush_pending_llist(struct idxd_irq_entry *ie)
 626 {
 627         struct idxd_desc *desc, *itr;
 628         struct llist_node *head;
 629
 630         head = llist_del_all(&ie->pending_llist);
 631         if (!head)
 632                 return;
 633
 634         llist_for_each_entry_safe(desc, itr, head, llnode) {
 635                 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
 636                 idxd_free_desc(desc->wq, desc);
 637         }
 638 }
 639
 640 static void idxd_flush_work_list(struct idxd_irq_entry *ie)
 641 {
 642         struct idxd_desc *desc, *iter;
 643
 644         list_for_each_entry_safe(desc, iter, &ie->work_list, list) {
 645                 list_del(&desc->list);
 646                 idxd_dma_complete_txd(desc, IDXD_COMPLETE_ABORT);
 647                 idxd_free_desc(desc->wq, desc);
 648         }
 649 }
 650
 651 void idxd_wqs_quiesce(struct idxd_device *idxd)
 652 {
 653         struct idxd_wq *wq;
 654         int i;
 655
 656         for (i = 0; i < idxd->max_wqs; i++) {
 657                 wq = idxd->wqs[i];
 658                 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
 659                         idxd_wq_quiesce(wq);
 660         }
 661 }
 662
 663 static void idxd_release_int_handles(struct idxd_device *idxd)
 664 {
 665         struct device *dev = &idxd->pdev->dev;
 666         int i, rc;
 667
 668         for (i = 0; i < idxd->num_wq_irqs; i++) {
 669                 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)) {
 670                         rc = idxd_device_release_int_handle(idxd, idxd->int_handles[i],
 671                                                             IDXD_IRQ_MSIX);
 672                         if (rc < 0)
 673                                 dev_warn(dev, "irq handle %d release failed\n",
 674                                          idxd->int_handles[i]);
 675                         else
 676                                 dev_dbg(dev, "int handle requested: %u\n", idxd->int_handles[i]);
 677                 }
 678         }
 679 }
 680
 681 static void idxd_shutdown(struct pci_dev *pdev)
 682 {
 683         struct idxd_device *idxd = pci_get_drvdata(pdev);
 684         int rc, i;
 685         struct idxd_irq_entry *irq_entry;
 686         int msixcnt = pci_msix_vec_count(pdev);
 687
 688         rc = idxd_device_disable(idxd);
 689         if (rc)
 690                 dev_err(&pdev->dev, "Disabling device failed\n");
 691
 692         dev_dbg(&pdev->dev, "%s called\n", __func__);
 693         idxd_mask_msix_vectors(idxd);
 694         idxd_mask_error_interrupts(idxd);
 695
 696         for (i = 0; i < msixcnt; i++) {
 697                 irq_entry = &idxd->irq_entries[i];
 698                 synchronize_irq(irq_entry->vector);
 699                 free_irq(irq_entry->vector, irq_entry);
 700                 if (i == 0)
 701                         continue;
 702                 idxd_flush_pending_llist(irq_entry);
 703                 idxd_flush_work_list(irq_entry);
 704         }
 705
 706         idxd_msix_perm_clear(idxd);
 707         idxd_release_int_handles(idxd);
 708         pci_free_irq_vectors(pdev);
 709         pci_iounmap(pdev, idxd->reg_base);
 710         pci_disable_device(pdev);
 711         destroy_workqueue(idxd->wq);
 712 }
 713
 714 static void idxd_remove(struct pci_dev *pdev)
 715 {
 716         struct idxd_device *idxd = pci_get_drvdata(pdev);
 717
 718         dev_dbg(&pdev->dev, "%s called\n", __func__);
 719         idxd_shutdown(pdev);
 720         if (device_pasid_enabled(idxd))
 721                 idxd_disable_system_pasid(idxd);
 722         idxd_unregister_devices(idxd);
 723         iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
 724 }
 725
 726 static struct pci_driver idxd_pci_driver = {
 727         .name           = DRV_NAME,
 728         .id_table       = idxd_pci_tbl,
 729         .probe          = idxd_pci_probe,
 730         .remove         = idxd_remove,
 731         .shutdown       = idxd_shutdown,
 732 };
 733
 734 static int __init idxd_init_module(void)
 735 {
 736         int err;
 737
 738         /*
 739          * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
 740          * enumerating the device. We can not utilize it.
 741          */
 742         if (!boot_cpu_has(X86_FEATURE_MOVDIR64B)) {
 743                 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
 744                 return -ENODEV;
 745         }
 746
 747         if (!boot_cpu_has(X86_FEATURE_ENQCMD))
 748                 pr_warn("Platform does not have ENQCMD(S) support.\n");
 749         else
 750                 support_enqcmd = true;
 751
 752         err = idxd_register_bus_type();
 753         if (err < 0)
 754                 return err;
 755
 756         err = idxd_register_driver();
 757         if (err < 0)
 758                 goto err_idxd_driver_register;
 759
 760         err = idxd_cdev_register();
 761         if (err)
 762                 goto err_cdev_register;
 763
 764         err = pci_register_driver(&idxd_pci_driver);
 765         if (err)
 766                 goto err_pci_register;
 767
 768         return 0;
 769
 770 err_pci_register:
 771         idxd_cdev_remove();
 772 err_cdev_register:
 773         idxd_unregister_driver();
 774 err_idxd_driver_register:
 775         idxd_unregister_bus_type();
 776         return err;
 777 }
 778 module_init(idxd_init_module);
 779
 780 static void __exit idxd_exit_module(void)
 781 {
 782         pci_unregister_driver(&idxd_pci_driver);
 783         idxd_cdev_remove();
 784         idxd_unregister_bus_type();
 785 }
 786 module_exit(idxd_exit_module);