1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
7 #include <linux/device.h>
8 #include <linux/io-64-nonatomic-lo-hi.h>
9 #include <linux/dmaengine.h>
10 #include <uapi/linux/idxd.h>
11 #include "../dmaengine.h"
12 #include "registers.h"
15 static inline struct idxd_wq *to_idxd_wq(struct dma_chan *c)
17 struct idxd_dma_chan *idxd_chan;
19 idxd_chan = container_of(c, struct idxd_dma_chan, chan);
23 void idxd_dma_complete_txd(struct idxd_desc *desc,
24 enum idxd_complete_type comp_type)
26 struct dma_async_tx_descriptor *tx;
27 struct dmaengine_result res;
30 if (desc->completion->status == DSA_COMP_SUCCESS)
31 res.result = DMA_TRANS_NOERROR;
32 else if (desc->completion->status)
33 res.result = DMA_TRANS_WRITE_FAILED;
34 else if (comp_type == IDXD_COMPLETE_ABORT)
35 res.result = DMA_TRANS_ABORTED;
40 if (complete && tx->cookie) {
41 dma_cookie_complete(tx);
42 dma_descriptor_unmap(tx);
43 dmaengine_desc_get_callback_invoke(tx, &res);
45 tx->callback_result = NULL;
49 static void op_flag_setup(unsigned long flags, u32 *desc_flags)
51 *desc_flags = IDXD_OP_FLAG_CRAV | IDXD_OP_FLAG_RCR;
52 if (flags & DMA_PREP_INTERRUPT)
53 *desc_flags |= IDXD_OP_FLAG_RCI;
56 static inline void set_completion_address(struct idxd_desc *desc,
59 *compl_addr = desc->compl_dma;
62 static inline void idxd_prep_desc_common(struct idxd_wq *wq,
63 struct dsa_hw_desc *hw, char opcode,
64 u64 addr_f1, u64 addr_f2, u64 len,
69 hw->src_addr = addr_f1;
70 hw->dst_addr = addr_f2;
73 * For dedicated WQ, this field is ignored and HW will use the WQCFG.priv
74 * field instead. This field should be set to 1 for kernel descriptors.
77 hw->completion_addr = compl;
80 static struct dma_async_tx_descriptor *
81 idxd_dma_submit_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
82 dma_addr_t dma_src, size_t len, unsigned long flags)
84 struct idxd_wq *wq = to_idxd_wq(c);
86 struct idxd_device *idxd = wq->idxd;
87 struct idxd_desc *desc;
89 if (wq->state != IDXD_WQ_ENABLED)
92 if (len > idxd->max_xfer_bytes)
95 op_flag_setup(flags, &desc_flags);
96 desc = idxd_alloc_desc(wq, IDXD_OP_BLOCK);
100 idxd_prep_desc_common(wq, desc->hw, DSA_OPCODE_MEMMOVE,
101 dma_src, dma_dest, len, desc->compl_dma,
104 desc->txd.flags = flags;
109 static int idxd_dma_alloc_chan_resources(struct dma_chan *chan)
111 struct idxd_wq *wq = to_idxd_wq(chan);
112 struct device *dev = &wq->idxd->pdev->dev;
115 dev_dbg(dev, "%s: client_count: %d\n", __func__,
116 idxd_wq_refcount(wq));
120 static void idxd_dma_free_chan_resources(struct dma_chan *chan)
122 struct idxd_wq *wq = to_idxd_wq(chan);
123 struct device *dev = &wq->idxd->pdev->dev;
126 dev_dbg(dev, "%s: client_count: %d\n", __func__,
127 idxd_wq_refcount(wq));
130 static enum dma_status idxd_dma_tx_status(struct dma_chan *dma_chan,
132 struct dma_tx_state *txstate)
134 return DMA_OUT_OF_ORDER;
138 * issue_pending() does not need to do anything since tx_submit() does the job
141 static void idxd_dma_issue_pending(struct dma_chan *dma_chan)
145 static dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx)
147 struct dma_chan *c = tx->chan;
148 struct idxd_wq *wq = to_idxd_wq(c);
151 struct idxd_desc *desc = container_of(tx, struct idxd_desc, txd);
153 cookie = dma_cookie_assign(tx);
155 rc = idxd_submit_desc(wq, desc);
162 static void idxd_dma_release(struct dma_device *device)
164 struct idxd_dma_dev *idxd_dma = container_of(device, struct idxd_dma_dev, dma);
169 int idxd_register_dma_device(struct idxd_device *idxd)
171 struct idxd_dma_dev *idxd_dma;
172 struct dma_device *dma;
173 struct device *dev = &idxd->pdev->dev;
176 idxd_dma = kzalloc_node(sizeof(*idxd_dma), GFP_KERNEL, dev_to_node(dev));
180 dma = &idxd_dma->dma;
181 INIT_LIST_HEAD(&dma->channels);
184 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
185 dma_cap_set(DMA_COMPLETION_NO_ORDER, dma->cap_mask);
186 dma->device_release = idxd_dma_release;
188 if (idxd->hw.opcap.bits[0] & IDXD_OPCAP_MEMMOVE) {
189 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
190 dma->device_prep_dma_memcpy = idxd_dma_submit_memcpy;
193 dma->device_tx_status = idxd_dma_tx_status;
194 dma->device_issue_pending = idxd_dma_issue_pending;
195 dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources;
196 dma->device_free_chan_resources = idxd_dma_free_chan_resources;
198 rc = dma_async_device_register(dma);
204 idxd_dma->idxd = idxd;
206 * This pointer is protected by the refs taken by the dma_chan. It will remain valid
207 * as long as there are outstanding channels.
209 idxd->idxd_dma = idxd_dma;
213 void idxd_unregister_dma_device(struct idxd_device *idxd)
215 dma_async_device_unregister(&idxd->idxd_dma->dma);
218 int idxd_register_dma_channel(struct idxd_wq *wq)
220 struct idxd_device *idxd = wq->idxd;
221 struct dma_device *dma = &idxd->idxd_dma->dma;
222 struct device *dev = &idxd->pdev->dev;
223 struct idxd_dma_chan *idxd_chan;
224 struct dma_chan *chan;
227 idxd_chan = kzalloc_node(sizeof(*idxd_chan), GFP_KERNEL, dev_to_node(dev));
231 chan = &idxd_chan->chan;
233 list_add_tail(&chan->device_node, &dma->channels);
235 for (i = 0; i < wq->num_descs; i++) {
236 struct idxd_desc *desc = wq->descs[i];
238 dma_async_tx_descriptor_init(&desc->txd, chan);
239 desc->txd.tx_submit = idxd_dma_tx_submit;
242 rc = dma_async_device_channel_register(dma, chan);
248 wq->idxd_chan = idxd_chan;
250 get_device(wq_confdev(wq));
255 void idxd_unregister_dma_channel(struct idxd_wq *wq)
257 struct idxd_dma_chan *idxd_chan = wq->idxd_chan;
258 struct dma_chan *chan = &idxd_chan->chan;
259 struct idxd_dma_dev *idxd_dma = wq->idxd->idxd_dma;
261 dma_async_device_channel_unregister(&idxd_dma->dma, chan);
262 list_del(&chan->device_node);
263 kfree(wq->idxd_chan);
264 wq->idxd_chan = NULL;
265 put_device(wq_confdev(wq));
268 static int idxd_dmaengine_drv_probe(struct idxd_dev *idxd_dev)
270 struct device *dev = &idxd_dev->conf_dev;
271 struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);
272 struct idxd_device *idxd = wq->idxd;
275 if (idxd->state != IDXD_DEV_ENABLED)
278 mutex_lock(&wq->wq_lock);
279 wq->type = IDXD_WQT_KERNEL;
280 rc = __drv_enable_wq(wq);
282 dev_dbg(dev, "Enable wq %d failed: %d\n", wq->id, rc);
287 rc = idxd_wq_alloc_resources(wq);
289 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR;
290 dev_dbg(dev, "WQ resource alloc failed\n");
294 rc = idxd_wq_init_percpu_ref(wq);
296 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR;
297 dev_dbg(dev, "percpu_ref setup failed\n");
301 rc = idxd_register_dma_channel(wq);
303 idxd->cmd_status = IDXD_SCMD_DMA_CHAN_ERR;
304 dev_dbg(dev, "Failed to register dma channel\n");
308 idxd->cmd_status = 0;
309 mutex_unlock(&wq->wq_lock);
314 percpu_ref_exit(&wq->wq_active);
316 idxd_wq_free_resources(wq);
318 __drv_disable_wq(wq);
320 wq->type = IDXD_WQT_NONE;
321 mutex_unlock(&wq->wq_lock);
325 static void idxd_dmaengine_drv_remove(struct idxd_dev *idxd_dev)
327 struct idxd_wq *wq = idxd_dev_to_wq(idxd_dev);
329 mutex_lock(&wq->wq_lock);
331 idxd_unregister_dma_channel(wq);
332 idxd_wq_free_resources(wq);
333 __drv_disable_wq(wq);
334 percpu_ref_exit(&wq->wq_active);
335 mutex_unlock(&wq->wq_lock);
338 static enum idxd_dev_type dev_types[] = {
343 struct idxd_device_driver idxd_dmaengine_drv = {
344 .probe = idxd_dmaengine_drv_probe,
345 .remove = idxd_dmaengine_drv_remove,
349 EXPORT_SYMBOL_GPL(idxd_dmaengine_drv);