1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
7 #include <linux/io-64-nonatomic-lo-hi.h>
8 #include <linux/dmaengine.h>
10 #include <linux/msi.h>
11 #include <uapi/linux/idxd.h>
12 #include "../dmaengine.h"
14 #include "registers.h"
16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
21 /* Interrupt control bits */
22 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
24 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
26 pci_msi_mask_irq(data);
29 void idxd_mask_msix_vectors(struct idxd_device *idxd)
31 struct pci_dev *pdev = idxd->pdev;
32 int msixcnt = pci_msix_vec_count(pdev);
35 for (i = 0; i < msixcnt; i++)
36 idxd_mask_msix_vector(idxd, i);
39 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
41 struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
43 pci_msi_unmask_irq(data);
46 void idxd_unmask_error_interrupts(struct idxd_device *idxd)
48 union genctrl_reg genctrl;
50 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
51 genctrl.softerr_int_en = 1;
52 genctrl.halt_int_en = 1;
53 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
56 void idxd_mask_error_interrupts(struct idxd_device *idxd)
58 union genctrl_reg genctrl;
60 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
61 genctrl.softerr_int_en = 0;
62 genctrl.halt_int_en = 0;
63 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
66 static void free_hw_descs(struct idxd_wq *wq)
70 for (i = 0; i < wq->num_descs; i++)
71 kfree(wq->hw_descs[i]);
76 static int alloc_hw_descs(struct idxd_wq *wq, int num)
78 struct device *dev = &wq->idxd->pdev->dev;
80 int node = dev_to_node(dev);
82 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
87 for (i = 0; i < num; i++) {
88 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
90 if (!wq->hw_descs[i]) {
99 static void free_descs(struct idxd_wq *wq)
103 for (i = 0; i < wq->num_descs; i++)
109 static int alloc_descs(struct idxd_wq *wq, int num)
111 struct device *dev = &wq->idxd->pdev->dev;
113 int node = dev_to_node(dev);
115 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
120 for (i = 0; i < num; i++) {
121 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
132 /* WQ control bits */
133 int idxd_wq_alloc_resources(struct idxd_wq *wq)
135 struct idxd_device *idxd = wq->idxd;
136 struct device *dev = &idxd->pdev->dev;
137 int rc, num_descs, i;
141 if (wq->type != IDXD_WQT_KERNEL)
144 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
145 wq->num_descs = num_descs;
147 rc = alloc_hw_descs(wq, num_descs);
151 align = idxd->data->align;
152 wq->compls_size = num_descs * idxd->data->compl_size + align;
153 wq->compls_raw = dma_alloc_coherent(dev, wq->compls_size,
154 &wq->compls_addr_raw, GFP_KERNEL);
155 if (!wq->compls_raw) {
157 goto fail_alloc_compls;
160 /* Adjust alignment */
161 wq->compls_addr = (wq->compls_addr_raw + (align - 1)) & ~(align - 1);
162 tmp = (u64)wq->compls_raw;
163 tmp = (tmp + (align - 1)) & ~(align - 1);
164 wq->compls = (struct dsa_completion_record *)tmp;
166 rc = alloc_descs(wq, num_descs);
168 goto fail_alloc_descs;
170 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
173 goto fail_sbitmap_init;
175 for (i = 0; i < num_descs; i++) {
176 struct idxd_desc *desc = wq->descs[i];
178 desc->hw = wq->hw_descs[i];
179 if (idxd->data->type == IDXD_TYPE_DSA)
180 desc->completion = &wq->compls[i];
181 else if (idxd->data->type == IDXD_TYPE_IAX)
182 desc->iax_completion = &wq->iax_compls[i];
183 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
194 dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
195 wq->compls_addr_raw);
201 void idxd_wq_free_resources(struct idxd_wq *wq)
203 struct device *dev = &wq->idxd->pdev->dev;
205 if (wq->type != IDXD_WQT_KERNEL)
210 dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
211 wq->compls_addr_raw);
212 sbitmap_queue_free(&wq->sbq);
215 int idxd_wq_enable(struct idxd_wq *wq)
217 struct idxd_device *idxd = wq->idxd;
218 struct device *dev = &idxd->pdev->dev;
221 if (wq->state == IDXD_WQ_ENABLED) {
222 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
226 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
228 if (status != IDXD_CMDSTS_SUCCESS &&
229 status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
230 dev_dbg(dev, "WQ enable failed: %#x\n", status);
234 wq->state = IDXD_WQ_ENABLED;
235 dev_dbg(dev, "WQ %d enabled\n", wq->id);
239 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
241 struct idxd_device *idxd = wq->idxd;
242 struct device *dev = &idxd->pdev->dev;
245 dev_dbg(dev, "Disabling WQ %d\n", wq->id);
247 if (wq->state != IDXD_WQ_ENABLED) {
248 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
252 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
253 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
255 if (status != IDXD_CMDSTS_SUCCESS) {
256 dev_dbg(dev, "WQ disable failed: %#x\n", status);
261 idxd_wq_disable_cleanup(wq);
262 wq->state = IDXD_WQ_DISABLED;
263 dev_dbg(dev, "WQ %d disabled\n", wq->id);
267 void idxd_wq_drain(struct idxd_wq *wq)
269 struct idxd_device *idxd = wq->idxd;
270 struct device *dev = &idxd->pdev->dev;
273 if (wq->state != IDXD_WQ_ENABLED) {
274 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
278 dev_dbg(dev, "Draining WQ %d\n", wq->id);
279 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
280 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
283 void idxd_wq_reset(struct idxd_wq *wq)
285 struct idxd_device *idxd = wq->idxd;
286 struct device *dev = &idxd->pdev->dev;
289 if (wq->state != IDXD_WQ_ENABLED) {
290 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
294 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
295 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
296 idxd_wq_disable_cleanup(wq);
297 wq->state = IDXD_WQ_DISABLED;
300 int idxd_wq_map_portal(struct idxd_wq *wq)
302 struct idxd_device *idxd = wq->idxd;
303 struct pci_dev *pdev = idxd->pdev;
304 struct device *dev = &pdev->dev;
305 resource_size_t start;
307 start = pci_resource_start(pdev, IDXD_WQ_BAR);
308 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
310 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
317 void idxd_wq_unmap_portal(struct idxd_wq *wq)
319 struct device *dev = &wq->idxd->pdev->dev;
321 devm_iounmap(dev, wq->portal);
323 wq->portal_offset = 0;
326 void idxd_wqs_unmap_portal(struct idxd_device *idxd)
330 for (i = 0; i < idxd->max_wqs; i++) {
331 struct idxd_wq *wq = idxd->wqs[i];
334 idxd_wq_unmap_portal(wq);
338 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
340 struct idxd_device *idxd = wq->idxd;
345 rc = idxd_wq_disable(wq, false);
349 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
350 spin_lock(&idxd->dev_lock);
351 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
354 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
355 spin_unlock(&idxd->dev_lock);
357 rc = idxd_wq_enable(wq);
364 int idxd_wq_disable_pasid(struct idxd_wq *wq)
366 struct idxd_device *idxd = wq->idxd;
371 rc = idxd_wq_disable(wq, false);
375 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
376 spin_lock(&idxd->dev_lock);
377 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
380 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
381 spin_unlock(&idxd->dev_lock);
383 rc = idxd_wq_enable(wq);
390 static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
392 struct idxd_device *idxd = wq->idxd;
394 lockdep_assert_held(&wq->wq_lock);
395 memset(wq->wqcfg, 0, idxd->wqcfg_size);
396 wq->type = IDXD_WQT_NONE;
402 clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
403 clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
404 memset(wq->name, 0, WQ_NAME_SIZE);
407 static void idxd_wq_ref_release(struct percpu_ref *ref)
409 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
411 complete(&wq->wq_dead);
414 int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
418 memset(&wq->wq_active, 0, sizeof(wq->wq_active));
419 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 0, GFP_KERNEL);
422 reinit_completion(&wq->wq_dead);
426 void idxd_wq_quiesce(struct idxd_wq *wq)
428 percpu_ref_kill(&wq->wq_active);
429 wait_for_completion(&wq->wq_dead);
430 percpu_ref_exit(&wq->wq_active);
433 /* Device control bits */
434 static inline bool idxd_is_enabled(struct idxd_device *idxd)
436 union gensts_reg gensts;
438 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
440 if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
445 static inline bool idxd_device_is_halted(struct idxd_device *idxd)
447 union gensts_reg gensts;
449 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
451 return (gensts.state == IDXD_DEVICE_STATE_HALT);
455 * This is function is only used for reset during probe and will
456 * poll for completion. Once the device is setup with interrupts,
457 * all commands will be done via interrupt completion.
459 int idxd_device_init_reset(struct idxd_device *idxd)
461 struct device *dev = &idxd->pdev->dev;
462 union idxd_command_reg cmd;
464 if (idxd_device_is_halted(idxd)) {
465 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
469 memset(&cmd, 0, sizeof(cmd));
470 cmd.cmd = IDXD_CMD_RESET_DEVICE;
471 dev_dbg(dev, "%s: sending reset for init.\n", __func__);
472 spin_lock(&idxd->cmd_lock);
473 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
475 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
478 spin_unlock(&idxd->cmd_lock);
482 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
485 union idxd_command_reg cmd;
486 DECLARE_COMPLETION_ONSTACK(done);
489 if (idxd_device_is_halted(idxd)) {
490 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
492 *status = IDXD_CMDSTS_HW_ERR;
496 memset(&cmd, 0, sizeof(cmd));
498 cmd.operand = operand;
501 spin_lock(&idxd->cmd_lock);
502 wait_event_lock_irq(idxd->cmd_waitq,
503 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
506 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
507 __func__, cmd_code, operand);
509 idxd->cmd_status = 0;
510 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
511 idxd->cmd_done = &done;
512 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
515 * After command submitted, release lock and go to sleep until
516 * the command completes via interrupt.
518 spin_unlock(&idxd->cmd_lock);
519 wait_for_completion(&done);
520 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
521 spin_lock(&idxd->cmd_lock);
524 idxd->cmd_status = stat & GENMASK(7, 0);
526 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
527 /* Wake up other pending commands */
528 wake_up(&idxd->cmd_waitq);
529 spin_unlock(&idxd->cmd_lock);
532 int idxd_device_enable(struct idxd_device *idxd)
534 struct device *dev = &idxd->pdev->dev;
537 if (idxd_is_enabled(idxd)) {
538 dev_dbg(dev, "Device already enabled\n");
542 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
544 /* If the command is successful or if the device was enabled */
545 if (status != IDXD_CMDSTS_SUCCESS &&
546 status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
547 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
551 idxd->state = IDXD_DEV_ENABLED;
555 int idxd_device_disable(struct idxd_device *idxd)
557 struct device *dev = &idxd->pdev->dev;
560 if (!idxd_is_enabled(idxd)) {
561 dev_dbg(dev, "Device is not enabled\n");
565 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
567 /* If the command is successful or if the device was disabled */
568 if (status != IDXD_CMDSTS_SUCCESS &&
569 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
570 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
574 spin_lock(&idxd->dev_lock);
575 idxd_device_clear_state(idxd);
576 idxd->state = IDXD_DEV_DISABLED;
577 spin_unlock(&idxd->dev_lock);
581 void idxd_device_reset(struct idxd_device *idxd)
583 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
584 spin_lock(&idxd->dev_lock);
585 idxd_device_clear_state(idxd);
586 idxd->state = IDXD_DEV_DISABLED;
587 spin_unlock(&idxd->dev_lock);
590 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
592 struct device *dev = &idxd->pdev->dev;
596 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
597 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
598 dev_dbg(dev, "pasid %d drained\n", pasid);
601 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
602 enum idxd_interrupt_type irq_type)
604 struct device *dev = &idxd->pdev->dev;
607 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
610 dev_dbg(dev, "get int handle, idx %d\n", idx);
612 operand = idx & GENMASK(15, 0);
613 if (irq_type == IDXD_IRQ_IMS)
614 operand |= CMD_INT_HANDLE_IMS;
616 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
618 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
620 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
621 dev_dbg(dev, "request int handle failed: %#x\n", status);
625 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
627 dev_dbg(dev, "int handle acquired: %u\n", *handle);
631 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
632 enum idxd_interrupt_type irq_type)
634 struct device *dev = &idxd->pdev->dev;
636 union idxd_command_reg cmd;
638 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
641 dev_dbg(dev, "release int handle, handle %d\n", handle);
643 memset(&cmd, 0, sizeof(cmd));
644 operand = handle & GENMASK(15, 0);
646 if (irq_type == IDXD_IRQ_IMS)
647 operand |= CMD_INT_HANDLE_IMS;
649 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
650 cmd.operand = operand;
652 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
654 spin_lock(&idxd->cmd_lock);
655 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
657 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
659 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
660 spin_unlock(&idxd->cmd_lock);
662 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
663 dev_dbg(dev, "release int handle failed: %#x\n", status);
667 dev_dbg(dev, "int handle released.\n");
671 /* Device configuration bits */
672 static void idxd_engines_clear_state(struct idxd_device *idxd)
674 struct idxd_engine *engine;
677 lockdep_assert_held(&idxd->dev_lock);
678 for (i = 0; i < idxd->max_engines; i++) {
679 engine = idxd->engines[i];
680 engine->group = NULL;
684 static void idxd_groups_clear_state(struct idxd_device *idxd)
686 struct idxd_group *group;
689 lockdep_assert_held(&idxd->dev_lock);
690 for (i = 0; i < idxd->max_groups; i++) {
691 group = idxd->groups[i];
692 memset(&group->grpcfg, 0, sizeof(group->grpcfg));
693 group->num_engines = 0;
695 group->use_token_limit = false;
696 group->tokens_allowed = 0;
697 group->tokens_reserved = 0;
703 static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
707 lockdep_assert_held(&idxd->dev_lock);
708 for (i = 0; i < idxd->max_wqs; i++) {
709 struct idxd_wq *wq = idxd->wqs[i];
711 if (wq->state == IDXD_WQ_ENABLED) {
712 idxd_wq_disable_cleanup(wq);
713 wq->state = IDXD_WQ_DISABLED;
718 void idxd_device_clear_state(struct idxd_device *idxd)
720 idxd_groups_clear_state(idxd);
721 idxd_engines_clear_state(idxd);
722 idxd_device_wqs_clear_state(idxd);
725 void idxd_msix_perm_setup(struct idxd_device *idxd)
727 union msix_perm mperm;
730 msixcnt = pci_msix_vec_count(idxd->pdev);
735 mperm.pasid = idxd->pasid;
736 mperm.pasid_en = device_pasid_enabled(idxd);
737 for (i = 1; i < msixcnt; i++)
738 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
741 void idxd_msix_perm_clear(struct idxd_device *idxd)
743 union msix_perm mperm;
746 msixcnt = pci_msix_vec_count(idxd->pdev);
751 for (i = 1; i < msixcnt; i++)
752 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
755 static void idxd_group_config_write(struct idxd_group *group)
757 struct idxd_device *idxd = group->idxd;
758 struct device *dev = &idxd->pdev->dev;
762 dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
765 for (i = 0; i < GRPWQCFG_STRIDES; i++) {
766 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
767 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
768 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
769 group->id, i, grpcfg_offset,
770 ioread64(idxd->reg_base + grpcfg_offset));
773 /* setup GRPENGCFG */
774 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
775 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
776 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
777 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
780 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
781 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
782 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
783 group->id, grpcfg_offset,
784 ioread32(idxd->reg_base + grpcfg_offset));
787 static int idxd_groups_config_write(struct idxd_device *idxd)
790 union gencfg_reg reg;
792 struct device *dev = &idxd->pdev->dev;
794 /* Setup bandwidth token limit */
795 if (idxd->token_limit) {
796 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
797 reg.token_limit = idxd->token_limit;
798 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
801 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
802 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
804 for (i = 0; i < idxd->max_groups; i++) {
805 struct idxd_group *group = idxd->groups[i];
807 idxd_group_config_write(group);
813 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
815 struct pci_dev *pdev = idxd->pdev;
817 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
822 static int idxd_wq_config_write(struct idxd_wq *wq)
824 struct idxd_device *idxd = wq->idxd;
825 struct device *dev = &idxd->pdev->dev;
833 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
834 * wq reset. This will copy back the sticky values that are present on some devices.
836 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
837 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
838 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset);
842 wq->wqcfg->wq_size = wq->size;
845 idxd->cmd_status = IDXD_SCMD_WQ_NO_SIZE;
846 dev_warn(dev, "Incorrect work queue size: 0\n");
851 wq->wqcfg->wq_thresh = wq->threshold;
854 if (wq_dedicated(wq))
857 if (device_pasid_enabled(idxd)) {
858 wq->wqcfg->pasid_en = 1;
859 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq))
860 wq->wqcfg->pasid = idxd->pasid;
864 * Here the priv bit is set depending on the WQ type. priv = 1 if the
865 * WQ type is kernel to indicate privileged access. This setting only
866 * matters for dedicated WQ. According to the DSA spec:
867 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
868 * Privileged Mode Enable field of the PCI Express PASID capability
869 * is 0, this field must be 0.
871 * In the case of a dedicated kernel WQ that is not able to support
872 * the PASID cap, then the configuration will be rejected.
874 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL);
875 if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
876 !idxd_device_pasid_priv_enabled(idxd) &&
877 wq->type == IDXD_WQT_KERNEL) {
878 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
882 wq->wqcfg->priority = wq->priority;
884 if (idxd->hw.gen_cap.block_on_fault &&
885 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags))
888 if (idxd->hw.wq_cap.wq_ats_support)
889 wq->wqcfg->wq_ats_disable = wq->ats_dis;
892 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
893 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
895 dev_dbg(dev, "WQ %d CFGs\n", wq->id);
896 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
897 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
898 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
899 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
900 wq->id, i, wq_offset,
901 ioread32(idxd->reg_base + wq_offset));
907 static int idxd_wqs_config_write(struct idxd_device *idxd)
911 for (i = 0; i < idxd->max_wqs; i++) {
912 struct idxd_wq *wq = idxd->wqs[i];
914 rc = idxd_wq_config_write(wq);
922 static void idxd_group_flags_setup(struct idxd_device *idxd)
926 /* TC-A 0 and TC-B 1 should be defaults */
927 for (i = 0; i < idxd->max_groups; i++) {
928 struct idxd_group *group = idxd->groups[i];
930 if (group->tc_a == -1)
931 group->tc_a = group->grpcfg.flags.tc_a = 0;
933 group->grpcfg.flags.tc_a = group->tc_a;
934 if (group->tc_b == -1)
935 group->tc_b = group->grpcfg.flags.tc_b = 1;
937 group->grpcfg.flags.tc_b = group->tc_b;
938 group->grpcfg.flags.use_token_limit = group->use_token_limit;
939 group->grpcfg.flags.tokens_reserved = group->tokens_reserved;
940 if (group->tokens_allowed)
941 group->grpcfg.flags.tokens_allowed =
942 group->tokens_allowed;
944 group->grpcfg.flags.tokens_allowed = idxd->max_tokens;
948 static int idxd_engines_setup(struct idxd_device *idxd)
951 struct idxd_engine *eng;
952 struct idxd_group *group;
954 for (i = 0; i < idxd->max_groups; i++) {
955 group = idxd->groups[i];
956 group->grpcfg.engines = 0;
959 for (i = 0; i < idxd->max_engines; i++) {
960 eng = idxd->engines[i];
966 group->grpcfg.engines |= BIT(eng->id);
976 static int idxd_wqs_setup(struct idxd_device *idxd)
979 struct idxd_group *group;
980 int i, j, configured = 0;
981 struct device *dev = &idxd->pdev->dev;
983 for (i = 0; i < idxd->max_groups; i++) {
984 group = idxd->groups[i];
985 for (j = 0; j < 4; j++)
986 group->grpcfg.wqs[j] = 0;
989 for (i = 0; i < idxd->max_wqs; i++) {
998 if (wq_shared(wq) && !device_swq_supported(idxd)) {
999 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
1000 dev_warn(dev, "No shared wq support but configured.\n");
1004 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
1008 if (configured == 0) {
1009 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
1016 int idxd_device_config(struct idxd_device *idxd)
1020 lockdep_assert_held(&idxd->dev_lock);
1021 rc = idxd_wqs_setup(idxd);
1025 rc = idxd_engines_setup(idxd);
1029 idxd_group_flags_setup(idxd);
1031 rc = idxd_wqs_config_write(idxd);
1035 rc = idxd_groups_config_write(idxd);
1042 static int idxd_wq_load_config(struct idxd_wq *wq)
1044 struct idxd_device *idxd = wq->idxd;
1045 struct device *dev = &idxd->pdev->dev;
1049 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1050 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1052 wq->size = wq->wqcfg->wq_size;
1053 wq->threshold = wq->wqcfg->wq_thresh;
1054 if (wq->wqcfg->priv)
1055 wq->type = IDXD_WQT_KERNEL;
1057 /* The driver does not support shared WQ mode in read-only config yet */
1058 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1061 set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1063 wq->priority = wq->wqcfg->priority;
1065 for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1066 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1067 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1073 static void idxd_group_load_config(struct idxd_group *group)
1075 struct idxd_device *idxd = group->idxd;
1076 struct device *dev = &idxd->pdev->dev;
1077 int i, j, grpcfg_offset;
1080 * Load WQS bit fields
1081 * Iterate through all 256 bits 64 bits at a time
1083 for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1086 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1087 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1088 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1089 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1091 if (i * 64 >= idxd->max_wqs)
1094 /* Iterate through all 64 bits and check for wq set */
1095 for (j = 0; j < 64; j++) {
1096 int id = i * 64 + j;
1098 /* No need to check beyond max wqs */
1099 if (id >= idxd->max_wqs)
1102 /* Set group assignment for wq if wq bit is set */
1103 if (group->grpcfg.wqs[i] & BIT(j)) {
1110 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1111 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1112 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1113 grpcfg_offset, group->grpcfg.engines);
1115 /* Iterate through all 64 bits to check engines set */
1116 for (i = 0; i < 64; i++) {
1117 if (i >= idxd->max_engines)
1120 if (group->grpcfg.engines & BIT(i)) {
1121 struct idxd_engine *engine = idxd->engines[i];
1123 engine->group = group;
1127 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1128 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset);
1129 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
1130 group->id, grpcfg_offset, group->grpcfg.flags.bits);
1133 int idxd_device_load_config(struct idxd_device *idxd)
1135 union gencfg_reg reg;
1138 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
1139 idxd->token_limit = reg.token_limit;
1141 for (i = 0; i < idxd->max_groups; i++) {
1142 struct idxd_group *group = idxd->groups[i];
1144 idxd_group_load_config(group);
1147 for (i = 0; i < idxd->max_wqs; i++) {
1148 struct idxd_wq *wq = idxd->wqs[i];
1150 rc = idxd_wq_load_config(wq);
1158 int __drv_enable_wq(struct idxd_wq *wq)
1160 struct idxd_device *idxd = wq->idxd;
1161 struct device *dev = &idxd->pdev->dev;
1164 lockdep_assert_held(&wq->wq_lock);
1166 if (idxd->state != IDXD_DEV_ENABLED) {
1167 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
1171 if (wq->state != IDXD_WQ_DISABLED) {
1172 dev_dbg(dev, "wq %d already enabled.\n", wq->id);
1173 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
1179 dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
1180 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
1184 if (strlen(wq->name) == 0) {
1185 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
1186 dev_dbg(dev, "wq %d name not set.\n", wq->id);
1190 /* Shared WQ checks */
1191 if (wq_shared(wq)) {
1192 if (!device_swq_supported(idxd)) {
1193 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
1194 dev_dbg(dev, "PASID not enabled and shared wq.\n");
1198 * Shared wq with the threshold set to 0 means the user
1199 * did not set the threshold or transitioned from a
1200 * dedicated wq but did not set threshold. A value
1201 * of 0 would effectively disable the shared wq. The
1202 * driver does not allow a value of 0 to be set for
1203 * threshold via sysfs.
1205 if (wq->threshold == 0) {
1206 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
1207 dev_dbg(dev, "Shared wq and threshold 0.\n");
1213 spin_lock(&idxd->dev_lock);
1214 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1215 rc = idxd_device_config(idxd);
1216 spin_unlock(&idxd->dev_lock);
1218 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1222 rc = idxd_wq_enable(wq);
1224 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1228 rc = idxd_wq_map_portal(wq);
1230 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
1231 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1232 goto err_map_portal;
1235 wq->client_count = 0;
1239 rc = idxd_wq_disable(wq, false);
1241 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1246 int drv_enable_wq(struct idxd_wq *wq)
1250 mutex_lock(&wq->wq_lock);
1251 rc = __drv_enable_wq(wq);
1252 mutex_unlock(&wq->wq_lock);
1256 void __drv_disable_wq(struct idxd_wq *wq)
1258 struct idxd_device *idxd = wq->idxd;
1259 struct device *dev = &idxd->pdev->dev;
1261 lockdep_assert_held(&wq->wq_lock);
1263 if (idxd_wq_refcount(wq))
1264 dev_warn(dev, "Clients has claim on wq %d: %d\n",
1265 wq->id, idxd_wq_refcount(wq));
1267 idxd_wq_unmap_portal(wq);
1272 wq->client_count = 0;
1275 void drv_disable_wq(struct idxd_wq *wq)
1277 mutex_lock(&wq->wq_lock);
1278 __drv_disable_wq(wq);
1279 mutex_unlock(&wq->wq_lock);
1282 int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1284 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1288 * Device should be in disabled state for the idxd_drv to load. If it's in
1289 * enabled state, then the device was altered outside of driver's control.
1290 * If the state is in halted state, then we don't want to proceed.
1292 if (idxd->state != IDXD_DEV_DISABLED) {
1293 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
1297 /* Device configuration */
1298 spin_lock(&idxd->dev_lock);
1299 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1300 rc = idxd_device_config(idxd);
1301 spin_unlock(&idxd->dev_lock);
1306 rc = idxd_device_enable(idxd);
1310 /* Setup DMA device without channels */
1311 rc = idxd_register_dma_device(idxd);
1313 idxd_device_disable(idxd);
1314 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
1318 idxd->cmd_status = 0;
1322 void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1324 struct device *dev = &idxd_dev->conf_dev;
1325 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1328 for (i = 0; i < idxd->max_wqs; i++) {
1329 struct idxd_wq *wq = idxd->wqs[i];
1330 struct device *wq_dev = wq_confdev(wq);
1332 if (wq->state == IDXD_WQ_DISABLED)
1334 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1335 device_release_driver(wq_dev);
1338 idxd_unregister_dma_device(idxd);
1339 idxd_device_disable(idxd);
1340 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1341 idxd_device_reset(idxd);
1344 static enum idxd_dev_type dev_types[] = {
1350 struct idxd_device_driver idxd_drv = {
1352 .probe = idxd_device_drv_probe,
1353 .remove = idxd_device_drv_remove,
1356 EXPORT_SYMBOL_GPL(idxd_drv);