drivers/dma/idxd/device.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #include <linux/init.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/io-64-nonatomic-lo-hi.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/irq.h>
  10 #include <linux/msi.h>
  11 #include <uapi/linux/idxd.h>
  12 #include "../dmaengine.h"
  13 #include "idxd.h"
  14 #include "registers.h"
  15
  16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
  17                           u32 *status);
  18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
  19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
  20
  21 /* Interrupt control bits */
  22 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id)
  23 {
  24         struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
  25
  26         pci_msi_mask_irq(data);
  27 }
  28
  29 void idxd_mask_msix_vectors(struct idxd_device *idxd)
  30 {
  31         struct pci_dev *pdev = idxd->pdev;
  32         int msixcnt = pci_msix_vec_count(pdev);
  33         int i;
  34
  35         for (i = 0; i < msixcnt; i++)
  36                 idxd_mask_msix_vector(idxd, i);
  37 }
  38
  39 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id)
  40 {
  41         struct irq_data *data = irq_get_irq_data(idxd->irq_entries[vec_id].vector);
  42
  43         pci_msi_unmask_irq(data);
  44 }
  45
  46 void idxd_unmask_error_interrupts(struct idxd_device *idxd)
  47 {
  48         union genctrl_reg genctrl;
  49
  50         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  51         genctrl.softerr_int_en = 1;
  52         genctrl.halt_int_en = 1;
  53         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  54 }
  55
  56 void idxd_mask_error_interrupts(struct idxd_device *idxd)
  57 {
  58         union genctrl_reg genctrl;
  59
  60         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  61         genctrl.softerr_int_en = 0;
  62         genctrl.halt_int_en = 0;
  63         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  64 }
  65
  66 static void free_hw_descs(struct idxd_wq *wq)
  67 {
  68         int i;
  69
  70         for (i = 0; i < wq->num_descs; i++)
  71                 kfree(wq->hw_descs[i]);
  72
  73         kfree(wq->hw_descs);
  74 }
  75
  76 static int alloc_hw_descs(struct idxd_wq *wq, int num)
  77 {
  78         struct device *dev = &wq->idxd->pdev->dev;
  79         int i;
  80         int node = dev_to_node(dev);
  81
  82         wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
  83                                     GFP_KERNEL, node);
  84         if (!wq->hw_descs)
  85                 return -ENOMEM;
  86
  87         for (i = 0; i < num; i++) {
  88                 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
  89                                                GFP_KERNEL, node);
  90                 if (!wq->hw_descs[i]) {
  91                         free_hw_descs(wq);
  92                         return -ENOMEM;
  93                 }
  94         }
  95
  96         return 0;
  97 }
  98
  99 static void free_descs(struct idxd_wq *wq)
 100 {
 101         int i;
 102
 103         for (i = 0; i < wq->num_descs; i++)
 104                 kfree(wq->descs[i]);
 105
 106         kfree(wq->descs);
 107 }
 108
 109 static int alloc_descs(struct idxd_wq *wq, int num)
 110 {
 111         struct device *dev = &wq->idxd->pdev->dev;
 112         int i;
 113         int node = dev_to_node(dev);
 114
 115         wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
 116                                  GFP_KERNEL, node);
 117         if (!wq->descs)
 118                 return -ENOMEM;
 119
 120         for (i = 0; i < num; i++) {
 121                 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
 122                                             GFP_KERNEL, node);
 123                 if (!wq->descs[i]) {
 124                         free_descs(wq);
 125                         return -ENOMEM;
 126                 }
 127         }
 128
 129         return 0;
 130 }
 131
 132 /* WQ control bits */
 133 int idxd_wq_alloc_resources(struct idxd_wq *wq)
 134 {
 135         struct idxd_device *idxd = wq->idxd;
 136         struct device *dev = &idxd->pdev->dev;
 137         int rc, num_descs, i;
 138         int align;
 139         u64 tmp;
 140
 141         if (wq->type != IDXD_WQT_KERNEL)
 142                 return 0;
 143
 144         num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
 145         wq->num_descs = num_descs;
 146
 147         rc = alloc_hw_descs(wq, num_descs);
 148         if (rc < 0)
 149                 return rc;
 150
 151         align = idxd->data->align;
 152         wq->compls_size = num_descs * idxd->data->compl_size + align;
 153         wq->compls_raw = dma_alloc_coherent(dev, wq->compls_size,
 154                                             &wq->compls_addr_raw, GFP_KERNEL);
 155         if (!wq->compls_raw) {
 156                 rc = -ENOMEM;
 157                 goto fail_alloc_compls;
 158         }
 159
 160         /* Adjust alignment */
 161         wq->compls_addr = (wq->compls_addr_raw + (align - 1)) & ~(align - 1);
 162         tmp = (u64)wq->compls_raw;
 163         tmp = (tmp + (align - 1)) & ~(align - 1);
 164         wq->compls = (struct dsa_completion_record *)tmp;
 165
 166         rc = alloc_descs(wq, num_descs);
 167         if (rc < 0)
 168                 goto fail_alloc_descs;
 169
 170         rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
 171                                      dev_to_node(dev));
 172         if (rc < 0)
 173                 goto fail_sbitmap_init;
 174
 175         for (i = 0; i < num_descs; i++) {
 176                 struct idxd_desc *desc = wq->descs[i];
 177
 178                 desc->hw = wq->hw_descs[i];
 179                 if (idxd->data->type == IDXD_TYPE_DSA)
 180                         desc->completion = &wq->compls[i];
 181                 else if (idxd->data->type == IDXD_TYPE_IAX)
 182                         desc->iax_completion = &wq->iax_compls[i];
 183                 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
 184                 desc->id = i;
 185                 desc->wq = wq;
 186                 desc->cpu = -1;
 187         }
 188
 189         return 0;
 190
 191  fail_sbitmap_init:
 192         free_descs(wq);
 193  fail_alloc_descs:
 194         dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
 195                           wq->compls_addr_raw);
 196  fail_alloc_compls:
 197         free_hw_descs(wq);
 198         return rc;
 199 }
 200
 201 void idxd_wq_free_resources(struct idxd_wq *wq)
 202 {
 203         struct device *dev = &wq->idxd->pdev->dev;
 204
 205         if (wq->type != IDXD_WQT_KERNEL)
 206                 return;
 207
 208         free_hw_descs(wq);
 209         free_descs(wq);
 210         dma_free_coherent(dev, wq->compls_size, wq->compls_raw,
 211                           wq->compls_addr_raw);
 212         sbitmap_queue_free(&wq->sbq);
 213 }
 214
 215 int idxd_wq_enable(struct idxd_wq *wq)
 216 {
 217         struct idxd_device *idxd = wq->idxd;
 218         struct device *dev = &idxd->pdev->dev;
 219         u32 status;
 220
 221         if (wq->state == IDXD_WQ_ENABLED) {
 222                 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
 223                 return -ENXIO;
 224         }
 225
 226         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
 227
 228         if (status != IDXD_CMDSTS_SUCCESS &&
 229             status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
 230                 dev_dbg(dev, "WQ enable failed: %#x\n", status);
 231                 return -ENXIO;
 232         }
 233
 234         wq->state = IDXD_WQ_ENABLED;
 235         dev_dbg(dev, "WQ %d enabled\n", wq->id);
 236         return 0;
 237 }
 238
 239 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
 240 {
 241         struct idxd_device *idxd = wq->idxd;
 242         struct device *dev = &idxd->pdev->dev;
 243         u32 status, operand;
 244
 245         dev_dbg(dev, "Disabling WQ %d\n", wq->id);
 246
 247         if (wq->state != IDXD_WQ_ENABLED) {
 248                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 249                 return 0;
 250         }
 251
 252         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 253         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
 254
 255         if (status != IDXD_CMDSTS_SUCCESS) {
 256                 dev_dbg(dev, "WQ disable failed: %#x\n", status);
 257                 return -ENXIO;
 258         }
 259
 260         if (reset_config)
 261                 idxd_wq_disable_cleanup(wq);
 262         wq->state = IDXD_WQ_DISABLED;
 263         dev_dbg(dev, "WQ %d disabled\n", wq->id);
 264         return 0;
 265 }
 266
 267 void idxd_wq_drain(struct idxd_wq *wq)
 268 {
 269         struct idxd_device *idxd = wq->idxd;
 270         struct device *dev = &idxd->pdev->dev;
 271         u32 operand;
 272
 273         if (wq->state != IDXD_WQ_ENABLED) {
 274                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 275                 return;
 276         }
 277
 278         dev_dbg(dev, "Draining WQ %d\n", wq->id);
 279         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 280         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
 281 }
 282
 283 void idxd_wq_reset(struct idxd_wq *wq)
 284 {
 285         struct idxd_device *idxd = wq->idxd;
 286         struct device *dev = &idxd->pdev->dev;
 287         u32 operand;
 288
 289         if (wq->state != IDXD_WQ_ENABLED) {
 290                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 291                 return;
 292         }
 293
 294         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 295         idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
 296         idxd_wq_disable_cleanup(wq);
 297         wq->state = IDXD_WQ_DISABLED;
 298 }
 299
 300 int idxd_wq_map_portal(struct idxd_wq *wq)
 301 {
 302         struct idxd_device *idxd = wq->idxd;
 303         struct pci_dev *pdev = idxd->pdev;
 304         struct device *dev = &pdev->dev;
 305         resource_size_t start;
 306
 307         start = pci_resource_start(pdev, IDXD_WQ_BAR);
 308         start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
 309
 310         wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
 311         if (!wq->portal)
 312                 return -ENOMEM;
 313
 314         return 0;
 315 }
 316
 317 void idxd_wq_unmap_portal(struct idxd_wq *wq)
 318 {
 319         struct device *dev = &wq->idxd->pdev->dev;
 320
 321         devm_iounmap(dev, wq->portal);
 322         wq->portal = NULL;
 323         wq->portal_offset = 0;
 324 }
 325
 326 void idxd_wqs_unmap_portal(struct idxd_device *idxd)
 327 {
 328         int i;
 329
 330         for (i = 0; i < idxd->max_wqs; i++) {
 331                 struct idxd_wq *wq = idxd->wqs[i];
 332
 333                 if (wq->portal)
 334                         idxd_wq_unmap_portal(wq);
 335         }
 336 }
 337
 338 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
 339 {
 340         struct idxd_device *idxd = wq->idxd;
 341         int rc;
 342         union wqcfg wqcfg;
 343         unsigned int offset;
 344
 345         rc = idxd_wq_disable(wq, false);
 346         if (rc < 0)
 347                 return rc;
 348
 349         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 350         spin_lock(&idxd->dev_lock);
 351         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 352         wqcfg.pasid_en = 1;
 353         wqcfg.pasid = pasid;
 354         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 355         spin_unlock(&idxd->dev_lock);
 356
 357         rc = idxd_wq_enable(wq);
 358         if (rc < 0)
 359                 return rc;
 360
 361         return 0;
 362 }
 363
 364 int idxd_wq_disable_pasid(struct idxd_wq *wq)
 365 {
 366         struct idxd_device *idxd = wq->idxd;
 367         int rc;
 368         union wqcfg wqcfg;
 369         unsigned int offset;
 370
 371         rc = idxd_wq_disable(wq, false);
 372         if (rc < 0)
 373                 return rc;
 374
 375         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 376         spin_lock(&idxd->dev_lock);
 377         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 378         wqcfg.pasid_en = 0;
 379         wqcfg.pasid = 0;
 380         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 381         spin_unlock(&idxd->dev_lock);
 382
 383         rc = idxd_wq_enable(wq);
 384         if (rc < 0)
 385                 return rc;
 386
 387         return 0;
 388 }
 389
 390 static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
 391 {
 392         struct idxd_device *idxd = wq->idxd;
 393
 394         lockdep_assert_held(&wq->wq_lock);
 395         memset(wq->wqcfg, 0, idxd->wqcfg_size);
 396         wq->type = IDXD_WQT_NONE;
 397         wq->threshold = 0;
 398         wq->priority = 0;
 399         wq->ats_dis = 0;
 400         clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
 401         clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
 402         memset(wq->name, 0, WQ_NAME_SIZE);
 403 }
 404
 405 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
 406 {
 407         lockdep_assert_held(&wq->wq_lock);
 408
 409         wq->size = 0;
 410         wq->group = NULL;
 411 }
 412
 413 static void idxd_wq_ref_release(struct percpu_ref *ref)
 414 {
 415         struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
 416
 417         complete(&wq->wq_dead);
 418 }
 419
 420 int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
 421 {
 422         int rc;
 423
 424         memset(&wq->wq_active, 0, sizeof(wq->wq_active));
 425         rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 0, GFP_KERNEL);
 426         if (rc < 0)
 427                 return rc;
 428         reinit_completion(&wq->wq_dead);
 429         return 0;
 430 }
 431
 432 void idxd_wq_quiesce(struct idxd_wq *wq)
 433 {
 434         percpu_ref_kill(&wq->wq_active);
 435         wait_for_completion(&wq->wq_dead);
 436 }
 437
 438 /* Device control bits */
 439 static inline bool idxd_is_enabled(struct idxd_device *idxd)
 440 {
 441         union gensts_reg gensts;
 442
 443         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 444
 445         if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
 446                 return true;
 447         return false;
 448 }
 449
 450 static inline bool idxd_device_is_halted(struct idxd_device *idxd)
 451 {
 452         union gensts_reg gensts;
 453
 454         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 455
 456         return (gensts.state == IDXD_DEVICE_STATE_HALT);
 457 }
 458
 459 /*
 460  * This is function is only used for reset during probe and will
 461  * poll for completion. Once the device is setup with interrupts,
 462  * all commands will be done via interrupt completion.
 463  */
 464 int idxd_device_init_reset(struct idxd_device *idxd)
 465 {
 466         struct device *dev = &idxd->pdev->dev;
 467         union idxd_command_reg cmd;
 468
 469         if (idxd_device_is_halted(idxd)) {
 470                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 471                 return -ENXIO;
 472         }
 473
 474         memset(&cmd, 0, sizeof(cmd));
 475         cmd.cmd = IDXD_CMD_RESET_DEVICE;
 476         dev_dbg(dev, "%s: sending reset for init.\n", __func__);
 477         spin_lock(&idxd->cmd_lock);
 478         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 479
 480         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
 481                IDXD_CMDSTS_ACTIVE)
 482                 cpu_relax();
 483         spin_unlock(&idxd->cmd_lock);
 484         return 0;
 485 }
 486
 487 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
 488                           u32 *status)
 489 {
 490         union idxd_command_reg cmd;
 491         DECLARE_COMPLETION_ONSTACK(done);
 492         u32 stat;
 493
 494         if (idxd_device_is_halted(idxd)) {
 495                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 496                 if (status)
 497                         *status = IDXD_CMDSTS_HW_ERR;
 498                 return;
 499         }
 500
 501         memset(&cmd, 0, sizeof(cmd));
 502         cmd.cmd = cmd_code;
 503         cmd.operand = operand;
 504         cmd.int_req = 1;
 505
 506         spin_lock(&idxd->cmd_lock);
 507         wait_event_lock_irq(idxd->cmd_waitq,
 508                             !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
 509                             idxd->cmd_lock);
 510
 511         dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
 512                 __func__, cmd_code, operand);
 513
 514         idxd->cmd_status = 0;
 515         __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 516         idxd->cmd_done = &done;
 517         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 518
 519         /*
 520          * After command submitted, release lock and go to sleep until
 521          * the command completes via interrupt.
 522          */
 523         spin_unlock(&idxd->cmd_lock);
 524         wait_for_completion(&done);
 525         stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 526         spin_lock(&idxd->cmd_lock);
 527         if (status)
 528                 *status = stat;
 529         idxd->cmd_status = stat & GENMASK(7, 0);
 530
 531         __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 532         /* Wake up other pending commands */
 533         wake_up(&idxd->cmd_waitq);
 534         spin_unlock(&idxd->cmd_lock);
 535 }
 536
 537 int idxd_device_enable(struct idxd_device *idxd)
 538 {
 539         struct device *dev = &idxd->pdev->dev;
 540         u32 status;
 541
 542         if (idxd_is_enabled(idxd)) {
 543                 dev_dbg(dev, "Device already enabled\n");
 544                 return -ENXIO;
 545         }
 546
 547         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
 548
 549         /* If the command is successful or if the device was enabled */
 550         if (status != IDXD_CMDSTS_SUCCESS &&
 551             status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
 552                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 553                 return -ENXIO;
 554         }
 555
 556         idxd->state = IDXD_DEV_ENABLED;
 557         return 0;
 558 }
 559
 560 int idxd_device_disable(struct idxd_device *idxd)
 561 {
 562         struct device *dev = &idxd->pdev->dev;
 563         u32 status;
 564
 565         if (!idxd_is_enabled(idxd)) {
 566                 dev_dbg(dev, "Device is not enabled\n");
 567                 return 0;
 568         }
 569
 570         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
 571
 572         /* If the command is successful or if the device was disabled */
 573         if (status != IDXD_CMDSTS_SUCCESS &&
 574             !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
 575                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 576                 return -ENXIO;
 577         }
 578
 579         spin_lock(&idxd->dev_lock);
 580         idxd_device_clear_state(idxd);
 581         idxd->state = IDXD_DEV_DISABLED;
 582         spin_unlock(&idxd->dev_lock);
 583         return 0;
 584 }
 585
 586 void idxd_device_reset(struct idxd_device *idxd)
 587 {
 588         idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
 589         spin_lock(&idxd->dev_lock);
 590         idxd_device_clear_state(idxd);
 591         idxd->state = IDXD_DEV_DISABLED;
 592         idxd_unmask_error_interrupts(idxd);
 593         idxd_msix_perm_setup(idxd);
 594         spin_unlock(&idxd->dev_lock);
 595 }
 596
 597 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
 598 {
 599         struct device *dev = &idxd->pdev->dev;
 600         u32 operand;
 601
 602         operand = pasid;
 603         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
 604         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
 605         dev_dbg(dev, "pasid %d drained\n", pasid);
 606 }
 607
 608 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
 609                                    enum idxd_interrupt_type irq_type)
 610 {
 611         struct device *dev = &idxd->pdev->dev;
 612         u32 operand, status;
 613
 614         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
 615                 return -EOPNOTSUPP;
 616
 617         dev_dbg(dev, "get int handle, idx %d\n", idx);
 618
 619         operand = idx & GENMASK(15, 0);
 620         if (irq_type == IDXD_IRQ_IMS)
 621                 operand |= CMD_INT_HANDLE_IMS;
 622
 623         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
 624
 625         idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
 626
 627         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 628                 dev_dbg(dev, "request int handle failed: %#x\n", status);
 629                 return -ENXIO;
 630         }
 631
 632         *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
 633
 634         dev_dbg(dev, "int handle acquired: %u\n", *handle);
 635         return 0;
 636 }
 637
 638 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
 639                                    enum idxd_interrupt_type irq_type)
 640 {
 641         struct device *dev = &idxd->pdev->dev;
 642         u32 operand, status;
 643         union idxd_command_reg cmd;
 644
 645         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
 646                 return -EOPNOTSUPP;
 647
 648         dev_dbg(dev, "release int handle, handle %d\n", handle);
 649
 650         memset(&cmd, 0, sizeof(cmd));
 651         operand = handle & GENMASK(15, 0);
 652
 653         if (irq_type == IDXD_IRQ_IMS)
 654                 operand |= CMD_INT_HANDLE_IMS;
 655
 656         cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
 657         cmd.operand = operand;
 658
 659         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
 660
 661         spin_lock(&idxd->cmd_lock);
 662         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 663
 664         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
 665                 cpu_relax();
 666         status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 667         spin_unlock(&idxd->cmd_lock);
 668
 669         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 670                 dev_dbg(dev, "release int handle failed: %#x\n", status);
 671                 return -ENXIO;
 672         }
 673
 674         dev_dbg(dev, "int handle released.\n");
 675         return 0;
 676 }
 677
 678 /* Device configuration bits */
 679 static void idxd_engines_clear_state(struct idxd_device *idxd)
 680 {
 681         struct idxd_engine *engine;
 682         int i;
 683
 684         lockdep_assert_held(&idxd->dev_lock);
 685         for (i = 0; i < idxd->max_engines; i++) {
 686                 engine = idxd->engines[i];
 687                 engine->group = NULL;
 688         }
 689 }
 690
 691 static void idxd_groups_clear_state(struct idxd_device *idxd)
 692 {
 693         struct idxd_group *group;
 694         int i;
 695
 696         lockdep_assert_held(&idxd->dev_lock);
 697         for (i = 0; i < idxd->max_groups; i++) {
 698                 group = idxd->groups[i];
 699                 memset(&group->grpcfg, 0, sizeof(group->grpcfg));
 700                 group->num_engines = 0;
 701                 group->num_wqs = 0;
 702                 group->use_rdbuf_limit = false;
 703                 group->rdbufs_allowed = 0;
 704                 group->rdbufs_reserved = 0;
 705                 if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) {
 706                         group->tc_a = 1;
 707                         group->tc_b = 1;
 708                 } else {
 709                         group->tc_a = -1;
 710                         group->tc_b = -1;
 711                 }
 712         }
 713 }
 714
 715 static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
 716 {
 717         int i;
 718
 719         lockdep_assert_held(&idxd->dev_lock);
 720         for (i = 0; i < idxd->max_wqs; i++) {
 721                 struct idxd_wq *wq = idxd->wqs[i];
 722
 723                 if (wq->state == IDXD_WQ_ENABLED) {
 724                         idxd_wq_disable_cleanup(wq);
 725                         wq->state = IDXD_WQ_DISABLED;
 726                 }
 727                 idxd_wq_device_reset_cleanup(wq);
 728         }
 729 }
 730
 731 void idxd_device_clear_state(struct idxd_device *idxd)
 732 {
 733         if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
 734                 return;
 735
 736         idxd_groups_clear_state(idxd);
 737         idxd_engines_clear_state(idxd);
 738         idxd_device_wqs_clear_state(idxd);
 739 }
 740
 741 void idxd_msix_perm_setup(struct idxd_device *idxd)
 742 {
 743         union msix_perm mperm;
 744         int i, msixcnt;
 745
 746         msixcnt = pci_msix_vec_count(idxd->pdev);
 747         if (msixcnt < 0)
 748                 return;
 749
 750         mperm.bits = 0;
 751         mperm.pasid = idxd->pasid;
 752         mperm.pasid_en = device_pasid_enabled(idxd);
 753         for (i = 1; i < msixcnt; i++)
 754                 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
 755 }
 756
 757 void idxd_msix_perm_clear(struct idxd_device *idxd)
 758 {
 759         union msix_perm mperm;
 760         int i, msixcnt;
 761
 762         msixcnt = pci_msix_vec_count(idxd->pdev);
 763         if (msixcnt < 0)
 764                 return;
 765
 766         mperm.bits = 0;
 767         for (i = 1; i < msixcnt; i++)
 768                 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + i * 8);
 769 }
 770
 771 static void idxd_group_config_write(struct idxd_group *group)
 772 {
 773         struct idxd_device *idxd = group->idxd;
 774         struct device *dev = &idxd->pdev->dev;
 775         int i;
 776         u32 grpcfg_offset;
 777
 778         dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
 779
 780         /* setup GRPWQCFG */
 781         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
 782                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
 783                 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
 784                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
 785                         group->id, i, grpcfg_offset,
 786                         ioread64(idxd->reg_base + grpcfg_offset));
 787         }
 788
 789         /* setup GRPENGCFG */
 790         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
 791         iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
 792         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
 793                 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
 794
 795         /* setup GRPFLAGS */
 796         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
 797         iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
 798         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
 799                 group->id, grpcfg_offset,
 800                 ioread32(idxd->reg_base + grpcfg_offset));
 801 }
 802
 803 static int idxd_groups_config_write(struct idxd_device *idxd)
 804
 805 {
 806         union gencfg_reg reg;
 807         int i;
 808         struct device *dev = &idxd->pdev->dev;
 809
 810         /* Setup bandwidth rdbuf limit */
 811         if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) {
 812                 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 813                 reg.rdbuf_limit = idxd->rdbuf_limit;
 814                 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 815         }
 816
 817         dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
 818                 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
 819
 820         for (i = 0; i < idxd->max_groups; i++) {
 821                 struct idxd_group *group = idxd->groups[i];
 822
 823                 idxd_group_config_write(group);
 824         }
 825
 826         return 0;
 827 }
 828
 829 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
 830 {
 831         struct pci_dev *pdev = idxd->pdev;
 832
 833         if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
 834                 return true;
 835         return false;
 836 }
 837
 838 static int idxd_wq_config_write(struct idxd_wq *wq)
 839 {
 840         struct idxd_device *idxd = wq->idxd;
 841         struct device *dev = &idxd->pdev->dev;
 842         u32 wq_offset;
 843         int i;
 844
 845         if (!wq->group)
 846                 return 0;
 847
 848         /*
 849          * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
 850          * wq reset. This will copy back the sticky values that are present on some devices.
 851          */
 852         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 853                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 854                 wq->wqcfg->bits[i] = ioread32(idxd->reg_base + wq_offset);
 855         }
 856
 857         /* byte 0-3 */
 858         wq->wqcfg->wq_size = wq->size;
 859
 860         if (wq->size == 0) {
 861                 idxd->cmd_status = IDXD_SCMD_WQ_NO_SIZE;
 862                 dev_warn(dev, "Incorrect work queue size: 0\n");
 863                 return -EINVAL;
 864         }
 865
 866         /* bytes 4-7 */
 867         wq->wqcfg->wq_thresh = wq->threshold;
 868
 869         /* byte 8-11 */
 870         if (wq_dedicated(wq))
 871                 wq->wqcfg->mode = 1;
 872
 873         if (device_pasid_enabled(idxd)) {
 874                 wq->wqcfg->pasid_en = 1;
 875                 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq))
 876                         wq->wqcfg->pasid = idxd->pasid;
 877         }
 878
 879         /*
 880          * Here the priv bit is set depending on the WQ type. priv = 1 if the
 881          * WQ type is kernel to indicate privileged access. This setting only
 882          * matters for dedicated WQ. According to the DSA spec:
 883          * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
 884          * Privileged Mode Enable field of the PCI Express PASID capability
 885          * is 0, this field must be 0.
 886          *
 887          * In the case of a dedicated kernel WQ that is not able to support
 888          * the PASID cap, then the configuration will be rejected.
 889          */
 890         wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL);
 891         if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
 892             !idxd_device_pasid_priv_enabled(idxd) &&
 893             wq->type == IDXD_WQT_KERNEL) {
 894                 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
 895                 return -EOPNOTSUPP;
 896         }
 897
 898         wq->wqcfg->priority = wq->priority;
 899
 900         if (idxd->hw.gen_cap.block_on_fault &&
 901             test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags))
 902                 wq->wqcfg->bof = 1;
 903
 904         if (idxd->hw.wq_cap.wq_ats_support)
 905                 wq->wqcfg->wq_ats_disable = wq->ats_dis;
 906
 907         /* bytes 12-15 */
 908         wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
 909         wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size);
 910
 911         dev_dbg(dev, "WQ %d CFGs\n", wq->id);
 912         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 913                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 914                 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
 915                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
 916                         wq->id, i, wq_offset,
 917                         ioread32(idxd->reg_base + wq_offset));
 918         }
 919
 920         return 0;
 921 }
 922
 923 static int idxd_wqs_config_write(struct idxd_device *idxd)
 924 {
 925         int i, rc;
 926
 927         for (i = 0; i < idxd->max_wqs; i++) {
 928                 struct idxd_wq *wq = idxd->wqs[i];
 929
 930                 rc = idxd_wq_config_write(wq);
 931                 if (rc < 0)
 932                         return rc;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static void idxd_group_flags_setup(struct idxd_device *idxd)
 939 {
 940         int i;
 941
 942         /* TC-A 0 and TC-B 1 should be defaults */
 943         for (i = 0; i < idxd->max_groups; i++) {
 944                 struct idxd_group *group = idxd->groups[i];
 945
 946                 if (group->tc_a == -1)
 947                         group->tc_a = group->grpcfg.flags.tc_a = 0;
 948                 else
 949                         group->grpcfg.flags.tc_a = group->tc_a;
 950                 if (group->tc_b == -1)
 951                         group->tc_b = group->grpcfg.flags.tc_b = 1;
 952                 else
 953                         group->grpcfg.flags.tc_b = group->tc_b;
 954                 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
 955                 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
 956                 if (group->rdbufs_allowed)
 957                         group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
 958                 else
 959                         group->grpcfg.flags.rdbufs_allowed = idxd->max_rdbufs;
 960         }
 961 }
 962
 963 static int idxd_engines_setup(struct idxd_device *idxd)
 964 {
 965         int i, engines = 0;
 966         struct idxd_engine *eng;
 967         struct idxd_group *group;
 968
 969         for (i = 0; i < idxd->max_groups; i++) {
 970                 group = idxd->groups[i];
 971                 group->grpcfg.engines = 0;
 972         }
 973
 974         for (i = 0; i < idxd->max_engines; i++) {
 975                 eng = idxd->engines[i];
 976                 group = eng->group;
 977
 978                 if (!group)
 979                         continue;
 980
 981                 group->grpcfg.engines |= BIT(eng->id);
 982                 engines++;
 983         }
 984
 985         if (!engines)
 986                 return -EINVAL;
 987
 988         return 0;
 989 }
 990
 991 static int idxd_wqs_setup(struct idxd_device *idxd)
 992 {
 993         struct idxd_wq *wq;
 994         struct idxd_group *group;
 995         int i, j, configured = 0;
 996         struct device *dev = &idxd->pdev->dev;
 997
 998         for (i = 0; i < idxd->max_groups; i++) {
 999                 group = idxd->groups[i];
1000                 for (j = 0; j < 4; j++)
1001                         group->grpcfg.wqs[j] = 0;
1002         }
1003
1004         for (i = 0; i < idxd->max_wqs; i++) {
1005                 wq = idxd->wqs[i];
1006                 group = wq->group;
1007
1008                 if (!wq->group)
1009                         continue;
1010                 if (!wq->size)
1011                         continue;
1012
1013                 if (wq_shared(wq) && !device_swq_supported(idxd)) {
1014                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
1015                         dev_warn(dev, "No shared wq support but configured.\n");
1016                         return -EINVAL;
1017                 }
1018
1019                 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
1020                 configured++;
1021         }
1022
1023         if (configured == 0) {
1024                 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
1025                 return -EINVAL;
1026         }
1027
1028         return 0;
1029 }
1030
1031 int idxd_device_config(struct idxd_device *idxd)
1032 {
1033         int rc;
1034
1035         lockdep_assert_held(&idxd->dev_lock);
1036         rc = idxd_wqs_setup(idxd);
1037         if (rc < 0)
1038                 return rc;
1039
1040         rc = idxd_engines_setup(idxd);
1041         if (rc < 0)
1042                 return rc;
1043
1044         idxd_group_flags_setup(idxd);
1045
1046         rc = idxd_wqs_config_write(idxd);
1047         if (rc < 0)
1048                 return rc;
1049
1050         rc = idxd_groups_config_write(idxd);
1051         if (rc < 0)
1052                 return rc;
1053
1054         return 0;
1055 }
1056
1057 static int idxd_wq_load_config(struct idxd_wq *wq)
1058 {
1059         struct idxd_device *idxd = wq->idxd;
1060         struct device *dev = &idxd->pdev->dev;
1061         int wqcfg_offset;
1062         int i;
1063
1064         wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1065         memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1066
1067         wq->size = wq->wqcfg->wq_size;
1068         wq->threshold = wq->wqcfg->wq_thresh;
1069         if (wq->wqcfg->priv)
1070                 wq->type = IDXD_WQT_KERNEL;
1071
1072         /* The driver does not support shared WQ mode in read-only config yet */
1073         if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1074                 return -EOPNOTSUPP;
1075
1076         set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1077
1078         wq->priority = wq->wqcfg->priority;
1079
1080         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1081                 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1082                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1083         }
1084
1085         return 0;
1086 }
1087
1088 static void idxd_group_load_config(struct idxd_group *group)
1089 {
1090         struct idxd_device *idxd = group->idxd;
1091         struct device *dev = &idxd->pdev->dev;
1092         int i, j, grpcfg_offset;
1093
1094         /*
1095          * Load WQS bit fields
1096          * Iterate through all 256 bits 64 bits at a time
1097          */
1098         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1099                 struct idxd_wq *wq;
1100
1101                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1102                 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1103                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1104                         group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1105
1106                 if (i * 64 >= idxd->max_wqs)
1107                         break;
1108
1109                 /* Iterate through all 64 bits and check for wq set */
1110                 for (j = 0; j < 64; j++) {
1111                         int id = i * 64 + j;
1112
1113                         /* No need to check beyond max wqs */
1114                         if (id >= idxd->max_wqs)
1115                                 break;
1116
1117                         /* Set group assignment for wq if wq bit is set */
1118                         if (group->grpcfg.wqs[i] & BIT(j)) {
1119                                 wq = idxd->wqs[id];
1120                                 wq->group = group;
1121                         }
1122                 }
1123         }
1124
1125         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1126         group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1127         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1128                 grpcfg_offset, group->grpcfg.engines);
1129
1130         /* Iterate through all 64 bits to check engines set */
1131         for (i = 0; i < 64; i++) {
1132                 if (i >= idxd->max_engines)
1133                         break;
1134
1135                 if (group->grpcfg.engines & BIT(i)) {
1136                         struct idxd_engine *engine = idxd->engines[i];
1137
1138                         engine->group = group;
1139                 }
1140         }
1141
1142         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1143         group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset);
1144         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n",
1145                 group->id, grpcfg_offset, group->grpcfg.flags.bits);
1146 }
1147
1148 int idxd_device_load_config(struct idxd_device *idxd)
1149 {
1150         union gencfg_reg reg;
1151         int i, rc;
1152
1153         reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
1154         idxd->rdbuf_limit = reg.rdbuf_limit;
1155
1156         for (i = 0; i < idxd->max_groups; i++) {
1157                 struct idxd_group *group = idxd->groups[i];
1158
1159                 idxd_group_load_config(group);
1160         }
1161
1162         for (i = 0; i < idxd->max_wqs; i++) {
1163                 struct idxd_wq *wq = idxd->wqs[i];
1164
1165                 rc = idxd_wq_load_config(wq);
1166                 if (rc < 0)
1167                         return rc;
1168         }
1169
1170         return 0;
1171 }
1172
1173 int __drv_enable_wq(struct idxd_wq *wq)
1174 {
1175         struct idxd_device *idxd = wq->idxd;
1176         struct device *dev = &idxd->pdev->dev;
1177         int rc = -ENXIO;
1178
1179         lockdep_assert_held(&wq->wq_lock);
1180
1181         if (idxd->state != IDXD_DEV_ENABLED) {
1182                 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
1183                 goto err;
1184         }
1185
1186         if (wq->state != IDXD_WQ_DISABLED) {
1187                 dev_dbg(dev, "wq %d already enabled.\n", wq->id);
1188                 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
1189                 rc = -EBUSY;
1190                 goto err;
1191         }
1192
1193         if (!wq->group) {
1194                 dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
1195                 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
1196                 goto err;
1197         }
1198
1199         if (strlen(wq->name) == 0) {
1200                 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
1201                 dev_dbg(dev, "wq %d name not set.\n", wq->id);
1202                 goto err;
1203         }
1204
1205         /* Shared WQ checks */
1206         if (wq_shared(wq)) {
1207                 if (!device_swq_supported(idxd)) {
1208                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
1209                         dev_dbg(dev, "PASID not enabled and shared wq.\n");
1210                         goto err;
1211                 }
1212                 /*
1213                  * Shared wq with the threshold set to 0 means the user
1214                  * did not set the threshold or transitioned from a
1215                  * dedicated wq but did not set threshold. A value
1216                  * of 0 would effectively disable the shared wq. The
1217                  * driver does not allow a value of 0 to be set for
1218                  * threshold via sysfs.
1219                  */
1220                 if (wq->threshold == 0) {
1221                         idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
1222                         dev_dbg(dev, "Shared wq and threshold 0.\n");
1223                         goto err;
1224                 }
1225         }
1226
1227         rc = 0;
1228         spin_lock(&idxd->dev_lock);
1229         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1230                 rc = idxd_device_config(idxd);
1231         spin_unlock(&idxd->dev_lock);
1232         if (rc < 0) {
1233                 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1234                 goto err;
1235         }
1236
1237         rc = idxd_wq_enable(wq);
1238         if (rc < 0) {
1239                 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1240                 goto err;
1241         }
1242
1243         rc = idxd_wq_map_portal(wq);
1244         if (rc < 0) {
1245                 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
1246                 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1247                 goto err_map_portal;
1248         }
1249
1250         wq->client_count = 0;
1251         return 0;
1252
1253 err_map_portal:
1254         rc = idxd_wq_disable(wq, false);
1255         if (rc < 0)
1256                 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1257 err:
1258         return rc;
1259 }
1260
1261 int drv_enable_wq(struct idxd_wq *wq)
1262 {
1263         int rc;
1264
1265         mutex_lock(&wq->wq_lock);
1266         rc = __drv_enable_wq(wq);
1267         mutex_unlock(&wq->wq_lock);
1268         return rc;
1269 }
1270
1271 void __drv_disable_wq(struct idxd_wq *wq)
1272 {
1273         struct idxd_device *idxd = wq->idxd;
1274         struct device *dev = &idxd->pdev->dev;
1275
1276         lockdep_assert_held(&wq->wq_lock);
1277
1278         if (idxd_wq_refcount(wq))
1279                 dev_warn(dev, "Clients has claim on wq %d: %d\n",
1280                          wq->id, idxd_wq_refcount(wq));
1281
1282         idxd_wq_unmap_portal(wq);
1283
1284         idxd_wq_drain(wq);
1285         idxd_wq_reset(wq);
1286
1287         wq->client_count = 0;
1288 }
1289
1290 void drv_disable_wq(struct idxd_wq *wq)
1291 {
1292         mutex_lock(&wq->wq_lock);
1293         __drv_disable_wq(wq);
1294         mutex_unlock(&wq->wq_lock);
1295 }
1296
1297 int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1298 {
1299         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1300         int rc = 0;
1301
1302         /*
1303          * Device should be in disabled state for the idxd_drv to load. If it's in
1304          * enabled state, then the device was altered outside of driver's control.
1305          * If the state is in halted state, then we don't want to proceed.
1306          */
1307         if (idxd->state != IDXD_DEV_DISABLED) {
1308                 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
1309                 return -ENXIO;
1310         }
1311
1312         /* Device configuration */
1313         spin_lock(&idxd->dev_lock);
1314         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1315                 rc = idxd_device_config(idxd);
1316         spin_unlock(&idxd->dev_lock);
1317         if (rc < 0)
1318                 return -ENXIO;
1319
1320         /* Start device */
1321         rc = idxd_device_enable(idxd);
1322         if (rc < 0)
1323                 return rc;
1324
1325         /* Setup DMA device without channels */
1326         rc = idxd_register_dma_device(idxd);
1327         if (rc < 0) {
1328                 idxd_device_disable(idxd);
1329                 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
1330                 return rc;
1331         }
1332
1333         idxd->cmd_status = 0;
1334         return 0;
1335 }
1336
1337 void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1338 {
1339         struct device *dev = &idxd_dev->conf_dev;
1340         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1341         int i;
1342
1343         for (i = 0; i < idxd->max_wqs; i++) {
1344                 struct idxd_wq *wq = idxd->wqs[i];
1345                 struct device *wq_dev = wq_confdev(wq);
1346
1347                 if (wq->state == IDXD_WQ_DISABLED)
1348                         continue;
1349                 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1350                 device_release_driver(wq_dev);
1351         }
1352
1353         idxd_unregister_dma_device(idxd);
1354         idxd_device_disable(idxd);
1355         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1356                 idxd_device_reset(idxd);
1357 }
1358
1359 static enum idxd_dev_type dev_types[] = {
1360         IDXD_DEV_DSA,
1361         IDXD_DEV_IAX,
1362         IDXD_DEV_NONE,
1363 };
1364
1365 struct idxd_device_driver idxd_drv = {
1366         .type = dev_types,
1367         .probe = idxd_device_drv_probe,
1368         .remove = idxd_device_drv_remove,
1369         .name = "idxd",
1370 };
1371 EXPORT_SYMBOL_GPL(idxd_drv);