drivers/dma/idxd/device.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
   3 #include <linux/init.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/io-64-nonatomic-lo-hi.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/irq.h>
  10 #include <uapi/linux/idxd.h>
  11 #include "../dmaengine.h"
  12 #include "idxd.h"
  13 #include "registers.h"
  14
  15 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
  16                           u32 *status);
  17 static void idxd_device_wqs_clear_state(struct idxd_device *idxd);
  18 static void idxd_wq_disable_cleanup(struct idxd_wq *wq);
  19
  20 /* Interrupt control bits */
  21 void idxd_unmask_error_interrupts(struct idxd_device *idxd)
  22 {
  23         union genctrl_reg genctrl;
  24
  25         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  26         genctrl.softerr_int_en = 1;
  27         genctrl.halt_int_en = 1;
  28         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  29 }
  30
  31 void idxd_mask_error_interrupts(struct idxd_device *idxd)
  32 {
  33         union genctrl_reg genctrl;
  34
  35         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
  36         genctrl.softerr_int_en = 0;
  37         genctrl.halt_int_en = 0;
  38         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
  39 }
  40
  41 static void free_hw_descs(struct idxd_wq *wq)
  42 {
  43         int i;
  44
  45         for (i = 0; i < wq->num_descs; i++)
  46                 kfree(wq->hw_descs[i]);
  47
  48         kfree(wq->hw_descs);
  49 }
  50
  51 static int alloc_hw_descs(struct idxd_wq *wq, int num)
  52 {
  53         struct device *dev = &wq->idxd->pdev->dev;
  54         int i;
  55         int node = dev_to_node(dev);
  56
  57         wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *),
  58                                     GFP_KERNEL, node);
  59         if (!wq->hw_descs)
  60                 return -ENOMEM;
  61
  62         for (i = 0; i < num; i++) {
  63                 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]),
  64                                                GFP_KERNEL, node);
  65                 if (!wq->hw_descs[i]) {
  66                         free_hw_descs(wq);
  67                         return -ENOMEM;
  68                 }
  69         }
  70
  71         return 0;
  72 }
  73
  74 static void free_descs(struct idxd_wq *wq)
  75 {
  76         int i;
  77
  78         for (i = 0; i < wq->num_descs; i++)
  79                 kfree(wq->descs[i]);
  80
  81         kfree(wq->descs);
  82 }
  83
  84 static int alloc_descs(struct idxd_wq *wq, int num)
  85 {
  86         struct device *dev = &wq->idxd->pdev->dev;
  87         int i;
  88         int node = dev_to_node(dev);
  89
  90         wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *),
  91                                  GFP_KERNEL, node);
  92         if (!wq->descs)
  93                 return -ENOMEM;
  94
  95         for (i = 0; i < num; i++) {
  96                 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]),
  97                                             GFP_KERNEL, node);
  98                 if (!wq->descs[i]) {
  99                         free_descs(wq);
 100                         return -ENOMEM;
 101                 }
 102         }
 103
 104         return 0;
 105 }
 106
 107 /* WQ control bits */
 108 int idxd_wq_alloc_resources(struct idxd_wq *wq)
 109 {
 110         struct idxd_device *idxd = wq->idxd;
 111         struct device *dev = &idxd->pdev->dev;
 112         int rc, num_descs, i;
 113
 114         if (wq->type != IDXD_WQT_KERNEL)
 115                 return 0;
 116
 117         num_descs = wq_dedicated(wq) ? wq->size : wq->threshold;
 118         wq->num_descs = num_descs;
 119
 120         rc = alloc_hw_descs(wq, num_descs);
 121         if (rc < 0)
 122                 return rc;
 123
 124         wq->compls_size = num_descs * idxd->data->compl_size;
 125         wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL);
 126         if (!wq->compls) {
 127                 rc = -ENOMEM;
 128                 goto fail_alloc_compls;
 129         }
 130
 131         rc = alloc_descs(wq, num_descs);
 132         if (rc < 0)
 133                 goto fail_alloc_descs;
 134
 135         rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL,
 136                                      dev_to_node(dev));
 137         if (rc < 0)
 138                 goto fail_sbitmap_init;
 139
 140         for (i = 0; i < num_descs; i++) {
 141                 struct idxd_desc *desc = wq->descs[i];
 142
 143                 desc->hw = wq->hw_descs[i];
 144                 if (idxd->data->type == IDXD_TYPE_DSA)
 145                         desc->completion = &wq->compls[i];
 146                 else if (idxd->data->type == IDXD_TYPE_IAX)
 147                         desc->iax_completion = &wq->iax_compls[i];
 148                 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i;
 149                 desc->id = i;
 150                 desc->wq = wq;
 151                 desc->cpu = -1;
 152         }
 153
 154         return 0;
 155
 156  fail_sbitmap_init:
 157         free_descs(wq);
 158  fail_alloc_descs:
 159         dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 160  fail_alloc_compls:
 161         free_hw_descs(wq);
 162         return rc;
 163 }
 164
 165 void idxd_wq_free_resources(struct idxd_wq *wq)
 166 {
 167         struct device *dev = &wq->idxd->pdev->dev;
 168
 169         if (wq->type != IDXD_WQT_KERNEL)
 170                 return;
 171
 172         free_hw_descs(wq);
 173         free_descs(wq);
 174         dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
 175         sbitmap_queue_free(&wq->sbq);
 176 }
 177
 178 int idxd_wq_enable(struct idxd_wq *wq)
 179 {
 180         struct idxd_device *idxd = wq->idxd;
 181         struct device *dev = &idxd->pdev->dev;
 182         u32 status;
 183
 184         if (wq->state == IDXD_WQ_ENABLED) {
 185                 dev_dbg(dev, "WQ %d already enabled\n", wq->id);
 186                 return 0;
 187         }
 188
 189         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status);
 190
 191         if (status != IDXD_CMDSTS_SUCCESS &&
 192             status != IDXD_CMDSTS_ERR_WQ_ENABLED) {
 193                 dev_dbg(dev, "WQ enable failed: %#x\n", status);
 194                 return -ENXIO;
 195         }
 196
 197         wq->state = IDXD_WQ_ENABLED;
 198         set_bit(wq->id, idxd->wq_enable_map);
 199         dev_dbg(dev, "WQ %d enabled\n", wq->id);
 200         return 0;
 201 }
 202
 203 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config)
 204 {
 205         struct idxd_device *idxd = wq->idxd;
 206         struct device *dev = &idxd->pdev->dev;
 207         u32 status, operand;
 208
 209         dev_dbg(dev, "Disabling WQ %d\n", wq->id);
 210
 211         if (wq->state != IDXD_WQ_ENABLED) {
 212                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 213                 return 0;
 214         }
 215
 216         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 217         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status);
 218
 219         if (status != IDXD_CMDSTS_SUCCESS) {
 220                 dev_dbg(dev, "WQ disable failed: %#x\n", status);
 221                 return -ENXIO;
 222         }
 223
 224         if (reset_config)
 225                 idxd_wq_disable_cleanup(wq);
 226         clear_bit(wq->id, idxd->wq_enable_map);
 227         wq->state = IDXD_WQ_DISABLED;
 228         dev_dbg(dev, "WQ %d disabled\n", wq->id);
 229         return 0;
 230 }
 231
 232 void idxd_wq_drain(struct idxd_wq *wq)
 233 {
 234         struct idxd_device *idxd = wq->idxd;
 235         struct device *dev = &idxd->pdev->dev;
 236         u32 operand;
 237
 238         if (wq->state != IDXD_WQ_ENABLED) {
 239                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 240                 return;
 241         }
 242
 243         dev_dbg(dev, "Draining WQ %d\n", wq->id);
 244         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 245         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL);
 246 }
 247
 248 void idxd_wq_reset(struct idxd_wq *wq)
 249 {
 250         struct idxd_device *idxd = wq->idxd;
 251         struct device *dev = &idxd->pdev->dev;
 252         u32 operand;
 253
 254         if (wq->state != IDXD_WQ_ENABLED) {
 255                 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state);
 256                 return;
 257         }
 258
 259         operand = BIT(wq->id % 16) | ((wq->id / 16) << 16);
 260         idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL);
 261         idxd_wq_disable_cleanup(wq);
 262 }
 263
 264 int idxd_wq_map_portal(struct idxd_wq *wq)
 265 {
 266         struct idxd_device *idxd = wq->idxd;
 267         struct pci_dev *pdev = idxd->pdev;
 268         struct device *dev = &pdev->dev;
 269         resource_size_t start;
 270
 271         start = pci_resource_start(pdev, IDXD_WQ_BAR);
 272         start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED);
 273
 274         wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE);
 275         if (!wq->portal)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 void idxd_wq_unmap_portal(struct idxd_wq *wq)
 282 {
 283         struct device *dev = &wq->idxd->pdev->dev;
 284
 285         devm_iounmap(dev, wq->portal);
 286         wq->portal = NULL;
 287         wq->portal_offset = 0;
 288 }
 289
 290 void idxd_wqs_unmap_portal(struct idxd_device *idxd)
 291 {
 292         int i;
 293
 294         for (i = 0; i < idxd->max_wqs; i++) {
 295                 struct idxd_wq *wq = idxd->wqs[i];
 296
 297                 if (wq->portal)
 298                         idxd_wq_unmap_portal(wq);
 299         }
 300 }
 301
 302 static void __idxd_wq_set_priv_locked(struct idxd_wq *wq, int priv)
 303 {
 304         struct idxd_device *idxd = wq->idxd;
 305         union wqcfg wqcfg;
 306         unsigned int offset;
 307
 308         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PRIVL_IDX);
 309         spin_lock(&idxd->dev_lock);
 310         wqcfg.bits[WQCFG_PRIVL_IDX] = ioread32(idxd->reg_base + offset);
 311         wqcfg.priv = priv;
 312         wq->wqcfg->bits[WQCFG_PRIVL_IDX] = wqcfg.bits[WQCFG_PRIVL_IDX];
 313         iowrite32(wqcfg.bits[WQCFG_PRIVL_IDX], idxd->reg_base + offset);
 314         spin_unlock(&idxd->dev_lock);
 315 }
 316
 317 static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid)
 318 {
 319         struct idxd_device *idxd = wq->idxd;
 320         union wqcfg wqcfg;
 321         unsigned int offset;
 322
 323         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 324         spin_lock(&idxd->dev_lock);
 325         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 326         wqcfg.pasid_en = 1;
 327         wqcfg.pasid = pasid;
 328         wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX];
 329         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 330         spin_unlock(&idxd->dev_lock);
 331 }
 332
 333 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid)
 334 {
 335         int rc;
 336
 337         rc = idxd_wq_disable(wq, false);
 338         if (rc < 0)
 339                 return rc;
 340
 341         __idxd_wq_set_pasid_locked(wq, pasid);
 342
 343         rc = idxd_wq_enable(wq);
 344         if (rc < 0)
 345                 return rc;
 346
 347         return 0;
 348 }
 349
 350 int idxd_wq_disable_pasid(struct idxd_wq *wq)
 351 {
 352         struct idxd_device *idxd = wq->idxd;
 353         int rc;
 354         union wqcfg wqcfg;
 355         unsigned int offset;
 356
 357         rc = idxd_wq_disable(wq, false);
 358         if (rc < 0)
 359                 return rc;
 360
 361         offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX);
 362         spin_lock(&idxd->dev_lock);
 363         wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
 364         wqcfg.pasid_en = 0;
 365         wqcfg.pasid = 0;
 366         iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
 367         spin_unlock(&idxd->dev_lock);
 368
 369         rc = idxd_wq_enable(wq);
 370         if (rc < 0)
 371                 return rc;
 372
 373         return 0;
 374 }
 375
 376 static void idxd_wq_disable_cleanup(struct idxd_wq *wq)
 377 {
 378         struct idxd_device *idxd = wq->idxd;
 379
 380         lockdep_assert_held(&wq->wq_lock);
 381         wq->state = IDXD_WQ_DISABLED;
 382         memset(wq->wqcfg, 0, idxd->wqcfg_size);
 383         wq->type = IDXD_WQT_NONE;
 384         wq->threshold = 0;
 385         wq->priority = 0;
 386         wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
 387         clear_bit(WQ_FLAG_DEDICATED, &wq->flags);
 388         clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags);
 389         clear_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);
 390         memset(wq->name, 0, WQ_NAME_SIZE);
 391         wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
 392         idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
 393         if (wq->opcap_bmap)
 394                 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
 395 }
 396
 397 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq)
 398 {
 399         lockdep_assert_held(&wq->wq_lock);
 400
 401         wq->size = 0;
 402         wq->group = NULL;
 403 }
 404
 405 static void idxd_wq_ref_release(struct percpu_ref *ref)
 406 {
 407         struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active);
 408
 409         complete(&wq->wq_dead);
 410 }
 411
 412 int idxd_wq_init_percpu_ref(struct idxd_wq *wq)
 413 {
 414         int rc;
 415
 416         memset(&wq->wq_active, 0, sizeof(wq->wq_active));
 417         rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release,
 418                              PERCPU_REF_ALLOW_REINIT, GFP_KERNEL);
 419         if (rc < 0)
 420                 return rc;
 421         reinit_completion(&wq->wq_dead);
 422         reinit_completion(&wq->wq_resurrect);
 423         return 0;
 424 }
 425
 426 void __idxd_wq_quiesce(struct idxd_wq *wq)
 427 {
 428         lockdep_assert_held(&wq->wq_lock);
 429         reinit_completion(&wq->wq_resurrect);
 430         percpu_ref_kill(&wq->wq_active);
 431         complete_all(&wq->wq_resurrect);
 432         wait_for_completion(&wq->wq_dead);
 433 }
 434
 435 void idxd_wq_quiesce(struct idxd_wq *wq)
 436 {
 437         mutex_lock(&wq->wq_lock);
 438         __idxd_wq_quiesce(wq);
 439         mutex_unlock(&wq->wq_lock);
 440 }
 441
 442 /* Device control bits */
 443 static inline bool idxd_is_enabled(struct idxd_device *idxd)
 444 {
 445         union gensts_reg gensts;
 446
 447         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 448
 449         if (gensts.state == IDXD_DEVICE_STATE_ENABLED)
 450                 return true;
 451         return false;
 452 }
 453
 454 static inline bool idxd_device_is_halted(struct idxd_device *idxd)
 455 {
 456         union gensts_reg gensts;
 457
 458         gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
 459
 460         return (gensts.state == IDXD_DEVICE_STATE_HALT);
 461 }
 462
 463 /*
 464  * This is function is only used for reset during probe and will
 465  * poll for completion. Once the device is setup with interrupts,
 466  * all commands will be done via interrupt completion.
 467  */
 468 int idxd_device_init_reset(struct idxd_device *idxd)
 469 {
 470         struct device *dev = &idxd->pdev->dev;
 471         union idxd_command_reg cmd;
 472
 473         if (idxd_device_is_halted(idxd)) {
 474                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 475                 return -ENXIO;
 476         }
 477
 478         memset(&cmd, 0, sizeof(cmd));
 479         cmd.cmd = IDXD_CMD_RESET_DEVICE;
 480         dev_dbg(dev, "%s: sending reset for init.\n", __func__);
 481         spin_lock(&idxd->cmd_lock);
 482         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 483
 484         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) &
 485                IDXD_CMDSTS_ACTIVE)
 486                 cpu_relax();
 487         spin_unlock(&idxd->cmd_lock);
 488         return 0;
 489 }
 490
 491 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand,
 492                           u32 *status)
 493 {
 494         union idxd_command_reg cmd;
 495         DECLARE_COMPLETION_ONSTACK(done);
 496         u32 stat;
 497
 498         if (idxd_device_is_halted(idxd)) {
 499                 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n");
 500                 if (status)
 501                         *status = IDXD_CMDSTS_HW_ERR;
 502                 return;
 503         }
 504
 505         memset(&cmd, 0, sizeof(cmd));
 506         cmd.cmd = cmd_code;
 507         cmd.operand = operand;
 508         cmd.int_req = 1;
 509
 510         spin_lock(&idxd->cmd_lock);
 511         wait_event_lock_irq(idxd->cmd_waitq,
 512                             !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags),
 513                             idxd->cmd_lock);
 514
 515         dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n",
 516                 __func__, cmd_code, operand);
 517
 518         idxd->cmd_status = 0;
 519         __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 520         idxd->cmd_done = &done;
 521         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 522
 523         /*
 524          * After command submitted, release lock and go to sleep until
 525          * the command completes via interrupt.
 526          */
 527         spin_unlock(&idxd->cmd_lock);
 528         wait_for_completion(&done);
 529         stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 530         spin_lock(&idxd->cmd_lock);
 531         if (status)
 532                 *status = stat;
 533         idxd->cmd_status = stat & GENMASK(7, 0);
 534
 535         __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags);
 536         /* Wake up other pending commands */
 537         wake_up(&idxd->cmd_waitq);
 538         spin_unlock(&idxd->cmd_lock);
 539 }
 540
 541 int idxd_device_enable(struct idxd_device *idxd)
 542 {
 543         struct device *dev = &idxd->pdev->dev;
 544         u32 status;
 545
 546         if (idxd_is_enabled(idxd)) {
 547                 dev_dbg(dev, "Device already enabled\n");
 548                 return -ENXIO;
 549         }
 550
 551         idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status);
 552
 553         /* If the command is successful or if the device was enabled */
 554         if (status != IDXD_CMDSTS_SUCCESS &&
 555             status != IDXD_CMDSTS_ERR_DEV_ENABLED) {
 556                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 557                 return -ENXIO;
 558         }
 559
 560         idxd->state = IDXD_DEV_ENABLED;
 561         return 0;
 562 }
 563
 564 int idxd_device_disable(struct idxd_device *idxd)
 565 {
 566         struct device *dev = &idxd->pdev->dev;
 567         u32 status;
 568
 569         if (!idxd_is_enabled(idxd)) {
 570                 dev_dbg(dev, "Device is not enabled\n");
 571                 return 0;
 572         }
 573
 574         idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status);
 575
 576         /* If the command is successful or if the device was disabled */
 577         if (status != IDXD_CMDSTS_SUCCESS &&
 578             !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) {
 579                 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status);
 580                 return -ENXIO;
 581         }
 582
 583         idxd_device_clear_state(idxd);
 584         return 0;
 585 }
 586
 587 void idxd_device_reset(struct idxd_device *idxd)
 588 {
 589         idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
 590         idxd_device_clear_state(idxd);
 591         spin_lock(&idxd->dev_lock);
 592         idxd_unmask_error_interrupts(idxd);
 593         spin_unlock(&idxd->dev_lock);
 594 }
 595
 596 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid)
 597 {
 598         struct device *dev = &idxd->pdev->dev;
 599         u32 operand;
 600
 601         operand = pasid;
 602         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand);
 603         idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL);
 604         dev_dbg(dev, "pasid %d drained\n", pasid);
 605 }
 606
 607 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
 608                                    enum idxd_interrupt_type irq_type)
 609 {
 610         struct device *dev = &idxd->pdev->dev;
 611         u32 operand, status;
 612
 613         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)))
 614                 return -EOPNOTSUPP;
 615
 616         dev_dbg(dev, "get int handle, idx %d\n", idx);
 617
 618         operand = idx & GENMASK(15, 0);
 619         if (irq_type == IDXD_IRQ_IMS)
 620                 operand |= CMD_INT_HANDLE_IMS;
 621
 622         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand);
 623
 624         idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status);
 625
 626         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 627                 dev_dbg(dev, "request int handle failed: %#x\n", status);
 628                 return -ENXIO;
 629         }
 630
 631         *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0);
 632
 633         dev_dbg(dev, "int handle acquired: %u\n", *handle);
 634         return 0;
 635 }
 636
 637 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
 638                                    enum idxd_interrupt_type irq_type)
 639 {
 640         struct device *dev = &idxd->pdev->dev;
 641         u32 operand, status;
 642         union idxd_command_reg cmd;
 643
 644         if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE)))
 645                 return -EOPNOTSUPP;
 646
 647         dev_dbg(dev, "release int handle, handle %d\n", handle);
 648
 649         memset(&cmd, 0, sizeof(cmd));
 650         operand = handle & GENMASK(15, 0);
 651
 652         if (irq_type == IDXD_IRQ_IMS)
 653                 operand |= CMD_INT_HANDLE_IMS;
 654
 655         cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE;
 656         cmd.operand = operand;
 657
 658         dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand);
 659
 660         spin_lock(&idxd->cmd_lock);
 661         iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET);
 662
 663         while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE)
 664                 cpu_relax();
 665         status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET);
 666         spin_unlock(&idxd->cmd_lock);
 667
 668         if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) {
 669                 dev_dbg(dev, "release int handle failed: %#x\n", status);
 670                 return -ENXIO;
 671         }
 672
 673         dev_dbg(dev, "int handle released.\n");
 674         return 0;
 675 }
 676
 677 /* Device configuration bits */
 678 static void idxd_engines_clear_state(struct idxd_device *idxd)
 679 {
 680         struct idxd_engine *engine;
 681         int i;
 682
 683         lockdep_assert_held(&idxd->dev_lock);
 684         for (i = 0; i < idxd->max_engines; i++) {
 685                 engine = idxd->engines[i];
 686                 engine->group = NULL;
 687         }
 688 }
 689
 690 static void idxd_groups_clear_state(struct idxd_device *idxd)
 691 {
 692         struct idxd_group *group;
 693         int i;
 694
 695         lockdep_assert_held(&idxd->dev_lock);
 696         for (i = 0; i < idxd->max_groups; i++) {
 697                 group = idxd->groups[i];
 698                 memset(&group->grpcfg, 0, sizeof(group->grpcfg));
 699                 group->num_engines = 0;
 700                 group->num_wqs = 0;
 701                 group->use_rdbuf_limit = false;
 702                 /*
 703                  * The default value is the same as the value of
 704                  * total read buffers in GRPCAP.
 705                  */
 706                 group->rdbufs_allowed = idxd->max_rdbufs;
 707                 group->rdbufs_reserved = 0;
 708                 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
 709                         group->tc_a = 1;
 710                         group->tc_b = 1;
 711                 } else {
 712                         group->tc_a = -1;
 713                         group->tc_b = -1;
 714                 }
 715                 group->desc_progress_limit = 0;
 716                 group->batch_progress_limit = 0;
 717         }
 718 }
 719
 720 static void idxd_device_wqs_clear_state(struct idxd_device *idxd)
 721 {
 722         int i;
 723
 724         for (i = 0; i < idxd->max_wqs; i++) {
 725                 struct idxd_wq *wq = idxd->wqs[i];
 726
 727                 mutex_lock(&wq->wq_lock);
 728                 idxd_wq_disable_cleanup(wq);
 729                 idxd_wq_device_reset_cleanup(wq);
 730                 mutex_unlock(&wq->wq_lock);
 731         }
 732 }
 733
 734 void idxd_device_clear_state(struct idxd_device *idxd)
 735 {
 736         /* IDXD is always disabled. Other states are cleared only when IDXD is configurable. */
 737         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
 738                 /*
 739                  * Clearing wq state is protected by wq lock.
 740                  * So no need to be protected by device lock.
 741                  */
 742                 idxd_device_wqs_clear_state(idxd);
 743
 744                 spin_lock(&idxd->dev_lock);
 745                 idxd_groups_clear_state(idxd);
 746                 idxd_engines_clear_state(idxd);
 747         } else {
 748                 spin_lock(&idxd->dev_lock);
 749         }
 750
 751         idxd->state = IDXD_DEV_DISABLED;
 752         spin_unlock(&idxd->dev_lock);
 753 }
 754
 755 static int idxd_device_evl_setup(struct idxd_device *idxd)
 756 {
 757         union gencfg_reg gencfg;
 758         union evlcfg_reg evlcfg;
 759         union genctrl_reg genctrl;
 760         struct device *dev = &idxd->pdev->dev;
 761         void *addr;
 762         dma_addr_t dma_addr;
 763         int size;
 764         struct idxd_evl *evl = idxd->evl;
 765         unsigned long *bmap;
 766         int rc;
 767
 768         if (!evl)
 769                 return 0;
 770
 771         size = evl_size(idxd);
 772
 773         bmap = bitmap_zalloc(size, GFP_KERNEL);
 774         if (!bmap) {
 775                 rc = -ENOMEM;
 776                 goto err_bmap;
 777         }
 778
 779         /*
 780          * Address needs to be page aligned. However, dma_alloc_coherent() provides
 781          * at minimal page size aligned address. No manual alignment required.
 782          */
 783         addr = dma_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
 784         if (!addr) {
 785                 rc = -ENOMEM;
 786                 goto err_alloc;
 787         }
 788
 789         spin_lock(&evl->lock);
 790         evl->log = addr;
 791         evl->dma = dma_addr;
 792         evl->log_size = size;
 793         evl->bmap = bmap;
 794
 795         memset(&evlcfg, 0, sizeof(evlcfg));
 796         evlcfg.bits[0] = dma_addr & GENMASK(63, 12);
 797         evlcfg.size = evl->size;
 798
 799         iowrite64(evlcfg.bits[0], idxd->reg_base + IDXD_EVLCFG_OFFSET);
 800         iowrite64(evlcfg.bits[1], idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
 801
 802         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
 803         genctrl.evl_int_en = 1;
 804         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
 805
 806         gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 807         gencfg.evl_en = 1;
 808         iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 809
 810         spin_unlock(&evl->lock);
 811         return 0;
 812
 813 err_alloc:
 814         bitmap_free(bmap);
 815 err_bmap:
 816         return rc;
 817 }
 818
 819 static void idxd_device_evl_free(struct idxd_device *idxd)
 820 {
 821         union gencfg_reg gencfg;
 822         union genctrl_reg genctrl;
 823         struct device *dev = &idxd->pdev->dev;
 824         struct idxd_evl *evl = idxd->evl;
 825
 826         gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 827         if (!gencfg.evl_en)
 828                 return;
 829
 830         spin_lock(&evl->lock);
 831         gencfg.evl_en = 0;
 832         iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 833
 834         genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
 835         genctrl.evl_int_en = 0;
 836         iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
 837
 838         iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET);
 839         iowrite64(0, idxd->reg_base + IDXD_EVLCFG_OFFSET + 8);
 840
 841         dma_free_coherent(dev, evl->log_size, evl->log, evl->dma);
 842         bitmap_free(evl->bmap);
 843         evl->log = NULL;
 844         evl->size = IDXD_EVL_SIZE_MIN;
 845         spin_unlock(&evl->lock);
 846 }
 847
 848 static void idxd_group_config_write(struct idxd_group *group)
 849 {
 850         struct idxd_device *idxd = group->idxd;
 851         struct device *dev = &idxd->pdev->dev;
 852         int i;
 853         u32 grpcfg_offset;
 854
 855         dev_dbg(dev, "Writing group %d cfg registers\n", group->id);
 856
 857         /* setup GRPWQCFG */
 858         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
 859                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
 860                 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset);
 861                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
 862                         group->id, i, grpcfg_offset,
 863                         ioread64(idxd->reg_base + grpcfg_offset));
 864         }
 865
 866         /* setup GRPENGCFG */
 867         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
 868         iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset);
 869         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
 870                 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset));
 871
 872         /* setup GRPFLAGS */
 873         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
 874         iowrite64(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset);
 875         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n",
 876                 group->id, grpcfg_offset,
 877                 ioread64(idxd->reg_base + grpcfg_offset));
 878 }
 879
 880 static int idxd_groups_config_write(struct idxd_device *idxd)
 881
 882 {
 883         union gencfg_reg reg;
 884         int i;
 885         struct device *dev = &idxd->pdev->dev;
 886
 887         /* Setup bandwidth rdbuf limit */
 888         if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) {
 889                 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
 890                 reg.rdbuf_limit = idxd->rdbuf_limit;
 891                 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
 892         }
 893
 894         dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET,
 895                 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET));
 896
 897         for (i = 0; i < idxd->max_groups; i++) {
 898                 struct idxd_group *group = idxd->groups[i];
 899
 900                 idxd_group_config_write(group);
 901         }
 902
 903         return 0;
 904 }
 905
 906 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd)
 907 {
 908         struct pci_dev *pdev = idxd->pdev;
 909
 910         if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV))
 911                 return true;
 912         return false;
 913 }
 914
 915 static int idxd_wq_config_write(struct idxd_wq *wq)
 916 {
 917         struct idxd_device *idxd = wq->idxd;
 918         struct device *dev = &idxd->pdev->dev;
 919         u32 wq_offset;
 920         int i, n;
 921
 922         if (!wq->group)
 923                 return 0;
 924
 925         /*
 926          * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after
 927          * wq reset. This will copy back the sticky values that are present on some devices.
 928          */
 929         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 930                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 931                 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset);
 932         }
 933
 934         if (wq->size == 0 && wq->type != IDXD_WQT_NONE)
 935                 wq->size = WQ_DEFAULT_QUEUE_DEPTH;
 936
 937         /* byte 0-3 */
 938         wq->wqcfg->wq_size = wq->size;
 939
 940         /* bytes 4-7 */
 941         wq->wqcfg->wq_thresh = wq->threshold;
 942
 943         /* byte 8-11 */
 944         if (wq_dedicated(wq))
 945                 wq->wqcfg->mode = 1;
 946
 947         /*
 948          * The WQ priv bit is set depending on the WQ type. priv = 1 if the
 949          * WQ type is kernel to indicate privileged access. This setting only
 950          * matters for dedicated WQ. According to the DSA spec:
 951          * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the
 952          * Privileged Mode Enable field of the PCI Express PASID capability
 953          * is 0, this field must be 0.
 954          *
 955          * In the case of a dedicated kernel WQ that is not able to support
 956          * the PASID cap, then the configuration will be rejected.
 957          */
 958         if (wq_dedicated(wq) && wq->wqcfg->pasid_en &&
 959             !idxd_device_pasid_priv_enabled(idxd) &&
 960             wq->type == IDXD_WQT_KERNEL) {
 961                 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV;
 962                 return -EOPNOTSUPP;
 963         }
 964
 965         wq->wqcfg->priority = wq->priority;
 966
 967         if (idxd->hw.gen_cap.block_on_fault &&
 968             test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags) &&
 969             !test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags))
 970                 wq->wqcfg->bof = 1;
 971
 972         if (idxd->hw.wq_cap.wq_ats_support)
 973                 wq->wqcfg->wq_ats_disable = test_bit(WQ_FLAG_ATS_DISABLE, &wq->flags);
 974
 975         if (idxd->hw.wq_cap.wq_prs_support)
 976                 wq->wqcfg->wq_prs_disable = test_bit(WQ_FLAG_PRS_DISABLE, &wq->flags);
 977
 978         /* bytes 12-15 */
 979         wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes);
 980         idxd_wqcfg_set_max_batch_shift(idxd->data->type, wq->wqcfg, ilog2(wq->max_batch_size));
 981
 982         /* bytes 32-63 */
 983         if (idxd->hw.wq_cap.op_config && wq->opcap_bmap) {
 984                 memset(wq->wqcfg->op_config, 0, IDXD_MAX_OPCAP_BITS / 8);
 985                 for_each_set_bit(n, wq->opcap_bmap, IDXD_MAX_OPCAP_BITS) {
 986                         int pos = n % BITS_PER_LONG_LONG;
 987                         int idx = n / BITS_PER_LONG_LONG;
 988
 989                         wq->wqcfg->op_config[idx] |= BIT(pos);
 990                 }
 991         }
 992
 993         dev_dbg(dev, "WQ %d CFGs\n", wq->id);
 994         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
 995                 wq_offset = WQCFG_OFFSET(idxd, wq->id, i);
 996                 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset);
 997                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n",
 998                         wq->id, i, wq_offset,
 999                         ioread32(idxd->reg_base + wq_offset));
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int idxd_wqs_config_write(struct idxd_device *idxd)
1006 {
1007         int i, rc;
1008
1009         for (i = 0; i < idxd->max_wqs; i++) {
1010                 struct idxd_wq *wq = idxd->wqs[i];
1011
1012                 rc = idxd_wq_config_write(wq);
1013                 if (rc < 0)
1014                         return rc;
1015         }
1016
1017         return 0;
1018 }
1019
1020 static void idxd_group_flags_setup(struct idxd_device *idxd)
1021 {
1022         int i;
1023
1024         /* TC-A 0 and TC-B 1 should be defaults */
1025         for (i = 0; i < idxd->max_groups; i++) {
1026                 struct idxd_group *group = idxd->groups[i];
1027
1028                 if (group->tc_a == -1)
1029                         group->tc_a = group->grpcfg.flags.tc_a = 0;
1030                 else
1031                         group->grpcfg.flags.tc_a = group->tc_a;
1032                 if (group->tc_b == -1)
1033                         group->tc_b = group->grpcfg.flags.tc_b = 1;
1034                 else
1035                         group->grpcfg.flags.tc_b = group->tc_b;
1036                 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
1037                 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
1038                 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
1039                 group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit;
1040                 group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit;
1041         }
1042 }
1043
1044 static int idxd_engines_setup(struct idxd_device *idxd)
1045 {
1046         int i, engines = 0;
1047         struct idxd_engine *eng;
1048         struct idxd_group *group;
1049
1050         for (i = 0; i < idxd->max_groups; i++) {
1051                 group = idxd->groups[i];
1052                 group->grpcfg.engines = 0;
1053         }
1054
1055         for (i = 0; i < idxd->max_engines; i++) {
1056                 eng = idxd->engines[i];
1057                 group = eng->group;
1058
1059                 if (!group)
1060                         continue;
1061
1062                 group->grpcfg.engines |= BIT(eng->id);
1063                 engines++;
1064         }
1065
1066         if (!engines)
1067                 return -EINVAL;
1068
1069         return 0;
1070 }
1071
1072 static int idxd_wqs_setup(struct idxd_device *idxd)
1073 {
1074         struct idxd_wq *wq;
1075         struct idxd_group *group;
1076         int i, j, configured = 0;
1077         struct device *dev = &idxd->pdev->dev;
1078
1079         for (i = 0; i < idxd->max_groups; i++) {
1080                 group = idxd->groups[i];
1081                 for (j = 0; j < 4; j++)
1082                         group->grpcfg.wqs[j] = 0;
1083         }
1084
1085         for (i = 0; i < idxd->max_wqs; i++) {
1086                 wq = idxd->wqs[i];
1087                 group = wq->group;
1088
1089                 if (!wq->group)
1090                         continue;
1091
1092                 if (wq_shared(wq) && !wq_shared_supported(wq)) {
1093                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT;
1094                         dev_warn(dev, "No shared wq support but configured.\n");
1095                         return -EINVAL;
1096                 }
1097
1098                 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64);
1099                 configured++;
1100         }
1101
1102         if (configured == 0) {
1103                 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED;
1104                 return -EINVAL;
1105         }
1106
1107         return 0;
1108 }
1109
1110 int idxd_device_config(struct idxd_device *idxd)
1111 {
1112         int rc;
1113
1114         lockdep_assert_held(&idxd->dev_lock);
1115         rc = idxd_wqs_setup(idxd);
1116         if (rc < 0)
1117                 return rc;
1118
1119         rc = idxd_engines_setup(idxd);
1120         if (rc < 0)
1121                 return rc;
1122
1123         idxd_group_flags_setup(idxd);
1124
1125         rc = idxd_wqs_config_write(idxd);
1126         if (rc < 0)
1127                 return rc;
1128
1129         rc = idxd_groups_config_write(idxd);
1130         if (rc < 0)
1131                 return rc;
1132
1133         return 0;
1134 }
1135
1136 static int idxd_wq_load_config(struct idxd_wq *wq)
1137 {
1138         struct idxd_device *idxd = wq->idxd;
1139         struct device *dev = &idxd->pdev->dev;
1140         int wqcfg_offset;
1141         int i;
1142
1143         wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0);
1144         memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size);
1145
1146         wq->size = wq->wqcfg->wq_size;
1147         wq->threshold = wq->wqcfg->wq_thresh;
1148
1149         /* The driver does not support shared WQ mode in read-only config yet */
1150         if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en)
1151                 return -EOPNOTSUPP;
1152
1153         set_bit(WQ_FLAG_DEDICATED, &wq->flags);
1154
1155         wq->priority = wq->wqcfg->priority;
1156
1157         wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift;
1158         idxd_wq_set_max_batch_size(idxd->data->type, wq, 1U << wq->wqcfg->max_batch_shift);
1159
1160         for (i = 0; i < WQCFG_STRIDES(idxd); i++) {
1161                 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i);
1162                 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]);
1163         }
1164
1165         return 0;
1166 }
1167
1168 static void idxd_group_load_config(struct idxd_group *group)
1169 {
1170         struct idxd_device *idxd = group->idxd;
1171         struct device *dev = &idxd->pdev->dev;
1172         int i, j, grpcfg_offset;
1173
1174         /*
1175          * Load WQS bit fields
1176          * Iterate through all 256 bits 64 bits at a time
1177          */
1178         for (i = 0; i < GRPWQCFG_STRIDES; i++) {
1179                 struct idxd_wq *wq;
1180
1181                 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i);
1182                 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset);
1183                 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n",
1184                         group->id, i, grpcfg_offset, group->grpcfg.wqs[i]);
1185
1186                 if (i * 64 >= idxd->max_wqs)
1187                         break;
1188
1189                 /* Iterate through all 64 bits and check for wq set */
1190                 for (j = 0; j < 64; j++) {
1191                         int id = i * 64 + j;
1192
1193                         /* No need to check beyond max wqs */
1194                         if (id >= idxd->max_wqs)
1195                                 break;
1196
1197                         /* Set group assignment for wq if wq bit is set */
1198                         if (group->grpcfg.wqs[i] & BIT(j)) {
1199                                 wq = idxd->wqs[id];
1200                                 wq->group = group;
1201                         }
1202                 }
1203         }
1204
1205         grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id);
1206         group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset);
1207         dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id,
1208                 grpcfg_offset, group->grpcfg.engines);
1209
1210         /* Iterate through all 64 bits to check engines set */
1211         for (i = 0; i < 64; i++) {
1212                 if (i >= idxd->max_engines)
1213                         break;
1214
1215                 if (group->grpcfg.engines & BIT(i)) {
1216                         struct idxd_engine *engine = idxd->engines[i];
1217
1218                         engine->group = group;
1219                 }
1220         }
1221
1222         grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id);
1223         group->grpcfg.flags.bits = ioread64(idxd->reg_base + grpcfg_offset);
1224         dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#llx\n",
1225                 group->id, grpcfg_offset, group->grpcfg.flags.bits);
1226 }
1227
1228 int idxd_device_load_config(struct idxd_device *idxd)
1229 {
1230         union gencfg_reg reg;
1231         int i, rc;
1232
1233         reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
1234         idxd->rdbuf_limit = reg.rdbuf_limit;
1235
1236         for (i = 0; i < idxd->max_groups; i++) {
1237                 struct idxd_group *group = idxd->groups[i];
1238
1239                 idxd_group_load_config(group);
1240         }
1241
1242         for (i = 0; i < idxd->max_wqs; i++) {
1243                 struct idxd_wq *wq = idxd->wqs[i];
1244
1245                 rc = idxd_wq_load_config(wq);
1246                 if (rc < 0)
1247                         return rc;
1248         }
1249
1250         return 0;
1251 }
1252
1253 static void idxd_flush_pending_descs(struct idxd_irq_entry *ie)
1254 {
1255         struct idxd_desc *desc, *itr;
1256         struct llist_node *head;
1257         LIST_HEAD(flist);
1258         enum idxd_complete_type ctype;
1259
1260         spin_lock(&ie->list_lock);
1261         head = llist_del_all(&ie->pending_llist);
1262         if (head) {
1263                 llist_for_each_entry_safe(desc, itr, head, llnode)
1264                         list_add_tail(&desc->list, &ie->work_list);
1265         }
1266
1267         list_for_each_entry_safe(desc, itr, &ie->work_list, list)
1268                 list_move_tail(&desc->list, &flist);
1269         spin_unlock(&ie->list_lock);
1270
1271         list_for_each_entry_safe(desc, itr, &flist, list) {
1272                 struct dma_async_tx_descriptor *tx;
1273
1274                 list_del(&desc->list);
1275                 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT;
1276                 /*
1277                  * wq is being disabled. Any remaining descriptors are
1278                  * likely to be stuck and can be dropped. callback could
1279                  * point to code that is no longer accessible, for example
1280                  * if dmatest module has been unloaded.
1281                  */
1282                 tx = &desc->txd;
1283                 tx->callback = NULL;
1284                 tx->callback_result = NULL;
1285                 idxd_dma_complete_txd(desc, ctype, true);
1286         }
1287 }
1288
1289 static void idxd_device_set_perm_entry(struct idxd_device *idxd,
1290                                        struct idxd_irq_entry *ie)
1291 {
1292         union msix_perm mperm;
1293
1294         if (ie->pasid == IOMMU_PASID_INVALID)
1295                 return;
1296
1297         mperm.bits = 0;
1298         mperm.pasid = ie->pasid;
1299         mperm.pasid_en = 1;
1300         iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1301 }
1302
1303 static void idxd_device_clear_perm_entry(struct idxd_device *idxd,
1304                                          struct idxd_irq_entry *ie)
1305 {
1306         iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8);
1307 }
1308
1309 void idxd_wq_free_irq(struct idxd_wq *wq)
1310 {
1311         struct idxd_device *idxd = wq->idxd;
1312         struct idxd_irq_entry *ie = &wq->ie;
1313
1314         if (wq->type != IDXD_WQT_KERNEL)
1315                 return;
1316
1317         free_irq(ie->vector, ie);
1318         idxd_flush_pending_descs(ie);
1319         if (idxd->request_int_handles)
1320                 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1321         idxd_device_clear_perm_entry(idxd, ie);
1322         ie->vector = -1;
1323         ie->int_handle = INVALID_INT_HANDLE;
1324         ie->pasid = IOMMU_PASID_INVALID;
1325 }
1326
1327 int idxd_wq_request_irq(struct idxd_wq *wq)
1328 {
1329         struct idxd_device *idxd = wq->idxd;
1330         struct pci_dev *pdev = idxd->pdev;
1331         struct device *dev = &pdev->dev;
1332         struct idxd_irq_entry *ie;
1333         int rc;
1334
1335         if (wq->type != IDXD_WQT_KERNEL)
1336                 return 0;
1337
1338         ie = &wq->ie;
1339         ie->vector = pci_irq_vector(pdev, ie->id);
1340         ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : IOMMU_PASID_INVALID;
1341         idxd_device_set_perm_entry(idxd, ie);
1342
1343         rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie);
1344         if (rc < 0) {
1345                 dev_err(dev, "Failed to request irq %d.\n", ie->vector);
1346                 goto err_irq;
1347         }
1348
1349         if (idxd->request_int_handles) {
1350                 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle,
1351                                                     IDXD_IRQ_MSIX);
1352                 if (rc < 0)
1353                         goto err_int_handle;
1354         } else {
1355                 ie->int_handle = ie->id;
1356         }
1357
1358         return 0;
1359
1360 err_int_handle:
1361         ie->int_handle = INVALID_INT_HANDLE;
1362         free_irq(ie->vector, ie);
1363 err_irq:
1364         idxd_device_clear_perm_entry(idxd, ie);
1365         ie->pasid = IOMMU_PASID_INVALID;
1366         return rc;
1367 }
1368
1369 int drv_enable_wq(struct idxd_wq *wq)
1370 {
1371         struct idxd_device *idxd = wq->idxd;
1372         struct device *dev = &idxd->pdev->dev;
1373         int rc = -ENXIO;
1374
1375         lockdep_assert_held(&wq->wq_lock);
1376
1377         if (idxd->state != IDXD_DEV_ENABLED) {
1378                 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED;
1379                 goto err;
1380         }
1381
1382         if (wq->state != IDXD_WQ_DISABLED) {
1383                 dev_dbg(dev, "wq %d already enabled.\n", wq->id);
1384                 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED;
1385                 rc = -EBUSY;
1386                 goto err;
1387         }
1388
1389         if (!wq->group) {
1390                 dev_dbg(dev, "wq %d not attached to group.\n", wq->id);
1391                 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP;
1392                 goto err;
1393         }
1394
1395         if (strlen(wq->name) == 0) {
1396                 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME;
1397                 dev_dbg(dev, "wq %d name not set.\n", wq->id);
1398                 goto err;
1399         }
1400
1401         /* Shared WQ checks */
1402         if (wq_shared(wq)) {
1403                 if (!wq_shared_supported(wq)) {
1404                         idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM;
1405                         dev_dbg(dev, "PASID not enabled and shared wq.\n");
1406                         goto err;
1407                 }
1408                 /*
1409                  * Shared wq with the threshold set to 0 means the user
1410                  * did not set the threshold or transitioned from a
1411                  * dedicated wq but did not set threshold. A value
1412                  * of 0 would effectively disable the shared wq. The
1413                  * driver does not allow a value of 0 to be set for
1414                  * threshold via sysfs.
1415                  */
1416                 if (wq->threshold == 0) {
1417                         idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH;
1418                         dev_dbg(dev, "Shared wq and threshold 0.\n");
1419                         goto err;
1420                 }
1421         }
1422
1423         /*
1424          * In the event that the WQ is configurable for pasid and priv bits.
1425          * For kernel wq, the driver should setup the pasid, pasid_en, and priv bit.
1426          * However, for non-kernel wq, the driver should only set the pasid_en bit for
1427          * shared wq. A dedicated wq that is not 'kernel' type will configure pasid and
1428          * pasid_en later on so there is no need to setup.
1429          */
1430         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
1431                 int priv = 0;
1432
1433                 if (wq_pasid_enabled(wq)) {
1434                         if (is_idxd_wq_kernel(wq) || wq_shared(wq)) {
1435                                 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0;
1436
1437                                 __idxd_wq_set_pasid_locked(wq, pasid);
1438                         }
1439                 }
1440
1441                 if (is_idxd_wq_kernel(wq))
1442                         priv = 1;
1443                 __idxd_wq_set_priv_locked(wq, priv);
1444         }
1445
1446         rc = 0;
1447         spin_lock(&idxd->dev_lock);
1448         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1449                 rc = idxd_device_config(idxd);
1450         spin_unlock(&idxd->dev_lock);
1451         if (rc < 0) {
1452                 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1453                 goto err;
1454         }
1455
1456         rc = idxd_wq_enable(wq);
1457         if (rc < 0) {
1458                 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc);
1459                 goto err;
1460         }
1461
1462         rc = idxd_wq_map_portal(wq);
1463         if (rc < 0) {
1464                 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR;
1465                 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc);
1466                 goto err_map_portal;
1467         }
1468
1469         wq->client_count = 0;
1470
1471         rc = idxd_wq_request_irq(wq);
1472         if (rc < 0) {
1473                 idxd->cmd_status = IDXD_SCMD_WQ_IRQ_ERR;
1474                 dev_dbg(dev, "WQ %d irq setup failed: %d\n", wq->id, rc);
1475                 goto err_irq;
1476         }
1477
1478         rc = idxd_wq_alloc_resources(wq);
1479         if (rc < 0) {
1480                 idxd->cmd_status = IDXD_SCMD_WQ_RES_ALLOC_ERR;
1481                 dev_dbg(dev, "WQ resource alloc failed\n");
1482                 goto err_res_alloc;
1483         }
1484
1485         rc = idxd_wq_init_percpu_ref(wq);
1486         if (rc < 0) {
1487                 idxd->cmd_status = IDXD_SCMD_PERCPU_ERR;
1488                 dev_dbg(dev, "percpu_ref setup failed\n");
1489                 goto err_ref;
1490         }
1491
1492         return 0;
1493
1494 err_ref:
1495         idxd_wq_free_resources(wq);
1496 err_res_alloc:
1497         idxd_wq_free_irq(wq);
1498 err_irq:
1499         idxd_wq_unmap_portal(wq);
1500 err_map_portal:
1501         if (idxd_wq_disable(wq, false))
1502                 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq)));
1503 err:
1504         return rc;
1505 }
1506
1507 void drv_disable_wq(struct idxd_wq *wq)
1508 {
1509         struct idxd_device *idxd = wq->idxd;
1510         struct device *dev = &idxd->pdev->dev;
1511
1512         lockdep_assert_held(&wq->wq_lock);
1513
1514         if (idxd_wq_refcount(wq))
1515                 dev_warn(dev, "Clients has claim on wq %d: %d\n",
1516                          wq->id, idxd_wq_refcount(wq));
1517
1518         idxd_wq_unmap_portal(wq);
1519         idxd_wq_drain(wq);
1520         idxd_wq_free_irq(wq);
1521         idxd_wq_reset(wq);
1522         idxd_wq_free_resources(wq);
1523         percpu_ref_exit(&wq->wq_active);
1524         wq->type = IDXD_WQT_NONE;
1525         wq->client_count = 0;
1526 }
1527
1528 int idxd_device_drv_probe(struct idxd_dev *idxd_dev)
1529 {
1530         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1531         int rc = 0;
1532
1533         /*
1534          * Device should be in disabled state for the idxd_drv to load. If it's in
1535          * enabled state, then the device was altered outside of driver's control.
1536          * If the state is in halted state, then we don't want to proceed.
1537          */
1538         if (idxd->state != IDXD_DEV_DISABLED) {
1539                 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED;
1540                 return -ENXIO;
1541         }
1542
1543         /* Device configuration */
1544         spin_lock(&idxd->dev_lock);
1545         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1546                 rc = idxd_device_config(idxd);
1547         spin_unlock(&idxd->dev_lock);
1548         if (rc < 0)
1549                 return -ENXIO;
1550
1551         rc = idxd_device_evl_setup(idxd);
1552         if (rc < 0) {
1553                 idxd->cmd_status = IDXD_SCMD_DEV_EVL_ERR;
1554                 return rc;
1555         }
1556
1557         /* Start device */
1558         rc = idxd_device_enable(idxd);
1559         if (rc < 0) {
1560                 idxd_device_evl_free(idxd);
1561                 return rc;
1562         }
1563
1564         /* Setup DMA device without channels */
1565         rc = idxd_register_dma_device(idxd);
1566         if (rc < 0) {
1567                 idxd_device_disable(idxd);
1568                 idxd_device_evl_free(idxd);
1569                 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR;
1570                 return rc;
1571         }
1572
1573         idxd->cmd_status = 0;
1574         return 0;
1575 }
1576
1577 void idxd_device_drv_remove(struct idxd_dev *idxd_dev)
1578 {
1579         struct device *dev = &idxd_dev->conf_dev;
1580         struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev);
1581         int i;
1582
1583         for (i = 0; i < idxd->max_wqs; i++) {
1584                 struct idxd_wq *wq = idxd->wqs[i];
1585                 struct device *wq_dev = wq_confdev(wq);
1586
1587                 if (wq->state == IDXD_WQ_DISABLED)
1588                         continue;
1589                 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev));
1590                 device_release_driver(wq_dev);
1591         }
1592
1593         idxd_unregister_dma_device(idxd);
1594         idxd_device_disable(idxd);
1595         if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1596                 idxd_device_reset(idxd);
1597         idxd_device_evl_free(idxd);
1598 }
1599
1600 static enum idxd_dev_type dev_types[] = {
1601         IDXD_DEV_DSA,
1602         IDXD_DEV_IAX,
1603         IDXD_DEV_NONE,
1604 };
1605
1606 struct idxd_device_driver idxd_drv = {
1607         .type = dev_types,
1608         .probe = idxd_device_drv_probe,
1609         .remove = idxd_device_drv_remove,
1610         .name = "idxd",
1611 };
1612 EXPORT_SYMBOL_GPL(idxd_drv);