drivers/dma/fsl-edma-main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * drivers/dma/fsl-edma.c
   4  *
   5  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   6  *
   7  * Driver for the Freescale eDMA engine with flexible channel multiplexing
   8  * capability for DMA request sources. The eDMA block can be found on some
   9  * Vybrid and Layerscape SoCs.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/clk.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_dma.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/pm_domain.h>
  23
  24 #include "fsl-edma-common.h"
  25
  26 #define ARGS_RX                         BIT(0)
  27 #define ARGS_REMOTE                     BIT(1)
  28 #define ARGS_MULTI_FIFO                 BIT(2)
  29
  30 static void fsl_edma_synchronize(struct dma_chan *chan)
  31 {
  32         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
  33
  34         vchan_synchronize(&fsl_chan->vchan);
  35 }
  36
  37 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
  38 {
  39         struct fsl_edma_engine *fsl_edma = dev_id;
  40         unsigned int intr, ch;
  41         struct edma_regs *regs = &fsl_edma->regs;
  42
  43         intr = edma_readl(fsl_edma, regs->intl);
  44         if (!intr)
  45                 return IRQ_NONE;
  46
  47         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  48                 if (intr & (0x1 << ch)) {
  49                         edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
  50                         fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
  51                 }
  52         }
  53         return IRQ_HANDLED;
  54 }
  55
  56 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
  57 {
  58         struct fsl_edma_chan *fsl_chan = dev_id;
  59         unsigned int intr;
  60
  61         intr = edma_readl_chreg(fsl_chan, ch_int);
  62         if (!intr)
  63                 return IRQ_HANDLED;
  64
  65         edma_writel_chreg(fsl_chan, 1, ch_int);
  66
  67         fsl_edma_tx_chan_handler(fsl_chan);
  68
  69         return IRQ_HANDLED;
  70 }
  71
  72 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
  73 {
  74         struct fsl_edma_engine *fsl_edma = dev_id;
  75         unsigned int err, ch;
  76         struct edma_regs *regs = &fsl_edma->regs;
  77
  78         err = edma_readl(fsl_edma, regs->errl);
  79         if (!err)
  80                 return IRQ_NONE;
  81
  82         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  83                 if (err & (0x1 << ch)) {
  84                         fsl_edma_disable_request(&fsl_edma->chans[ch]);
  85                         edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
  86                         fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
  87                 }
  88         }
  89         return IRQ_HANDLED;
  90 }
  91
  92 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
  93 {
  94         if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
  95                 return IRQ_HANDLED;
  96
  97         return fsl_edma_err_handler(irq, dev_id);
  98 }
  99
 100 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
 101                 struct of_dma *ofdma)
 102 {
 103         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 104         struct dma_chan *chan, *_chan;
 105         struct fsl_edma_chan *fsl_chan;
 106         u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
 107         unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
 108
 109         if (dma_spec->args_count != 2)
 110                 return NULL;
 111
 112         mutex_lock(&fsl_edma->fsl_edma_mutex);
 113         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
 114                 if (chan->client_count)
 115                         continue;
 116                 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
 117                         chan = dma_get_slave_channel(chan);
 118                         if (chan) {
 119                                 chan->device->privatecnt++;
 120                                 fsl_chan = to_fsl_edma_chan(chan);
 121                                 fsl_chan->slave_id = dma_spec->args[1];
 122                                 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
 123                                                 true);
 124                                 mutex_unlock(&fsl_edma->fsl_edma_mutex);
 125                                 return chan;
 126                         }
 127                 }
 128         }
 129         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 130         return NULL;
 131 }
 132
 133 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 134                                         struct of_dma *ofdma)
 135 {
 136         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 137         struct dma_chan *chan, *_chan;
 138         struct fsl_edma_chan *fsl_chan;
 139         bool b_chmux;
 140         int i;
 141
 142         if (dma_spec->args_count != 3)
 143                 return NULL;
 144
 145         b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
 146
 147         mutex_lock(&fsl_edma->fsl_edma_mutex);
 148         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
 149                                         device_node) {
 150
 151                 if (chan->client_count)
 152                         continue;
 153
 154                 fsl_chan = to_fsl_edma_chan(chan);
 155                 i = fsl_chan - fsl_edma->chans;
 156
 157                 chan = dma_get_slave_channel(chan);
 158                 chan->device->privatecnt++;
 159                 fsl_chan->priority = dma_spec->args[1];
 160                 fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
 161                 fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
 162                 fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
 163
 164                 if (!b_chmux && i == dma_spec->args[0]) {
 165                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 166                         return chan;
 167                 } else if (b_chmux && !fsl_chan->srcid) {
 168                         /* if controller support channel mux, choose a free channel */
 169                         fsl_chan->srcid = dma_spec->args[0];
 170                         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 171                         return chan;
 172                 }
 173         }
 174         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 175         return NULL;
 176 }
 177
 178 static int
 179 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 180 {
 181         int ret;
 182
 183         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 184
 185         fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
 186         if (fsl_edma->txirq < 0)
 187                 return fsl_edma->txirq;
 188
 189         fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
 190         if (fsl_edma->errirq < 0)
 191                 return fsl_edma->errirq;
 192
 193         if (fsl_edma->txirq == fsl_edma->errirq) {
 194                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 195                                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
 196                 if (ret) {
 197                         dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
 198                         return ret;
 199                 }
 200         } else {
 201                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 202                                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
 203                 if (ret) {
 204                         dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
 205                         return ret;
 206                 }
 207
 208                 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
 209                                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
 210                 if (ret) {
 211                         dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
 212                         return ret;
 213                 }
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 220 {
 221         int ret;
 222         int i;
 223
 224         for (i = 0; i < fsl_edma->n_chans; i++) {
 225
 226                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 227
 228                 if (fsl_edma->chan_masked & BIT(i))
 229                         continue;
 230
 231                 /* request channel irq */
 232                 fsl_chan->txirq = platform_get_irq(pdev, i);
 233                 if (fsl_chan->txirq < 0) {
 234                         dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i);
 235                         return  -EINVAL;
 236                 }
 237
 238                 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
 239                         fsl_edma3_tx_handler, IRQF_SHARED,
 240                         fsl_chan->chan_name, fsl_chan);
 241                 if (ret) {
 242                         dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
 243                         return -EINVAL;
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 static int
 251 fsl_edma2_irq_init(struct platform_device *pdev,
 252                    struct fsl_edma_engine *fsl_edma)
 253 {
 254         int i, ret, irq;
 255         int count;
 256
 257         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 258
 259         count = platform_irq_count(pdev);
 260         dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
 261         if (count <= 2) {
 262                 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
 263                 return -EINVAL;
 264         }
 265         /*
 266          * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
 267          * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
 268          * For now, just simply request irq without IRQF_SHARED flag, since 16
 269          * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
 270          */
 271         for (i = 0; i < count; i++) {
 272                 irq = platform_get_irq(pdev, i);
 273                 if (irq < 0)
 274                         return -ENXIO;
 275
 276                 /* The last IRQ is for eDMA err */
 277                 if (i == count - 1)
 278                         ret = devm_request_irq(&pdev->dev, irq,
 279                                                 fsl_edma_err_handler,
 280                                                 0, "eDMA2-ERR", fsl_edma);
 281                 else
 282                         ret = devm_request_irq(&pdev->dev, irq,
 283                                                 fsl_edma_tx_handler, 0,
 284                                                 fsl_edma->chans[i].chan_name,
 285                                                 fsl_edma);
 286                 if (ret)
 287                         return ret;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static void fsl_edma_irq_exit(
 294                 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 295 {
 296         if (fsl_edma->txirq == fsl_edma->errirq) {
 297                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 298         } else {
 299                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 300                 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
 301         }
 302 }
 303
 304 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
 305 {
 306         int i;
 307
 308         for (i = 0; i < nr_clocks; i++)
 309                 clk_disable_unprepare(fsl_edma->muxclk[i]);
 310 }
 311
 312 static struct fsl_edma_drvdata vf610_data = {
 313         .dmamuxs = DMAMUX_NR,
 314         .flags = FSL_EDMA_DRV_WRAP_IO,
 315         .chreg_off = EDMA_TCD,
 316         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 317         .setup_irq = fsl_edma_irq_init,
 318 };
 319
 320 static struct fsl_edma_drvdata ls1028a_data = {
 321         .dmamuxs = DMAMUX_NR,
 322         .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
 323         .chreg_off = EDMA_TCD,
 324         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 325         .setup_irq = fsl_edma_irq_init,
 326 };
 327
 328 static struct fsl_edma_drvdata imx7ulp_data = {
 329         .dmamuxs = 1,
 330         .chreg_off = EDMA_TCD,
 331         .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
 332         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
 333         .setup_irq = fsl_edma2_irq_init,
 334 };
 335
 336 static struct fsl_edma_drvdata imx8qm_data = {
 337         .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
 338         .chreg_space_sz = 0x10000,
 339         .chreg_off = 0x10000,
 340         .setup_irq = fsl_edma3_irq_init,
 341 };
 342
 343 static struct fsl_edma_drvdata imx8qm_audio_data = {
 344         .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
 345         .chreg_space_sz = 0x10000,
 346         .chreg_off = 0x10000,
 347         .setup_irq = fsl_edma3_irq_init,
 348 };
 349
 350 static struct fsl_edma_drvdata imx93_data3 = {
 351         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
 352         .chreg_space_sz = 0x10000,
 353         .chreg_off = 0x10000,
 354         .setup_irq = fsl_edma3_irq_init,
 355 };
 356
 357 static struct fsl_edma_drvdata imx93_data4 = {
 358         .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
 359         .chreg_space_sz = 0x8000,
 360         .chreg_off = 0x10000,
 361         .setup_irq = fsl_edma3_irq_init,
 362 };
 363
 364 static const struct of_device_id fsl_edma_dt_ids[] = {
 365         { .compatible = "fsl,vf610-edma", .data = &vf610_data},
 366         { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
 367         { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
 368         { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
 369         { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
 370         { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
 371         { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
 372         { /* sentinel */ }
 373 };
 374 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
 375
 376 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 377 {
 378         struct fsl_edma_chan *fsl_chan;
 379         struct device_link *link;
 380         struct device *pd_chan;
 381         struct device *dev;
 382         int i;
 383
 384         dev = &pdev->dev;
 385
 386         for (i = 0; i < fsl_edma->n_chans; i++) {
 387                 if (fsl_edma->chan_masked & BIT(i))
 388                         continue;
 389
 390                 fsl_chan = &fsl_edma->chans[i];
 391
 392                 pd_chan = dev_pm_domain_attach_by_id(dev, i);
 393                 if (IS_ERR_OR_NULL(pd_chan)) {
 394                         dev_err(dev, "Failed attach pd %d\n", i);
 395                         return -EINVAL;
 396                 }
 397
 398                 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
 399                                              DL_FLAG_PM_RUNTIME |
 400                                              DL_FLAG_RPM_ACTIVE);
 401                 if (IS_ERR(link)) {
 402                         dev_err(dev, "Failed to add device_link to %d: %ld\n", i,
 403                                 PTR_ERR(link));
 404                         return -EINVAL;
 405                 }
 406
 407                 fsl_chan->pd_dev = pd_chan;
 408
 409                 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
 410                 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
 411                 pm_runtime_set_active(fsl_chan->pd_dev);
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int fsl_edma_probe(struct platform_device *pdev)
 418 {
 419         const struct of_device_id *of_id =
 420                         of_match_device(fsl_edma_dt_ids, &pdev->dev);
 421         struct device_node *np = pdev->dev.of_node;
 422         struct fsl_edma_engine *fsl_edma;
 423         const struct fsl_edma_drvdata *drvdata = NULL;
 424         u32 chan_mask[2] = {0, 0};
 425         struct edma_regs *regs;
 426         int chans;
 427         int ret, i;
 428
 429         if (of_id)
 430                 drvdata = of_id->data;
 431         if (!drvdata) {
 432                 dev_err(&pdev->dev, "unable to find driver data\n");
 433                 return -EINVAL;
 434         }
 435
 436         ret = of_property_read_u32(np, "dma-channels", &chans);
 437         if (ret) {
 438                 dev_err(&pdev->dev, "Can't get dma-channels.\n");
 439                 return ret;
 440         }
 441
 442         fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
 443                                 GFP_KERNEL);
 444         if (!fsl_edma)
 445                 return -ENOMEM;
 446
 447         fsl_edma->drvdata = drvdata;
 448         fsl_edma->n_chans = chans;
 449         mutex_init(&fsl_edma->fsl_edma_mutex);
 450
 451         fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
 452         if (IS_ERR(fsl_edma->membase))
 453                 return PTR_ERR(fsl_edma->membase);
 454
 455         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
 456                 fsl_edma_setup_regs(fsl_edma);
 457                 regs = &fsl_edma->regs;
 458         }
 459
 460         if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
 461                 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
 462                 if (IS_ERR(fsl_edma->dmaclk)) {
 463                         dev_err(&pdev->dev, "Missing DMA block clock.\n");
 464                         return PTR_ERR(fsl_edma->dmaclk);
 465                 }
 466         }
 467
 468         if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
 469                 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
 470                 if (IS_ERR(fsl_edma->chclk)) {
 471                         dev_err(&pdev->dev, "Missing MP block clock.\n");
 472                         return PTR_ERR(fsl_edma->chclk);
 473                 }
 474         }
 475
 476         ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
 477
 478         if (ret > 0) {
 479                 fsl_edma->chan_masked = chan_mask[1];
 480                 fsl_edma->chan_masked <<= 32;
 481                 fsl_edma->chan_masked |= chan_mask[0];
 482         }
 483
 484         for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
 485                 char clkname[32];
 486
 487                 /* eDMAv3 mux register move to TCD area if ch_mux exist */
 488                 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
 489                         break;
 490
 491                 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
 492                                                                       1 + i);
 493                 if (IS_ERR(fsl_edma->muxbase[i])) {
 494                         /* on error: disable all previously enabled clks */
 495                         fsl_disable_clocks(fsl_edma, i);
 496                         return PTR_ERR(fsl_edma->muxbase[i]);
 497                 }
 498
 499                 sprintf(clkname, "dmamux%d", i);
 500                 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
 501                 if (IS_ERR(fsl_edma->muxclk[i])) {
 502                         dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
 503                         /* on error: disable all previously enabled clks */
 504                         return PTR_ERR(fsl_edma->muxclk[i]);
 505                 }
 506         }
 507
 508         fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
 509
 510         if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
 511                 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
 512                 if (ret)
 513                         return ret;
 514         }
 515
 516         INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 517         for (i = 0; i < fsl_edma->n_chans; i++) {
 518                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 519                 int len;
 520
 521                 if (fsl_edma->chan_masked & BIT(i))
 522                         continue;
 523
 524                 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
 525                                                            dev_name(&pdev->dev), i);
 526
 527                 fsl_chan->edma = fsl_edma;
 528                 fsl_chan->pm_state = RUNNING;
 529                 fsl_chan->slave_id = 0;
 530                 fsl_chan->idle = true;
 531                 fsl_chan->dma_dir = DMA_NONE;
 532                 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
 533
 534                 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
 535                                 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
 536                 fsl_chan->tcd = fsl_edma->membase
 537                                 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
 538
 539                 fsl_chan->pdev = pdev;
 540                 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
 541
 542                 edma_write_tcdreg(fsl_chan, 0, csr);
 543                 fsl_edma_chan_mux(fsl_chan, 0, false);
 544         }
 545
 546         ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
 547         if (ret)
 548                 return ret;
 549
 550         dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
 551         dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
 552         dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
 553         dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
 554
 555         fsl_edma->dma_dev.dev = &pdev->dev;
 556         fsl_edma->dma_dev.device_alloc_chan_resources
 557                 = fsl_edma_alloc_chan_resources;
 558         fsl_edma->dma_dev.device_free_chan_resources
 559                 = fsl_edma_free_chan_resources;
 560         fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
 561         fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
 562         fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
 563         fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
 564         fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
 565         fsl_edma->dma_dev.device_pause = fsl_edma_pause;
 566         fsl_edma->dma_dev.device_resume = fsl_edma_resume;
 567         fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
 568         fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
 569         fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
 570
 571         fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
 572         fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
 573
 574         if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
 575                 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 576                 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
 577         }
 578
 579         fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 580         if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
 581                 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
 582
 583         fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
 584                                         DMAENGINE_ALIGN_64_BYTES :
 585                                         DMAENGINE_ALIGN_32_BYTES;
 586
 587         /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
 588         dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
 589
 590         fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
 591
 592         platform_set_drvdata(pdev, fsl_edma);
 593
 594         ret = dma_async_device_register(&fsl_edma->dma_dev);
 595         if (ret) {
 596                 dev_err(&pdev->dev,
 597                         "Can't register Freescale eDMA engine. (%d)\n", ret);
 598                 return ret;
 599         }
 600
 601         ret = of_dma_controller_register(np,
 602                         drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
 603                         fsl_edma);
 604         if (ret) {
 605                 dev_err(&pdev->dev,
 606                         "Can't register Freescale eDMA of_dma. (%d)\n", ret);
 607                 dma_async_device_unregister(&fsl_edma->dma_dev);
 608                 return ret;
 609         }
 610
 611         /* enable round robin arbitration */
 612         if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
 613                 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 614
 615         return 0;
 616 }
 617
 618 static int fsl_edma_remove(struct platform_device *pdev)
 619 {
 620         struct device_node *np = pdev->dev.of_node;
 621         struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
 622
 623         fsl_edma_irq_exit(pdev, fsl_edma);
 624         fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
 625         of_dma_controller_free(np);
 626         dma_async_device_unregister(&fsl_edma->dma_dev);
 627         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
 628
 629         return 0;
 630 }
 631
 632 static int fsl_edma_suspend_late(struct device *dev)
 633 {
 634         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 635         struct fsl_edma_chan *fsl_chan;
 636         unsigned long flags;
 637         int i;
 638
 639         for (i = 0; i < fsl_edma->n_chans; i++) {
 640                 fsl_chan = &fsl_edma->chans[i];
 641                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 642                 /* Make sure chan is idle or will force disable. */
 643                 if (unlikely(!fsl_chan->idle)) {
 644                         dev_warn(dev, "WARN: There is non-idle channel.");
 645                         fsl_edma_disable_request(fsl_chan);
 646                         fsl_edma_chan_mux(fsl_chan, 0, false);
 647                 }
 648
 649                 fsl_chan->pm_state = SUSPENDED;
 650                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int fsl_edma_resume_early(struct device *dev)
 657 {
 658         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 659         struct fsl_edma_chan *fsl_chan;
 660         struct edma_regs *regs = &fsl_edma->regs;
 661         int i;
 662
 663         for (i = 0; i < fsl_edma->n_chans; i++) {
 664                 fsl_chan = &fsl_edma->chans[i];
 665                 fsl_chan->pm_state = RUNNING;
 666                 edma_write_tcdreg(fsl_chan, 0, csr);
 667                 if (fsl_chan->slave_id != 0)
 668                         fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
 669         }
 670
 671         edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 672
 673         return 0;
 674 }
 675
 676 /*
 677  * eDMA provides the service to others, so it should be suspend late
 678  * and resume early. When eDMA suspend, all of the clients should stop
 679  * the DMA data transmission and let the channel idle.
 680  */
 681 static const struct dev_pm_ops fsl_edma_pm_ops = {
 682         .suspend_late   = fsl_edma_suspend_late,
 683         .resume_early   = fsl_edma_resume_early,
 684 };
 685
 686 static struct platform_driver fsl_edma_driver = {
 687         .driver         = {
 688                 .name   = "fsl-edma",
 689                 .of_match_table = fsl_edma_dt_ids,
 690                 .pm     = &fsl_edma_pm_ops,
 691         },
 692         .probe          = fsl_edma_probe,
 693         .remove         = fsl_edma_remove,
 694 };
 695
 696 static int __init fsl_edma_init(void)
 697 {
 698         return platform_driver_register(&fsl_edma_driver);
 699 }
 700 subsys_initcall(fsl_edma_init);
 701
 702 static void __exit fsl_edma_exit(void)
 703 {
 704         platform_driver_unregister(&fsl_edma_driver);
 705 }
 706 module_exit(fsl_edma_exit);
 707
 708 MODULE_ALIAS("platform:fsl-edma");
 709 MODULE_DESCRIPTION("Freescale eDMA engine driver");
 710 MODULE_LICENSE("GPL v2");