drivers/dma/fsl-edma-main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * drivers/dma/fsl-edma.c
   4  *
   5  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   6  *
   7  * Driver for the Freescale eDMA engine with flexible channel multiplexing
   8  * capability for DMA request sources. The eDMA block can be found on some
   9  * Vybrid and Layerscape SoCs.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/clk.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_dma.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include "fsl-edma-common.h"
  23
  24 static void fsl_edma_synchronize(struct dma_chan *chan)
  25 {
  26         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
  27
  28         vchan_synchronize(&fsl_chan->vchan);
  29 }
  30
  31 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
  32 {
  33         struct fsl_edma_engine *fsl_edma = dev_id;
  34         unsigned int intr, ch;
  35         struct edma_regs *regs = &fsl_edma->regs;
  36
  37         intr = edma_readl(fsl_edma, regs->intl);
  38         if (!intr)
  39                 return IRQ_NONE;
  40
  41         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  42                 if (intr & (0x1 << ch)) {
  43                         edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
  44                         fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
  45                 }
  46         }
  47         return IRQ_HANDLED;
  48 }
  49
  50 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
  51 {
  52         struct fsl_edma_engine *fsl_edma = dev_id;
  53         unsigned int err, ch;
  54         struct edma_regs *regs = &fsl_edma->regs;
  55
  56         err = edma_readl(fsl_edma, regs->errl);
  57         if (!err)
  58                 return IRQ_NONE;
  59
  60         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
  61                 if (err & (0x1 << ch)) {
  62                         fsl_edma_disable_request(&fsl_edma->chans[ch]);
  63                         edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
  64                         fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
  65                 }
  66         }
  67         return IRQ_HANDLED;
  68 }
  69
  70 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
  71 {
  72         if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
  73                 return IRQ_HANDLED;
  74
  75         return fsl_edma_err_handler(irq, dev_id);
  76 }
  77
  78 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
  79                 struct of_dma *ofdma)
  80 {
  81         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
  82         struct dma_chan *chan, *_chan;
  83         struct fsl_edma_chan *fsl_chan;
  84         u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
  85         unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
  86
  87         if (dma_spec->args_count != 2)
  88                 return NULL;
  89
  90         mutex_lock(&fsl_edma->fsl_edma_mutex);
  91         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
  92                 if (chan->client_count)
  93                         continue;
  94                 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
  95                         chan = dma_get_slave_channel(chan);
  96                         if (chan) {
  97                                 chan->device->privatecnt++;
  98                                 fsl_chan = to_fsl_edma_chan(chan);
  99                                 fsl_chan->slave_id = dma_spec->args[1];
 100                                 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
 101                                                 true);
 102                                 mutex_unlock(&fsl_edma->fsl_edma_mutex);
 103                                 return chan;
 104                         }
 105                 }
 106         }
 107         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 108         return NULL;
 109 }
 110
 111 static int
 112 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 113 {
 114         int ret;
 115
 116         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 117
 118         fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
 119         if (fsl_edma->txirq < 0)
 120                 return fsl_edma->txirq;
 121
 122         fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
 123         if (fsl_edma->errirq < 0)
 124                 return fsl_edma->errirq;
 125
 126         if (fsl_edma->txirq == fsl_edma->errirq) {
 127                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 128                                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
 129                 if (ret) {
 130                         dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
 131                         return ret;
 132                 }
 133         } else {
 134                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 135                                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
 136                 if (ret) {
 137                         dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
 138                         return ret;
 139                 }
 140
 141                 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
 142                                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
 143                 if (ret) {
 144                         dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
 145                         return ret;
 146                 }
 147         }
 148
 149         return 0;
 150 }
 151
 152 static int
 153 fsl_edma2_irq_init(struct platform_device *pdev,
 154                    struct fsl_edma_engine *fsl_edma)
 155 {
 156         int i, ret, irq;
 157         int count;
 158
 159         edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
 160
 161         count = platform_irq_count(pdev);
 162         dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
 163         if (count <= 2) {
 164                 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
 165                 return -EINVAL;
 166         }
 167         /*
 168          * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
 169          * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
 170          * For now, just simply request irq without IRQF_SHARED flag, since 16
 171          * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
 172          */
 173         for (i = 0; i < count; i++) {
 174                 irq = platform_get_irq(pdev, i);
 175                 if (irq < 0)
 176                         return -ENXIO;
 177
 178                 /* The last IRQ is for eDMA err */
 179                 if (i == count - 1)
 180                         ret = devm_request_irq(&pdev->dev, irq,
 181                                                 fsl_edma_err_handler,
 182                                                 0, "eDMA2-ERR", fsl_edma);
 183                 else
 184                         ret = devm_request_irq(&pdev->dev, irq,
 185                                                 fsl_edma_tx_handler, 0,
 186                                                 fsl_edma->chans[i].chan_name,
 187                                                 fsl_edma);
 188                 if (ret)
 189                         return ret;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static void fsl_edma_irq_exit(
 196                 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 197 {
 198         if (fsl_edma->txirq == fsl_edma->errirq) {
 199                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 200         } else {
 201                 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
 202                 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
 203         }
 204 }
 205
 206 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
 207 {
 208         int i;
 209
 210         for (i = 0; i < nr_clocks; i++)
 211                 clk_disable_unprepare(fsl_edma->muxclk[i]);
 212 }
 213
 214 static struct fsl_edma_drvdata vf610_data = {
 215         .dmamuxs = DMAMUX_NR,
 216         .flags = FSL_EDMA_DRV_WRAP_IO,
 217         .setup_irq = fsl_edma_irq_init,
 218 };
 219
 220 static struct fsl_edma_drvdata ls1028a_data = {
 221         .dmamuxs = DMAMUX_NR,
 222         .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
 223         .setup_irq = fsl_edma_irq_init,
 224 };
 225
 226 static struct fsl_edma_drvdata imx7ulp_data = {
 227         .dmamuxs = 1,
 228         .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
 229         .setup_irq = fsl_edma2_irq_init,
 230 };
 231
 232 static const struct of_device_id fsl_edma_dt_ids[] = {
 233         { .compatible = "fsl,vf610-edma", .data = &vf610_data},
 234         { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
 235         { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
 236         { /* sentinel */ }
 237 };
 238 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
 239
 240 static int fsl_edma_probe(struct platform_device *pdev)
 241 {
 242         const struct of_device_id *of_id =
 243                         of_match_device(fsl_edma_dt_ids, &pdev->dev);
 244         struct device_node *np = pdev->dev.of_node;
 245         struct fsl_edma_engine *fsl_edma;
 246         const struct fsl_edma_drvdata *drvdata = NULL;
 247         struct edma_regs *regs;
 248         int chans;
 249         int ret, i;
 250
 251         if (of_id)
 252                 drvdata = of_id->data;
 253         if (!drvdata) {
 254                 dev_err(&pdev->dev, "unable to find driver data\n");
 255                 return -EINVAL;
 256         }
 257
 258         ret = of_property_read_u32(np, "dma-channels", &chans);
 259         if (ret) {
 260                 dev_err(&pdev->dev, "Can't get dma-channels.\n");
 261                 return ret;
 262         }
 263
 264         fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
 265                                 GFP_KERNEL);
 266         if (!fsl_edma)
 267                 return -ENOMEM;
 268
 269         fsl_edma->drvdata = drvdata;
 270         fsl_edma->n_chans = chans;
 271         mutex_init(&fsl_edma->fsl_edma_mutex);
 272
 273         fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
 274         if (IS_ERR(fsl_edma->membase))
 275                 return PTR_ERR(fsl_edma->membase);
 276
 277         fsl_edma_setup_regs(fsl_edma);
 278         regs = &fsl_edma->regs;
 279
 280         if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
 281                 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
 282                 if (IS_ERR(fsl_edma->dmaclk)) {
 283                         dev_err(&pdev->dev, "Missing DMA block clock.\n");
 284                         return PTR_ERR(fsl_edma->dmaclk);
 285                 }
 286         }
 287
 288         for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
 289                 char clkname[32];
 290
 291                 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
 292                                                                       1 + i);
 293                 if (IS_ERR(fsl_edma->muxbase[i])) {
 294                         /* on error: disable all previously enabled clks */
 295                         fsl_disable_clocks(fsl_edma, i);
 296                         return PTR_ERR(fsl_edma->muxbase[i]);
 297                 }
 298
 299                 sprintf(clkname, "dmamux%d", i);
 300                 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
 301                 if (IS_ERR(fsl_edma->muxclk[i])) {
 302                         dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
 303                         /* on error: disable all previously enabled clks */
 304                         return PTR_ERR(fsl_edma->muxclk[i]);
 305                 }
 306         }
 307
 308         fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
 309
 310         INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 311         for (i = 0; i < fsl_edma->n_chans; i++) {
 312                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 313
 314                 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
 315                                                            dev_name(&pdev->dev), i);
 316
 317                 fsl_chan->edma = fsl_edma;
 318                 fsl_chan->pm_state = RUNNING;
 319                 fsl_chan->slave_id = 0;
 320                 fsl_chan->idle = true;
 321                 fsl_chan->dma_dir = DMA_NONE;
 322                 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
 323                 fsl_chan->tcd = fsl_edma->membase + EDMA_TCD
 324                                 + i * sizeof(struct fsl_edma_hw_tcd);
 325                 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
 326
 327                 edma_write_tcdreg(fsl_chan, 0, csr);
 328                 fsl_edma_chan_mux(fsl_chan, 0, false);
 329         }
 330
 331         ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
 332         if (ret)
 333                 return ret;
 334
 335         dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
 336         dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
 337         dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
 338         dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
 339
 340         fsl_edma->dma_dev.dev = &pdev->dev;
 341         fsl_edma->dma_dev.device_alloc_chan_resources
 342                 = fsl_edma_alloc_chan_resources;
 343         fsl_edma->dma_dev.device_free_chan_resources
 344                 = fsl_edma_free_chan_resources;
 345         fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
 346         fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
 347         fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
 348         fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
 349         fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
 350         fsl_edma->dma_dev.device_pause = fsl_edma_pause;
 351         fsl_edma->dma_dev.device_resume = fsl_edma_resume;
 352         fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
 353         fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
 354         fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
 355
 356         fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
 357         fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
 358         fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 359
 360         fsl_edma->dma_dev.copy_align = DMAENGINE_ALIGN_32_BYTES;
 361         /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
 362         dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff);
 363
 364         platform_set_drvdata(pdev, fsl_edma);
 365
 366         ret = dma_async_device_register(&fsl_edma->dma_dev);
 367         if (ret) {
 368                 dev_err(&pdev->dev,
 369                         "Can't register Freescale eDMA engine. (%d)\n", ret);
 370                 return ret;
 371         }
 372
 373         ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
 374         if (ret) {
 375                 dev_err(&pdev->dev,
 376                         "Can't register Freescale eDMA of_dma. (%d)\n", ret);
 377                 dma_async_device_unregister(&fsl_edma->dma_dev);
 378                 return ret;
 379         }
 380
 381         /* enable round robin arbitration */
 382         edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 383
 384         return 0;
 385 }
 386
 387 static int fsl_edma_remove(struct platform_device *pdev)
 388 {
 389         struct device_node *np = pdev->dev.of_node;
 390         struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
 391
 392         fsl_edma_irq_exit(pdev, fsl_edma);
 393         fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
 394         of_dma_controller_free(np);
 395         dma_async_device_unregister(&fsl_edma->dma_dev);
 396         fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
 397
 398         return 0;
 399 }
 400
 401 static int fsl_edma_suspend_late(struct device *dev)
 402 {
 403         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 404         struct fsl_edma_chan *fsl_chan;
 405         unsigned long flags;
 406         int i;
 407
 408         for (i = 0; i < fsl_edma->n_chans; i++) {
 409                 fsl_chan = &fsl_edma->chans[i];
 410                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 411                 /* Make sure chan is idle or will force disable. */
 412                 if (unlikely(!fsl_chan->idle)) {
 413                         dev_warn(dev, "WARN: There is non-idle channel.");
 414                         fsl_edma_disable_request(fsl_chan);
 415                         fsl_edma_chan_mux(fsl_chan, 0, false);
 416                 }
 417
 418                 fsl_chan->pm_state = SUSPENDED;
 419                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int fsl_edma_resume_early(struct device *dev)
 426 {
 427         struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
 428         struct fsl_edma_chan *fsl_chan;
 429         struct edma_regs *regs = &fsl_edma->regs;
 430         int i;
 431
 432         for (i = 0; i < fsl_edma->n_chans; i++) {
 433                 fsl_chan = &fsl_edma->chans[i];
 434                 fsl_chan->pm_state = RUNNING;
 435                 edma_write_tcdreg(fsl_chan, 0, csr);
 436                 if (fsl_chan->slave_id != 0)
 437                         fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
 438         }
 439
 440         edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * eDMA provides the service to others, so it should be suspend late
 447  * and resume early. When eDMA suspend, all of the clients should stop
 448  * the DMA data transmission and let the channel idle.
 449  */
 450 static const struct dev_pm_ops fsl_edma_pm_ops = {
 451         .suspend_late   = fsl_edma_suspend_late,
 452         .resume_early   = fsl_edma_resume_early,
 453 };
 454
 455 static struct platform_driver fsl_edma_driver = {
 456         .driver         = {
 457                 .name   = "fsl-edma",
 458                 .of_match_table = fsl_edma_dt_ids,
 459                 .pm     = &fsl_edma_pm_ops,
 460         },
 461         .probe          = fsl_edma_probe,
 462         .remove         = fsl_edma_remove,
 463 };
 464
 465 static int __init fsl_edma_init(void)
 466 {
 467         return platform_driver_register(&fsl_edma_driver);
 468 }
 469 subsys_initcall(fsl_edma_init);
 470
 471 static void __exit fsl_edma_exit(void)
 472 {
 473         platform_driver_unregister(&fsl_edma_driver);
 474 }
 475 module_exit(fsl_edma_exit);
 476
 477 MODULE_ALIAS("platform:fsl-edma");
 478 MODULE_DESCRIPTION("Freescale eDMA engine driver");
 479 MODULE_LICENSE("GPL v2");