drivers/dma/fsl-edma-common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
   4 // Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>
   5
   6 #include <linux/dmapool.h>
   7 #include <linux/module.h>
   8 #include <linux/slab.h>
   9 #include <linux/dma-mapping.h>
  10
  11 #include "fsl-edma-common.h"
  12
  13 #define EDMA_CR                 0x00
  14 #define EDMA_ES                 0x04
  15 #define EDMA_ERQ                0x0C
  16 #define EDMA_EEI                0x14
  17 #define EDMA_SERQ               0x1B
  18 #define EDMA_CERQ               0x1A
  19 #define EDMA_SEEI               0x19
  20 #define EDMA_CEEI               0x18
  21 #define EDMA_CINT               0x1F
  22 #define EDMA_CERR               0x1E
  23 #define EDMA_SSRT               0x1D
  24 #define EDMA_CDNE               0x1C
  25 #define EDMA_INTR               0x24
  26 #define EDMA_ERR                0x2C
  27
  28 #define EDMA64_ERQH             0x08
  29 #define EDMA64_EEIH             0x10
  30 #define EDMA64_SERQ             0x18
  31 #define EDMA64_CERQ             0x19
  32 #define EDMA64_SEEI             0x1a
  33 #define EDMA64_CEEI             0x1b
  34 #define EDMA64_CINT             0x1c
  35 #define EDMA64_CERR             0x1d
  36 #define EDMA64_SSRT             0x1e
  37 #define EDMA64_CDNE             0x1f
  38 #define EDMA64_INTH             0x20
  39 #define EDMA64_INTL             0x24
  40 #define EDMA64_ERRH             0x28
  41 #define EDMA64_ERRL             0x2c
  42
  43 #define EDMA_TCD                0x1000
  44
  45 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
  46 {
  47         struct edma_regs *regs = &fsl_chan->edma->regs;
  48         u32 ch = fsl_chan->vchan.chan.chan_id;
  49
  50         if (fsl_chan->edma->drvdata->version == v1) {
  51                 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
  52                 edma_writeb(fsl_chan->edma, ch, regs->serq);
  53         } else {
  54                 /* ColdFire is big endian, and accesses natively
  55                  * big endian I/O peripherals
  56                  */
  57                 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
  58                 iowrite8(ch, regs->serq);
  59         }
  60 }
  61
  62 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
  63 {
  64         struct edma_regs *regs = &fsl_chan->edma->regs;
  65         u32 ch = fsl_chan->vchan.chan.chan_id;
  66
  67         if (fsl_chan->edma->drvdata->version == v1) {
  68                 edma_writeb(fsl_chan->edma, ch, regs->cerq);
  69                 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
  70         } else {
  71                 /* ColdFire is big endian, and accesses natively
  72                  * big endian I/O peripherals
  73                  */
  74                 iowrite8(ch, regs->cerq);
  75                 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
  76         }
  77 }
  78
  79 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
  80                            u32 off, u32 slot, bool enable)
  81 {
  82         u8 val8;
  83
  84         if (enable)
  85                 val8 = EDMAMUX_CHCFG_ENBL | slot;
  86         else
  87                 val8 = EDMAMUX_CHCFG_DIS;
  88
  89         iowrite8(val8, addr + off);
  90 }
  91
  92 static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
  93                             u32 off, u32 slot, bool enable)
  94 {
  95         u32 val;
  96
  97         if (enable)
  98                 val = EDMAMUX_CHCFG_ENBL << 24 | slot;
  99         else
 100                 val = EDMAMUX_CHCFG_DIS;
 101
 102         iowrite32(val, addr + off * 4);
 103 }
 104
 105 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
 106                        unsigned int slot, bool enable)
 107 {
 108         u32 ch = fsl_chan->vchan.chan.chan_id;
 109         void __iomem *muxaddr;
 110         unsigned int chans_per_mux, ch_off;
 111         int endian_diff[4] = {3, 1, -1, -3};
 112         u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
 113
 114         chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
 115         ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
 116
 117         if (fsl_chan->edma->drvdata->mux_swap)
 118                 ch_off += endian_diff[ch_off % 4];
 119
 120         muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
 121         slot = EDMAMUX_CHCFG_SOURCE(slot);
 122
 123         if (fsl_chan->edma->drvdata->version == v3)
 124                 mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
 125         else
 126                 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
 127 }
 128
 129 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
 130 {
 131         switch (addr_width) {
 132         case 1:
 133                 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
 134         case 2:
 135                 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
 136         case 4:
 137                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 138         case 8:
 139                 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
 140         default:
 141                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 142         }
 143 }
 144
 145 void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
 146 {
 147         struct fsl_edma_desc *fsl_desc;
 148         int i;
 149
 150         fsl_desc = to_fsl_edma_desc(vdesc);
 151         for (i = 0; i < fsl_desc->n_tcds; i++)
 152                 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
 153                               fsl_desc->tcd[i].ptcd);
 154         kfree(fsl_desc);
 155 }
 156
 157 int fsl_edma_terminate_all(struct dma_chan *chan)
 158 {
 159         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 160         unsigned long flags;
 161         LIST_HEAD(head);
 162
 163         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 164         fsl_edma_disable_request(fsl_chan);
 165         fsl_chan->edesc = NULL;
 166         fsl_chan->idle = true;
 167         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 168         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 169         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 170         return 0;
 171 }
 172
 173 int fsl_edma_pause(struct dma_chan *chan)
 174 {
 175         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 176         unsigned long flags;
 177
 178         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 179         if (fsl_chan->edesc) {
 180                 fsl_edma_disable_request(fsl_chan);
 181                 fsl_chan->status = DMA_PAUSED;
 182                 fsl_chan->idle = true;
 183         }
 184         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 185         return 0;
 186 }
 187
 188 int fsl_edma_resume(struct dma_chan *chan)
 189 {
 190         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 191         unsigned long flags;
 192
 193         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 194         if (fsl_chan->edesc) {
 195                 fsl_edma_enable_request(fsl_chan);
 196                 fsl_chan->status = DMA_IN_PROGRESS;
 197                 fsl_chan->idle = false;
 198         }
 199         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 200         return 0;
 201 }
 202
 203 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
 204 {
 205         if (fsl_chan->dma_dir != DMA_NONE)
 206                 dma_unmap_resource(fsl_chan->vchan.chan.device->dev,
 207                                    fsl_chan->dma_dev_addr,
 208                                    fsl_chan->dma_dev_size,
 209                                    fsl_chan->dma_dir, 0);
 210         fsl_chan->dma_dir = DMA_NONE;
 211 }
 212
 213 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan,
 214                                     enum dma_transfer_direction dir)
 215 {
 216         struct device *dev = fsl_chan->vchan.chan.device->dev;
 217         enum dma_data_direction dma_dir;
 218         phys_addr_t addr = 0;
 219         u32 size = 0;
 220
 221         switch (dir) {
 222         case DMA_MEM_TO_DEV:
 223                 dma_dir = DMA_FROM_DEVICE;
 224                 addr = fsl_chan->cfg.dst_addr;
 225                 size = fsl_chan->cfg.dst_maxburst;
 226                 break;
 227         case DMA_DEV_TO_MEM:
 228                 dma_dir = DMA_TO_DEVICE;
 229                 addr = fsl_chan->cfg.src_addr;
 230                 size = fsl_chan->cfg.src_maxburst;
 231                 break;
 232         default:
 233                 dma_dir = DMA_NONE;
 234                 break;
 235         }
 236
 237         /* Already mapped for this config? */
 238         if (fsl_chan->dma_dir == dma_dir)
 239                 return true;
 240
 241         fsl_edma_unprep_slave_dma(fsl_chan);
 242
 243         fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0);
 244         if (dma_mapping_error(dev, fsl_chan->dma_dev_addr))
 245                 return false;
 246         fsl_chan->dma_dev_size = size;
 247         fsl_chan->dma_dir = dma_dir;
 248
 249         return true;
 250 }
 251
 252 int fsl_edma_slave_config(struct dma_chan *chan,
 253                                  struct dma_slave_config *cfg)
 254 {
 255         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 256
 257         memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
 258         fsl_edma_unprep_slave_dma(fsl_chan);
 259
 260         return 0;
 261 }
 262
 263 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 264                 struct virt_dma_desc *vdesc, bool in_progress)
 265 {
 266         struct fsl_edma_desc *edesc = fsl_chan->edesc;
 267         struct edma_regs *regs = &fsl_chan->edma->regs;
 268         u32 ch = fsl_chan->vchan.chan.chan_id;
 269         enum dma_transfer_direction dir = edesc->dirn;
 270         dma_addr_t cur_addr, dma_addr;
 271         size_t len, size;
 272         int i;
 273
 274         /* calculate the total size in this desc */
 275         for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
 276                 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 277                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 278
 279         if (!in_progress)
 280                 return len;
 281
 282         if (dir == DMA_MEM_TO_DEV)
 283                 cur_addr = edma_readl(fsl_chan->edma, &regs->tcd[ch].saddr);
 284         else
 285                 cur_addr = edma_readl(fsl_chan->edma, &regs->tcd[ch].daddr);
 286
 287         /* figure out the finished and calculate the residue */
 288         for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
 289                 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 290                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 291                 if (dir == DMA_MEM_TO_DEV)
 292                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
 293                 else
 294                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
 295
 296                 len -= size;
 297                 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
 298                         len += dma_addr + size - cur_addr;
 299                         break;
 300                 }
 301         }
 302
 303         return len;
 304 }
 305
 306 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 307                 dma_cookie_t cookie, struct dma_tx_state *txstate)
 308 {
 309         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 310         struct virt_dma_desc *vdesc;
 311         enum dma_status status;
 312         unsigned long flags;
 313
 314         status = dma_cookie_status(chan, cookie, txstate);
 315         if (status == DMA_COMPLETE)
 316                 return status;
 317
 318         if (!txstate)
 319                 return fsl_chan->status;
 320
 321         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 322         vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
 323         if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
 324                 txstate->residue =
 325                         fsl_edma_desc_residue(fsl_chan, vdesc, true);
 326         else if (vdesc)
 327                 txstate->residue =
 328                         fsl_edma_desc_residue(fsl_chan, vdesc, false);
 329         else
 330                 txstate->residue = 0;
 331
 332         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 333
 334         return fsl_chan->status;
 335 }
 336
 337 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 338                                   struct fsl_edma_hw_tcd *tcd)
 339 {
 340         struct fsl_edma_engine *edma = fsl_chan->edma;
 341         struct edma_regs *regs = &fsl_chan->edma->regs;
 342         u32 ch = fsl_chan->vchan.chan.chan_id;
 343         u16 csr = 0;
 344
 345         /*
 346          * TCD parameters are stored in struct fsl_edma_hw_tcd in little
 347          * endian format. However, we need to load the TCD registers in
 348          * big- or little-endian obeying the eDMA engine model endian,
 349          * and this is performed from specific edma_write functions
 350          */
 351         edma_writew(edma, 0,  &regs->tcd[ch].csr);
 352
 353         edma_writel(edma, (s32)tcd->saddr, &regs->tcd[ch].saddr);
 354         edma_writel(edma, (s32)tcd->daddr, &regs->tcd[ch].daddr);
 355
 356         edma_writew(edma, (s16)tcd->attr, &regs->tcd[ch].attr);
 357         edma_writew(edma, tcd->soff, &regs->tcd[ch].soff);
 358
 359         edma_writel(edma, (s32)tcd->nbytes, &regs->tcd[ch].nbytes);
 360         edma_writel(edma, (s32)tcd->slast, &regs->tcd[ch].slast);
 361
 362         edma_writew(edma, (s16)tcd->citer, &regs->tcd[ch].citer);
 363         edma_writew(edma, (s16)tcd->biter, &regs->tcd[ch].biter);
 364         edma_writew(edma, (s16)tcd->doff, &regs->tcd[ch].doff);
 365
 366         edma_writel(edma, (s32)tcd->dlast_sga,
 367                         &regs->tcd[ch].dlast_sga);
 368
 369         if (fsl_chan->is_sw) {
 370                 csr = le16_to_cpu(tcd->csr);
 371                 csr |= EDMA_TCD_CSR_START;
 372                 tcd->csr = cpu_to_le16(csr);
 373         }
 374
 375         edma_writew(edma, (s16)tcd->csr, &regs->tcd[ch].csr);
 376 }
 377
 378 static inline
 379 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
 380                        u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
 381                        u16 biter, u16 doff, u32 dlast_sga, bool major_int,
 382                        bool disable_req, bool enable_sg)
 383 {
 384         u16 csr = 0;
 385
 386         /*
 387          * eDMA hardware SGs require the TCDs to be stored in little
 388          * endian format irrespective of the register endian model.
 389          * So we put the value in little endian in memory, waiting
 390          * for fsl_edma_set_tcd_regs doing the swap.
 391          */
 392         tcd->saddr = cpu_to_le32(src);
 393         tcd->daddr = cpu_to_le32(dst);
 394
 395         tcd->attr = cpu_to_le16(attr);
 396
 397         tcd->soff = cpu_to_le16(soff);
 398
 399         tcd->nbytes = cpu_to_le32(nbytes);
 400         tcd->slast = cpu_to_le32(slast);
 401
 402         tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
 403         tcd->doff = cpu_to_le16(doff);
 404
 405         tcd->dlast_sga = cpu_to_le32(dlast_sga);
 406
 407         tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
 408         if (major_int)
 409                 csr |= EDMA_TCD_CSR_INT_MAJOR;
 410
 411         if (disable_req)
 412                 csr |= EDMA_TCD_CSR_D_REQ;
 413
 414         if (enable_sg)
 415                 csr |= EDMA_TCD_CSR_E_SG;
 416
 417         tcd->csr = cpu_to_le16(csr);
 418 }
 419
 420 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
 421                 int sg_len)
 422 {
 423         struct fsl_edma_desc *fsl_desc;
 424         int i;
 425
 426         fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT);
 427         if (!fsl_desc)
 428                 return NULL;
 429
 430         fsl_desc->echan = fsl_chan;
 431         fsl_desc->n_tcds = sg_len;
 432         for (i = 0; i < sg_len; i++) {
 433                 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
 434                                         GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
 435                 if (!fsl_desc->tcd[i].vtcd)
 436                         goto err;
 437         }
 438         return fsl_desc;
 439
 440 err:
 441         while (--i >= 0)
 442                 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
 443                                 fsl_desc->tcd[i].ptcd);
 444         kfree(fsl_desc);
 445         return NULL;
 446 }
 447
 448 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 449                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 450                 size_t period_len, enum dma_transfer_direction direction,
 451                 unsigned long flags)
 452 {
 453         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 454         struct fsl_edma_desc *fsl_desc;
 455         dma_addr_t dma_buf_next;
 456         int sg_len, i;
 457         u32 src_addr, dst_addr, last_sg, nbytes;
 458         u16 soff, doff, iter;
 459
 460         if (!is_slave_direction(direction))
 461                 return NULL;
 462
 463         if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
 464                 return NULL;
 465
 466         sg_len = buf_len / period_len;
 467         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 468         if (!fsl_desc)
 469                 return NULL;
 470         fsl_desc->iscyclic = true;
 471         fsl_desc->dirn = direction;
 472
 473         dma_buf_next = dma_addr;
 474         if (direction == DMA_MEM_TO_DEV) {
 475                 fsl_chan->attr =
 476                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 477                 nbytes = fsl_chan->cfg.dst_addr_width *
 478                         fsl_chan->cfg.dst_maxburst;
 479         } else {
 480                 fsl_chan->attr =
 481                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 482                 nbytes = fsl_chan->cfg.src_addr_width *
 483                         fsl_chan->cfg.src_maxburst;
 484         }
 485
 486         iter = period_len / nbytes;
 487
 488         for (i = 0; i < sg_len; i++) {
 489                 if (dma_buf_next >= dma_addr + buf_len)
 490                         dma_buf_next = dma_addr;
 491
 492                 /* get next sg's physical address */
 493                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 494
 495                 if (direction == DMA_MEM_TO_DEV) {
 496                         src_addr = dma_buf_next;
 497                         dst_addr = fsl_chan->dma_dev_addr;
 498                         soff = fsl_chan->cfg.dst_addr_width;
 499                         doff = 0;
 500                 } else {
 501                         src_addr = fsl_chan->dma_dev_addr;
 502                         dst_addr = dma_buf_next;
 503                         soff = 0;
 504                         doff = fsl_chan->cfg.src_addr_width;
 505                 }
 506
 507                 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
 508                                   fsl_chan->attr, soff, nbytes, 0, iter,
 509                                   iter, doff, last_sg, true, false, true);
 510                 dma_buf_next += period_len;
 511         }
 512
 513         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 514 }
 515
 516 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 517                 struct dma_chan *chan, struct scatterlist *sgl,
 518                 unsigned int sg_len, enum dma_transfer_direction direction,
 519                 unsigned long flags, void *context)
 520 {
 521         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 522         struct fsl_edma_desc *fsl_desc;
 523         struct scatterlist *sg;
 524         u32 src_addr, dst_addr, last_sg, nbytes;
 525         u16 soff, doff, iter;
 526         int i;
 527
 528         if (!is_slave_direction(direction))
 529                 return NULL;
 530
 531         if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
 532                 return NULL;
 533
 534         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 535         if (!fsl_desc)
 536                 return NULL;
 537         fsl_desc->iscyclic = false;
 538         fsl_desc->dirn = direction;
 539
 540         if (direction == DMA_MEM_TO_DEV) {
 541                 fsl_chan->attr =
 542                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 543                 nbytes = fsl_chan->cfg.dst_addr_width *
 544                         fsl_chan->cfg.dst_maxburst;
 545         } else {
 546                 fsl_chan->attr =
 547                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 548                 nbytes = fsl_chan->cfg.src_addr_width *
 549                         fsl_chan->cfg.src_maxburst;
 550         }
 551
 552         for_each_sg(sgl, sg, sg_len, i) {
 553                 if (direction == DMA_MEM_TO_DEV) {
 554                         src_addr = sg_dma_address(sg);
 555                         dst_addr = fsl_chan->dma_dev_addr;
 556                         soff = fsl_chan->cfg.dst_addr_width;
 557                         doff = 0;
 558                 } else {
 559                         src_addr = fsl_chan->dma_dev_addr;
 560                         dst_addr = sg_dma_address(sg);
 561                         soff = 0;
 562                         doff = fsl_chan->cfg.src_addr_width;
 563                 }
 564
 565                 iter = sg_dma_len(sg) / nbytes;
 566                 if (i < sg_len - 1) {
 567                         last_sg = fsl_desc->tcd[(i + 1)].ptcd;
 568                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 569                                           dst_addr, fsl_chan->attr, soff,
 570                                           nbytes, 0, iter, iter, doff, last_sg,
 571                                           false, false, true);
 572                 } else {
 573                         last_sg = 0;
 574                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 575                                           dst_addr, fsl_chan->attr, soff,
 576                                           nbytes, 0, iter, iter, doff, last_sg,
 577                                           true, true, false);
 578                 }
 579         }
 580
 581         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 582 }
 583
 584 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
 585                                                      dma_addr_t dma_dst, dma_addr_t dma_src,
 586                                                      size_t len, unsigned long flags)
 587 {
 588         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 589         struct fsl_edma_desc *fsl_desc;
 590
 591         fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1);
 592         if (!fsl_desc)
 593                 return NULL;
 594         fsl_desc->iscyclic = false;
 595
 596         fsl_chan->is_sw = true;
 597
 598         /* To match with copy_align and max_seg_size so 1 tcd is enough */
 599         fsl_edma_fill_tcd(fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
 600                         EDMA_TCD_ATTR_SSIZE_32BYTE | EDMA_TCD_ATTR_DSIZE_32BYTE,
 601                         32, len, 0, 1, 1, 32, 0, true, true, false);
 602
 603         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 604 }
 605
 606 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
 607 {
 608         struct virt_dma_desc *vdesc;
 609
 610         lockdep_assert_held(&fsl_chan->vchan.lock);
 611
 612         vdesc = vchan_next_desc(&fsl_chan->vchan);
 613         if (!vdesc)
 614                 return;
 615         fsl_chan->edesc = to_fsl_edma_desc(vdesc);
 616         fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
 617         fsl_edma_enable_request(fsl_chan);
 618         fsl_chan->status = DMA_IN_PROGRESS;
 619         fsl_chan->idle = false;
 620 }
 621
 622 void fsl_edma_issue_pending(struct dma_chan *chan)
 623 {
 624         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 625         unsigned long flags;
 626
 627         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 628
 629         if (unlikely(fsl_chan->pm_state != RUNNING)) {
 630                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 631                 /* cannot submit due to suspend */
 632                 return;
 633         }
 634
 635         if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
 636                 fsl_edma_xfer_desc(fsl_chan);
 637
 638         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 639 }
 640
 641 int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
 642 {
 643         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 644
 645         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
 646                                 sizeof(struct fsl_edma_hw_tcd),
 647                                 32, 0);
 648         return 0;
 649 }
 650
 651 void fsl_edma_free_chan_resources(struct dma_chan *chan)
 652 {
 653         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 654         struct fsl_edma_engine *edma = fsl_chan->edma;
 655         unsigned long flags;
 656         LIST_HEAD(head);
 657
 658         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 659         fsl_edma_disable_request(fsl_chan);
 660         if (edma->drvdata->dmamuxs)
 661                 fsl_edma_chan_mux(fsl_chan, 0, false);
 662         fsl_chan->edesc = NULL;
 663         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 664         fsl_edma_unprep_slave_dma(fsl_chan);
 665         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 666
 667         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 668         dma_pool_destroy(fsl_chan->tcd_pool);
 669         fsl_chan->tcd_pool = NULL;
 670         fsl_chan->is_sw = false;
 671 }
 672
 673 void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
 674 {
 675         struct fsl_edma_chan *chan, *_chan;
 676
 677         list_for_each_entry_safe(chan, _chan,
 678                                 &dmadev->channels, vchan.chan.device_node) {
 679                 list_del(&chan->vchan.chan.device_node);
 680                 tasklet_kill(&chan->vchan.task);
 681         }
 682 }
 683
 684 /*
 685  * On the 32 channels Vybrid/mpc577x edma version (here called "v1"),
 686  * register offsets are different compared to ColdFire mcf5441x 64 channels
 687  * edma (here called "v2").
 688  *
 689  * This function sets up register offsets as per proper declared version
 690  * so must be called in xxx_edma_probe() just after setting the
 691  * edma "version" and "membase" appropriately.
 692  */
 693 void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
 694 {
 695         edma->regs.cr = edma->membase + EDMA_CR;
 696         edma->regs.es = edma->membase + EDMA_ES;
 697         edma->regs.erql = edma->membase + EDMA_ERQ;
 698         edma->regs.eeil = edma->membase + EDMA_EEI;
 699
 700         edma->regs.serq = edma->membase + ((edma->drvdata->version == v2) ?
 701                         EDMA64_SERQ : EDMA_SERQ);
 702         edma->regs.cerq = edma->membase + ((edma->drvdata->version == v2) ?
 703                         EDMA64_CERQ : EDMA_CERQ);
 704         edma->regs.seei = edma->membase + ((edma->drvdata->version == v2) ?
 705                         EDMA64_SEEI : EDMA_SEEI);
 706         edma->regs.ceei = edma->membase + ((edma->drvdata->version == v2) ?
 707                         EDMA64_CEEI : EDMA_CEEI);
 708         edma->regs.cint = edma->membase + ((edma->drvdata->version == v2) ?
 709                         EDMA64_CINT : EDMA_CINT);
 710         edma->regs.cerr = edma->membase + ((edma->drvdata->version == v2) ?
 711                         EDMA64_CERR : EDMA_CERR);
 712         edma->regs.ssrt = edma->membase + ((edma->drvdata->version == v2) ?
 713                         EDMA64_SSRT : EDMA_SSRT);
 714         edma->regs.cdne = edma->membase + ((edma->drvdata->version == v2) ?
 715                         EDMA64_CDNE : EDMA_CDNE);
 716         edma->regs.intl = edma->membase + ((edma->drvdata->version == v2) ?
 717                         EDMA64_INTL : EDMA_INTR);
 718         edma->regs.errl = edma->membase + ((edma->drvdata->version == v2) ?
 719                         EDMA64_ERRL : EDMA_ERR);
 720
 721         if (edma->drvdata->version == v2) {
 722                 edma->regs.erqh = edma->membase + EDMA64_ERQH;
 723                 edma->regs.eeih = edma->membase + EDMA64_EEIH;
 724                 edma->regs.errh = edma->membase + EDMA64_ERRH;
 725                 edma->regs.inth = edma->membase + EDMA64_INTH;
 726         }
 727
 728         edma->regs.tcd = edma->membase + EDMA_TCD;
 729 }
 730
 731 MODULE_LICENSE("GPL v2");