2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include <linux/platform_data/edma.h>
29 #include "dmaengine.h"
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
50 * Max of 20 segments per channel to conserve PaRAM slots
51 * Also note that MAX_NR_SG should be atleast the no.of periods
52 * that are required for ASoC, otherwise DMA prep calls will
53 * fail. Today davinci-pcm is the only user of this driver and
54 * requires atleast 17 slots, so we setup the default to 20.
57 #define EDMA_MAX_SLOTS MAX_NR_SG
58 #define EDMA_DESCRIPTORS 16
61 struct virt_dma_desc vdesc;
62 struct list_head node;
67 struct edmacc_param pset[0];
73 struct virt_dma_chan vchan;
74 struct list_head node;
75 struct edma_desc *edesc;
79 int slot[EDMA_MAX_SLOTS];
81 struct dma_slave_config cfg;
86 struct dma_device dma_slave;
87 struct edma_chan slave_chans[EDMA_CHANS];
92 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
94 return container_of(d, struct edma_cc, dma_slave);
97 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
99 return container_of(c, struct edma_chan, vchan.chan);
102 static inline struct edma_desc
103 *to_edma_desc(struct dma_async_tx_descriptor *tx)
105 return container_of(tx, struct edma_desc, vdesc.tx);
108 static void edma_desc_free(struct virt_dma_desc *vdesc)
110 kfree(container_of(vdesc, struct edma_desc, vdesc));
113 /* Dispatch a queued descriptor to the controller (caller holds lock) */
114 static void edma_execute(struct edma_chan *echan)
116 struct virt_dma_desc *vdesc;
117 struct edma_desc *edesc;
118 struct device *dev = echan->vchan.chan.device->dev;
119 int i, j, left, nslots;
121 /* If either we processed all psets or we're still not started */
123 echan->edesc->pset_nr == echan->edesc->processed) {
125 vdesc = vchan_next_desc(&echan->vchan);
130 list_del(&vdesc->node);
131 echan->edesc = to_edma_desc(&vdesc->tx);
134 edesc = echan->edesc;
136 /* Find out how many left */
137 left = edesc->pset_nr - edesc->processed;
138 nslots = min(MAX_NR_SG, left);
140 /* Write descriptor PaRAM set(s) */
141 for (i = 0; i < nslots; i++) {
142 j = i + edesc->processed;
143 edma_write_slot(echan->slot[i], &edesc->pset[j]);
144 dev_dbg(echan->vchan.chan.device->dev,
156 j, echan->ch_num, echan->slot[i],
160 edesc->pset[j].a_b_cnt,
162 edesc->pset[j].src_dst_bidx,
163 edesc->pset[j].src_dst_cidx,
164 edesc->pset[j].link_bcntrld);
165 /* Link to the previous slot if not the last set */
166 if (i != (nslots - 1))
167 edma_link(echan->slot[i], echan->slot[i+1]);
170 edesc->processed += nslots;
173 * If this is either the last set in a set of SG-list transactions
174 * then setup a link to the dummy slot, this results in all future
175 * events being absorbed and that's OK because we're done
177 if (edesc->processed == edesc->pset_nr) {
179 edma_link(echan->slot[nslots-1], echan->slot[1]);
181 edma_link(echan->slot[nslots-1],
182 echan->ecc->dummy_slot);
185 if (edesc->processed <= MAX_NR_SG) {
186 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
187 edma_start(echan->ch_num);
189 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
190 echan->ch_num, edesc->processed);
191 edma_resume(echan->ch_num);
195 * This happens due to setup times between intermediate transfers
196 * in long SG lists which have to be broken up into transfers of
200 dev_dbg(dev, "missed event in execute detected\n");
201 edma_clean_channel(echan->ch_num);
202 edma_stop(echan->ch_num);
203 edma_start(echan->ch_num);
204 edma_trigger_channel(echan->ch_num);
209 static int edma_terminate_all(struct edma_chan *echan)
214 spin_lock_irqsave(&echan->vchan.lock, flags);
217 * Stop DMA activity: we assume the callback will not be called
218 * after edma_dma() returns (even if it does, it will see
219 * echan->edesc is NULL and exit.)
223 edma_stop(echan->ch_num);
226 vchan_get_all_descriptors(&echan->vchan, &head);
227 spin_unlock_irqrestore(&echan->vchan.lock, flags);
228 vchan_dma_desc_free_list(&echan->vchan, &head);
233 static int edma_slave_config(struct edma_chan *echan,
234 struct dma_slave_config *cfg)
236 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
237 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
240 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
245 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
249 struct dma_slave_config *config;
250 struct edma_chan *echan = to_edma_chan(chan);
253 case DMA_TERMINATE_ALL:
254 edma_terminate_all(echan);
256 case DMA_SLAVE_CONFIG:
257 config = (struct dma_slave_config *)arg;
258 ret = edma_slave_config(echan, config);
268 * A PaRAM set configuration abstraction used by other modes
269 * @chan: Channel who's PaRAM set we're configuring
270 * @pset: PaRAM set to initialize and setup.
271 * @src_addr: Source address of the DMA
272 * @dst_addr: Destination address of the DMA
273 * @burst: In units of dev_width, how much to send
274 * @dev_width: How much is the dev_width
275 * @dma_length: Total length of the DMA transfer
276 * @direction: Direction of the transfer
278 static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
279 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
280 enum dma_slave_buswidth dev_width, unsigned int dma_length,
281 enum dma_transfer_direction direction)
283 struct edma_chan *echan = to_edma_chan(chan);
284 struct device *dev = chan->device->dev;
285 int acnt, bcnt, ccnt, cidx;
286 int src_bidx, dst_bidx, src_cidx, dst_cidx;
291 * If the maxburst is equal to the fifo width, use
292 * A-synced transfers. This allows for large contiguous
293 * buffer transfers using only one PaRAM set.
297 * For the A-sync case, bcnt and ccnt are the remainder
298 * and quotient respectively of the division of:
299 * (dma_length / acnt) by (SZ_64K -1). This is so
300 * that in case bcnt over flows, we have ccnt to use.
301 * Note: In A-sync tranfer only, bcntrld is used, but it
302 * only applies for sg_dma_len(sg) >= SZ_64K.
303 * In this case, the best way adopted is- bccnt for the
304 * first frame will be the remainder below. Then for
305 * every successive frame, bcnt will be SZ_64K-1. This
306 * is assured as bcntrld = 0xffff in end of function.
309 ccnt = dma_length / acnt / (SZ_64K - 1);
310 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
312 * If bcnt is non-zero, we have a remainder and hence an
313 * extra frame to transfer, so increment ccnt.
322 * If maxburst is greater than the fifo address_width,
323 * use AB-synced transfers where A count is the fifo
324 * address_width and B count is the maxburst. In this
325 * case, we are limited to transfers of C count frames
326 * of (address_width * maxburst) where C count is limited
327 * to SZ_64K-1. This places an upper bound on the length
328 * of an SG segment that can be handled.
332 ccnt = dma_length / (acnt * bcnt);
333 if (ccnt > (SZ_64K - 1)) {
334 dev_err(dev, "Exceeded max SG segment size\n");
340 if (direction == DMA_MEM_TO_DEV) {
345 } else if (direction == DMA_DEV_TO_MEM) {
351 dev_err(dev, "%s: direction not implemented yet\n", __func__);
355 pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
356 /* Configure A or AB synchronized transfers */
358 pset->opt |= SYNCDIM;
360 pset->src = src_addr;
361 pset->dst = dst_addr;
363 pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
364 pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
366 pset->a_b_cnt = bcnt << 16 | acnt;
369 * Only time when (bcntrld) auto reload is required is for
370 * A-sync case, and in this case, a requirement of reload value
371 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
372 * and then later will be populated by edma_execute.
374 pset->link_bcntrld = 0xffffffff;
378 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
379 struct dma_chan *chan, struct scatterlist *sgl,
380 unsigned int sg_len, enum dma_transfer_direction direction,
381 unsigned long tx_flags, void *context)
383 struct edma_chan *echan = to_edma_chan(chan);
384 struct device *dev = chan->device->dev;
385 struct edma_desc *edesc;
386 dma_addr_t src_addr = 0, dst_addr = 0;
387 enum dma_slave_buswidth dev_width;
389 struct scatterlist *sg;
392 if (unlikely(!echan || !sgl || !sg_len))
395 if (direction == DMA_DEV_TO_MEM) {
396 src_addr = echan->cfg.src_addr;
397 dev_width = echan->cfg.src_addr_width;
398 burst = echan->cfg.src_maxburst;
399 } else if (direction == DMA_MEM_TO_DEV) {
400 dst_addr = echan->cfg.dst_addr;
401 dev_width = echan->cfg.dst_addr_width;
402 burst = echan->cfg.dst_maxburst;
404 dev_err(dev, "%s: bad direction?\n", __func__);
408 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
409 dev_err(dev, "Undefined slave buswidth\n");
413 edesc = kzalloc(sizeof(*edesc) + sg_len *
414 sizeof(edesc->pset[0]), GFP_ATOMIC);
416 dev_dbg(dev, "Failed to allocate a descriptor\n");
420 edesc->pset_nr = sg_len;
422 /* Allocate a PaRAM slot, if needed */
423 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
425 for (i = 0; i < nslots; i++) {
426 if (echan->slot[i] < 0) {
428 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
430 if (echan->slot[i] < 0) {
432 dev_err(dev, "Failed to allocate slot\n");
438 /* Configure PaRAM sets for each SG */
439 for_each_sg(sgl, sg, sg_len, i) {
440 /* Get address for each SG */
441 if (direction == DMA_DEV_TO_MEM)
442 dst_addr = sg_dma_address(sg);
444 src_addr = sg_dma_address(sg);
446 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
447 dst_addr, burst, dev_width,
448 sg_dma_len(sg), direction);
456 /* If this is the last in a current SG set of transactions,
457 enable interrupts so that next set is processed */
458 if (!((i+1) % MAX_NR_SG))
459 edesc->pset[i].opt |= TCINTEN;
461 /* If this is the last set, enable completion interrupt flag */
463 edesc->pset[i].opt |= TCINTEN;
466 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
469 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
470 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
471 size_t period_len, enum dma_transfer_direction direction,
472 unsigned long tx_flags, void *context)
474 struct edma_chan *echan = to_edma_chan(chan);
475 struct device *dev = chan->device->dev;
476 struct edma_desc *edesc;
477 dma_addr_t src_addr, dst_addr;
478 enum dma_slave_buswidth dev_width;
482 if (unlikely(!echan || !buf_len || !period_len))
485 if (direction == DMA_DEV_TO_MEM) {
486 src_addr = echan->cfg.src_addr;
488 dev_width = echan->cfg.src_addr_width;
489 burst = echan->cfg.src_maxburst;
490 } else if (direction == DMA_MEM_TO_DEV) {
492 dst_addr = echan->cfg.dst_addr;
493 dev_width = echan->cfg.dst_addr_width;
494 burst = echan->cfg.dst_maxburst;
496 dev_err(dev, "%s: bad direction?\n", __func__);
500 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
501 dev_err(dev, "Undefined slave buswidth\n");
505 if (unlikely(buf_len % period_len)) {
506 dev_err(dev, "Period should be multiple of Buffer length\n");
510 nslots = (buf_len / period_len) + 1;
513 * Cyclic DMA users such as audio cannot tolerate delays introduced
514 * by cases where the number of periods is more than the maximum
515 * number of SGs the EDMA driver can handle at a time. For DMA types
516 * such as Slave SGs, such delays are tolerable and synchronized,
517 * but the synchronization is difficult to achieve with Cyclic and
518 * cannot be guaranteed, so we error out early.
520 if (nslots > MAX_NR_SG)
523 edesc = kzalloc(sizeof(*edesc) + nslots *
524 sizeof(edesc->pset[0]), GFP_ATOMIC);
526 dev_dbg(dev, "Failed to allocate a descriptor\n");
531 edesc->pset_nr = nslots;
533 dev_dbg(dev, "%s: nslots=%d\n", __func__, nslots);
534 dev_dbg(dev, "%s: period_len=%d\n", __func__, period_len);
535 dev_dbg(dev, "%s: buf_len=%d\n", __func__, buf_len);
537 for (i = 0; i < nslots; i++) {
538 /* Allocate a PaRAM slot, if needed */
539 if (echan->slot[i] < 0) {
541 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
543 if (echan->slot[i] < 0) {
544 dev_err(dev, "Failed to allocate slot\n");
549 if (i == nslots - 1) {
550 memcpy(&edesc->pset[i], &edesc->pset[0],
551 sizeof(edesc->pset[0]));
555 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
556 dst_addr, burst, dev_width, period_len,
561 if (direction == DMA_DEV_TO_MEM)
562 dst_addr += period_len;
564 src_addr += period_len;
566 dev_dbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
579 i, echan->ch_num, echan->slot[i],
583 edesc->pset[i].a_b_cnt,
585 edesc->pset[i].src_dst_bidx,
586 edesc->pset[i].src_dst_cidx,
587 edesc->pset[i].link_bcntrld);
592 * Enable interrupts for every period because callback
593 * has to be called for every period.
595 edesc->pset[i].opt |= TCINTEN;
598 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
601 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
603 struct edma_chan *echan = data;
604 struct device *dev = echan->vchan.chan.device->dev;
605 struct edma_desc *edesc;
607 struct edmacc_param p;
609 edesc = echan->edesc;
611 /* Pause the channel for non-cyclic */
612 if (!edesc || (edesc && !edesc->cyclic))
613 edma_pause(echan->ch_num);
616 case EDMA_DMA_COMPLETE:
617 spin_lock_irqsave(&echan->vchan.lock, flags);
621 vchan_cyclic_callback(&edesc->vdesc);
622 } else if (edesc->processed == edesc->pset_nr) {
623 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
624 edma_stop(echan->ch_num);
625 vchan_cookie_complete(&edesc->vdesc);
628 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
633 spin_unlock_irqrestore(&echan->vchan.lock, flags);
636 case EDMA_DMA_CC_ERROR:
637 spin_lock_irqsave(&echan->vchan.lock, flags);
639 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
642 * Issue later based on missed flag which will be sure
644 * (1) we finished transmitting an intermediate slot and
645 * edma_execute is coming up.
646 * (2) or we finished current transfer and issue will
649 * Important note: issuing can be dangerous here and
650 * lead to some nasty recursion when we are in a NULL
651 * slot. So we avoid doing so and set the missed flag.
653 if (p.a_b_cnt == 0 && p.ccnt == 0) {
654 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
658 * The slot is already programmed but the event got
659 * missed, so its safe to issue it here.
661 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
662 edma_clean_channel(echan->ch_num);
663 edma_stop(echan->ch_num);
664 edma_start(echan->ch_num);
665 edma_trigger_channel(echan->ch_num);
668 spin_unlock_irqrestore(&echan->vchan.lock, flags);
676 /* Alloc channel resources */
677 static int edma_alloc_chan_resources(struct dma_chan *chan)
679 struct edma_chan *echan = to_edma_chan(chan);
680 struct device *dev = chan->device->dev;
685 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
686 chan, EVENTQ_DEFAULT);
693 if (a_ch_num != echan->ch_num) {
694 dev_err(dev, "failed to allocate requested channel %u:%u\n",
695 EDMA_CTLR(echan->ch_num),
696 EDMA_CHAN_SLOT(echan->ch_num));
701 echan->alloced = true;
702 echan->slot[0] = echan->ch_num;
704 dev_dbg(dev, "allocated channel for %u:%u\n",
705 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
710 edma_free_channel(a_ch_num);
715 /* Free channel resources */
716 static void edma_free_chan_resources(struct dma_chan *chan)
718 struct edma_chan *echan = to_edma_chan(chan);
719 struct device *dev = chan->device->dev;
722 /* Terminate transfers */
723 edma_stop(echan->ch_num);
725 vchan_free_chan_resources(&echan->vchan);
727 /* Free EDMA PaRAM slots */
728 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
729 if (echan->slot[i] >= 0) {
730 edma_free_slot(echan->slot[i]);
735 /* Free EDMA channel */
736 if (echan->alloced) {
737 edma_free_channel(echan->ch_num);
738 echan->alloced = false;
741 dev_dbg(dev, "freeing channel for %u\n", echan->ch_num);
744 /* Send pending descriptor to hardware */
745 static void edma_issue_pending(struct dma_chan *chan)
747 struct edma_chan *echan = to_edma_chan(chan);
750 spin_lock_irqsave(&echan->vchan.lock, flags);
751 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
753 spin_unlock_irqrestore(&echan->vchan.lock, flags);
756 static size_t edma_desc_size(struct edma_desc *edesc)
762 for (size = i = 0; i < edesc->pset_nr; i++)
763 size += (edesc->pset[i].a_b_cnt & 0xffff) *
764 (edesc->pset[i].a_b_cnt >> 16) *
767 size = (edesc->pset[0].a_b_cnt & 0xffff) *
768 (edesc->pset[0].a_b_cnt >> 16) +
769 (edesc->pset[0].a_b_cnt & 0xffff) *
770 (SZ_64K - 1) * edesc->pset[0].ccnt;
775 /* Check request completion status */
776 static enum dma_status edma_tx_status(struct dma_chan *chan,
778 struct dma_tx_state *txstate)
780 struct edma_chan *echan = to_edma_chan(chan);
781 struct virt_dma_desc *vdesc;
785 ret = dma_cookie_status(chan, cookie, txstate);
786 if (ret == DMA_COMPLETE || !txstate)
789 spin_lock_irqsave(&echan->vchan.lock, flags);
790 vdesc = vchan_find_desc(&echan->vchan, cookie);
792 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
793 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
794 struct edma_desc *edesc = echan->edesc;
795 txstate->residue = edma_desc_size(edesc);
797 spin_unlock_irqrestore(&echan->vchan.lock, flags);
802 static void __init edma_chan_init(struct edma_cc *ecc,
803 struct dma_device *dma,
804 struct edma_chan *echans)
808 for (i = 0; i < EDMA_CHANS; i++) {
809 struct edma_chan *echan = &echans[i];
810 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
812 echan->vchan.desc_free = edma_desc_free;
814 vchan_init(&echan->vchan, dma);
816 INIT_LIST_HEAD(&echan->node);
817 for (j = 0; j < EDMA_MAX_SLOTS; j++)
822 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
825 dma->device_prep_slave_sg = edma_prep_slave_sg;
826 dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
827 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
828 dma->device_free_chan_resources = edma_free_chan_resources;
829 dma->device_issue_pending = edma_issue_pending;
830 dma->device_tx_status = edma_tx_status;
831 dma->device_control = edma_control;
834 INIT_LIST_HEAD(&dma->channels);
837 static int edma_probe(struct platform_device *pdev)
842 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
846 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
848 dev_err(&pdev->dev, "Can't allocate controller\n");
852 ecc->ctlr = pdev->id;
853 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
854 if (ecc->dummy_slot < 0) {
855 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
859 dma_cap_zero(ecc->dma_slave.cap_mask);
860 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
862 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
864 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
866 ret = dma_async_device_register(&ecc->dma_slave);
870 platform_set_drvdata(pdev, ecc);
872 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
877 edma_free_slot(ecc->dummy_slot);
881 static int edma_remove(struct platform_device *pdev)
883 struct device *dev = &pdev->dev;
884 struct edma_cc *ecc = dev_get_drvdata(dev);
886 dma_async_device_unregister(&ecc->dma_slave);
887 edma_free_slot(ecc->dummy_slot);
892 static struct platform_driver edma_driver = {
894 .remove = edma_remove,
896 .name = "edma-dma-engine",
897 .owner = THIS_MODULE,
901 bool edma_filter_fn(struct dma_chan *chan, void *param)
903 if (chan->device->dev->driver == &edma_driver.driver) {
904 struct edma_chan *echan = to_edma_chan(chan);
905 unsigned ch_req = *(unsigned *)param;
906 return ch_req == echan->ch_num;
910 EXPORT_SYMBOL(edma_filter_fn);
912 static struct platform_device *pdev0, *pdev1;
914 static const struct platform_device_info edma_dev_info0 = {
915 .name = "edma-dma-engine",
917 .dma_mask = DMA_BIT_MASK(32),
920 static const struct platform_device_info edma_dev_info1 = {
921 .name = "edma-dma-engine",
923 .dma_mask = DMA_BIT_MASK(32),
926 static int edma_init(void)
928 int ret = platform_driver_register(&edma_driver);
931 pdev0 = platform_device_register_full(&edma_dev_info0);
933 platform_driver_unregister(&edma_driver);
934 ret = PTR_ERR(pdev0);
939 if (EDMA_CTLRS == 2) {
940 pdev1 = platform_device_register_full(&edma_dev_info1);
942 platform_driver_unregister(&edma_driver);
943 platform_device_unregister(pdev0);
944 ret = PTR_ERR(pdev1);
951 subsys_initcall(edma_init);
953 static void __exit edma_exit(void)
955 platform_device_unregister(pdev0);
957 platform_device_unregister(pdev1);
958 platform_driver_unregister(&edma_driver);
960 module_exit(edma_exit);
962 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
963 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
964 MODULE_LICENSE("GPL v2");