2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include <linux/platform_data/edma.h>
29 #include "dmaengine.h"
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
49 /* Max of 16 segments per channel to conserve PaRAM slots */
51 #define EDMA_MAX_SLOTS MAX_NR_SG
52 #define EDMA_DESCRIPTORS 16
55 struct virt_dma_desc vdesc;
56 struct list_head node;
60 struct edmacc_param pset[0];
66 struct virt_dma_chan vchan;
67 struct list_head node;
68 struct edma_desc *edesc;
72 int slot[EDMA_MAX_SLOTS];
74 struct dma_slave_config cfg;
79 struct dma_device dma_slave;
80 struct edma_chan slave_chans[EDMA_CHANS];
85 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
87 return container_of(d, struct edma_cc, dma_slave);
90 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
92 return container_of(c, struct edma_chan, vchan.chan);
95 static inline struct edma_desc
96 *to_edma_desc(struct dma_async_tx_descriptor *tx)
98 return container_of(tx, struct edma_desc, vdesc.tx);
101 static void edma_desc_free(struct virt_dma_desc *vdesc)
103 kfree(container_of(vdesc, struct edma_desc, vdesc));
106 /* Dispatch a queued descriptor to the controller (caller holds lock) */
107 static void edma_execute(struct edma_chan *echan)
109 struct virt_dma_desc *vdesc;
110 struct edma_desc *edesc;
111 struct device *dev = echan->vchan.chan.device->dev;
112 int i, j, left, nslots;
114 /* If either we processed all psets or we're still not started */
116 echan->edesc->pset_nr == echan->edesc->processed) {
118 vdesc = vchan_next_desc(&echan->vchan);
123 list_del(&vdesc->node);
124 echan->edesc = to_edma_desc(&vdesc->tx);
127 edesc = echan->edesc;
129 /* Find out how many left */
130 left = edesc->pset_nr - edesc->processed;
131 nslots = min(MAX_NR_SG, left);
133 /* Write descriptor PaRAM set(s) */
134 for (i = 0; i < nslots; i++) {
135 j = i + edesc->processed;
136 edma_write_slot(echan->slot[i], &edesc->pset[j]);
137 dev_dbg(echan->vchan.chan.device->dev,
149 j, echan->ch_num, echan->slot[i],
153 edesc->pset[j].a_b_cnt,
155 edesc->pset[j].src_dst_bidx,
156 edesc->pset[j].src_dst_cidx,
157 edesc->pset[j].link_bcntrld);
158 /* Link to the previous slot if not the last set */
159 if (i != (nslots - 1))
160 edma_link(echan->slot[i], echan->slot[i+1]);
163 edesc->processed += nslots;
166 * If this is either the last set in a set of SG-list transactions
167 * then setup a link to the dummy slot, this results in all future
168 * events being absorbed and that's OK because we're done
170 if (edesc->processed == edesc->pset_nr)
171 edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot);
173 edma_resume(echan->ch_num);
175 if (edesc->processed <= MAX_NR_SG) {
176 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
177 edma_start(echan->ch_num);
181 * This happens due to setup times between intermediate transfers
182 * in long SG lists which have to be broken up into transfers of
186 dev_dbg(dev, "missed event in execute detected\n");
187 edma_clean_channel(echan->ch_num);
188 edma_stop(echan->ch_num);
189 edma_start(echan->ch_num);
190 edma_trigger_channel(echan->ch_num);
195 static int edma_terminate_all(struct edma_chan *echan)
200 spin_lock_irqsave(&echan->vchan.lock, flags);
203 * Stop DMA activity: we assume the callback will not be called
204 * after edma_dma() returns (even if it does, it will see
205 * echan->edesc is NULL and exit.)
209 edma_stop(echan->ch_num);
212 vchan_get_all_descriptors(&echan->vchan, &head);
213 spin_unlock_irqrestore(&echan->vchan.lock, flags);
214 vchan_dma_desc_free_list(&echan->vchan, &head);
219 static int edma_slave_config(struct edma_chan *echan,
220 struct dma_slave_config *cfg)
222 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
223 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
226 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
231 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
235 struct dma_slave_config *config;
236 struct edma_chan *echan = to_edma_chan(chan);
239 case DMA_TERMINATE_ALL:
240 edma_terminate_all(echan);
242 case DMA_SLAVE_CONFIG:
243 config = (struct dma_slave_config *)arg;
244 ret = edma_slave_config(echan, config);
253 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
254 struct dma_chan *chan, struct scatterlist *sgl,
255 unsigned int sg_len, enum dma_transfer_direction direction,
256 unsigned long tx_flags, void *context)
258 struct edma_chan *echan = to_edma_chan(chan);
259 struct device *dev = chan->device->dev;
260 struct edma_desc *edesc;
262 enum dma_slave_buswidth dev_width;
264 struct scatterlist *sg;
265 int acnt, bcnt, ccnt, src, dst, cidx;
266 int src_bidx, dst_bidx, src_cidx, dst_cidx;
269 if (unlikely(!echan || !sgl || !sg_len))
272 if (direction == DMA_DEV_TO_MEM) {
273 dev_addr = echan->cfg.src_addr;
274 dev_width = echan->cfg.src_addr_width;
275 burst = echan->cfg.src_maxburst;
276 } else if (direction == DMA_MEM_TO_DEV) {
277 dev_addr = echan->cfg.dst_addr;
278 dev_width = echan->cfg.dst_addr_width;
279 burst = echan->cfg.dst_maxburst;
281 dev_err(dev, "%s: bad direction?\n", __func__);
285 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
286 dev_err(dev, "Undefined slave buswidth\n");
290 edesc = kzalloc(sizeof(*edesc) + sg_len *
291 sizeof(edesc->pset[0]), GFP_ATOMIC);
293 dev_dbg(dev, "Failed to allocate a descriptor\n");
297 edesc->pset_nr = sg_len;
299 /* Allocate a PaRAM slot, if needed */
300 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
302 for (i = 0; i < nslots; i++) {
303 if (echan->slot[i] < 0) {
305 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
307 if (echan->slot[i] < 0) {
308 dev_err(dev, "Failed to allocate slot\n");
314 /* Configure PaRAM sets for each SG */
315 for_each_sg(sgl, sg, sg_len, i) {
320 * If the maxburst is equal to the fifo width, use
321 * A-synced transfers. This allows for large contiguous
322 * buffer transfers using only one PaRAM set.
325 edesc->absync = false;
326 ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
327 bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
334 * If maxburst is greater than the fifo address_width,
335 * use AB-synced transfers where A count is the fifo
336 * address_width and B count is the maxburst. In this
337 * case, we are limited to transfers of C count frames
338 * of (address_width * maxburst) where C count is limited
339 * to SZ_64K-1. This places an upper bound on the length
340 * of an SG segment that can be handled.
343 edesc->absync = true;
345 ccnt = sg_dma_len(sg) / (acnt * bcnt);
346 if (ccnt > (SZ_64K - 1)) {
347 dev_err(dev, "Exceeded max SG segment size\n");
353 if (direction == DMA_MEM_TO_DEV) {
354 src = sg_dma_address(sg);
362 dst = sg_dma_address(sg);
369 edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
370 /* Configure A or AB synchronized transfers */
372 edesc->pset[i].opt |= SYNCDIM;
374 /* If this is the last in a current SG set of transactions,
375 enable interrupts so that next set is processed */
376 if (!((i+1) % MAX_NR_SG))
377 edesc->pset[i].opt |= TCINTEN;
379 /* If this is the last set, enable completion interrupt flag */
381 edesc->pset[i].opt |= TCINTEN;
383 edesc->pset[i].src = src;
384 edesc->pset[i].dst = dst;
386 edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
387 edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
389 edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
390 edesc->pset[i].ccnt = ccnt;
391 edesc->pset[i].link_bcntrld = 0xffffffff;
395 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
398 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
400 struct edma_chan *echan = data;
401 struct device *dev = echan->vchan.chan.device->dev;
402 struct edma_desc *edesc;
404 struct edmacc_param p;
406 /* Pause the channel */
407 edma_pause(echan->ch_num);
411 spin_lock_irqsave(&echan->vchan.lock, flags);
413 edesc = echan->edesc;
415 if (edesc->processed == edesc->pset_nr) {
416 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
417 edma_stop(echan->ch_num);
418 vchan_cookie_complete(&edesc->vdesc);
420 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
426 spin_unlock_irqrestore(&echan->vchan.lock, flags);
430 spin_lock_irqsave(&echan->vchan.lock, flags);
432 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
435 * Issue later based on missed flag which will be sure
437 * (1) we finished transmitting an intermediate slot and
438 * edma_execute is coming up.
439 * (2) or we finished current transfer and issue will
442 * Important note: issuing can be dangerous here and
443 * lead to some nasty recursion when we are in a NULL
444 * slot. So we avoid doing so and set the missed flag.
446 if (p.a_b_cnt == 0 && p.ccnt == 0) {
447 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
451 * The slot is already programmed but the event got
452 * missed, so its safe to issue it here.
454 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
455 edma_clean_channel(echan->ch_num);
456 edma_stop(echan->ch_num);
457 edma_start(echan->ch_num);
458 edma_trigger_channel(echan->ch_num);
461 spin_unlock_irqrestore(&echan->vchan.lock, flags);
469 /* Alloc channel resources */
470 static int edma_alloc_chan_resources(struct dma_chan *chan)
472 struct edma_chan *echan = to_edma_chan(chan);
473 struct device *dev = chan->device->dev;
478 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
479 chan, EVENTQ_DEFAULT);
486 if (a_ch_num != echan->ch_num) {
487 dev_err(dev, "failed to allocate requested channel %u:%u\n",
488 EDMA_CTLR(echan->ch_num),
489 EDMA_CHAN_SLOT(echan->ch_num));
494 echan->alloced = true;
495 echan->slot[0] = echan->ch_num;
497 dev_info(dev, "allocated channel for %u:%u\n",
498 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
503 edma_free_channel(a_ch_num);
508 /* Free channel resources */
509 static void edma_free_chan_resources(struct dma_chan *chan)
511 struct edma_chan *echan = to_edma_chan(chan);
512 struct device *dev = chan->device->dev;
515 /* Terminate transfers */
516 edma_stop(echan->ch_num);
518 vchan_free_chan_resources(&echan->vchan);
520 /* Free EDMA PaRAM slots */
521 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
522 if (echan->slot[i] >= 0) {
523 edma_free_slot(echan->slot[i]);
528 /* Free EDMA channel */
529 if (echan->alloced) {
530 edma_free_channel(echan->ch_num);
531 echan->alloced = false;
534 dev_info(dev, "freeing channel for %u\n", echan->ch_num);
537 /* Send pending descriptor to hardware */
538 static void edma_issue_pending(struct dma_chan *chan)
540 struct edma_chan *echan = to_edma_chan(chan);
543 spin_lock_irqsave(&echan->vchan.lock, flags);
544 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
546 spin_unlock_irqrestore(&echan->vchan.lock, flags);
549 static size_t edma_desc_size(struct edma_desc *edesc)
555 for (size = i = 0; i < edesc->pset_nr; i++)
556 size += (edesc->pset[i].a_b_cnt & 0xffff) *
557 (edesc->pset[i].a_b_cnt >> 16) *
560 size = (edesc->pset[0].a_b_cnt & 0xffff) *
561 (edesc->pset[0].a_b_cnt >> 16) +
562 (edesc->pset[0].a_b_cnt & 0xffff) *
563 (SZ_64K - 1) * edesc->pset[0].ccnt;
568 /* Check request completion status */
569 static enum dma_status edma_tx_status(struct dma_chan *chan,
571 struct dma_tx_state *txstate)
573 struct edma_chan *echan = to_edma_chan(chan);
574 struct virt_dma_desc *vdesc;
578 ret = dma_cookie_status(chan, cookie, txstate);
579 if (ret == DMA_COMPLETE || !txstate)
582 spin_lock_irqsave(&echan->vchan.lock, flags);
583 vdesc = vchan_find_desc(&echan->vchan, cookie);
585 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
586 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
587 struct edma_desc *edesc = echan->edesc;
588 txstate->residue = edma_desc_size(edesc);
590 spin_unlock_irqrestore(&echan->vchan.lock, flags);
595 static void __init edma_chan_init(struct edma_cc *ecc,
596 struct dma_device *dma,
597 struct edma_chan *echans)
601 for (i = 0; i < EDMA_CHANS; i++) {
602 struct edma_chan *echan = &echans[i];
603 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
605 echan->vchan.desc_free = edma_desc_free;
607 vchan_init(&echan->vchan, dma);
609 INIT_LIST_HEAD(&echan->node);
610 for (j = 0; j < EDMA_MAX_SLOTS; j++)
615 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
618 dma->device_prep_slave_sg = edma_prep_slave_sg;
619 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
620 dma->device_free_chan_resources = edma_free_chan_resources;
621 dma->device_issue_pending = edma_issue_pending;
622 dma->device_tx_status = edma_tx_status;
623 dma->device_control = edma_control;
626 INIT_LIST_HEAD(&dma->channels);
629 static int edma_probe(struct platform_device *pdev)
634 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
636 dev_err(&pdev->dev, "Can't allocate controller\n");
640 ecc->ctlr = pdev->id;
641 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
642 if (ecc->dummy_slot < 0) {
643 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
647 dma_cap_zero(ecc->dma_slave.cap_mask);
648 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
650 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
652 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
654 ret = dma_async_device_register(&ecc->dma_slave);
658 platform_set_drvdata(pdev, ecc);
660 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
665 edma_free_slot(ecc->dummy_slot);
669 static int edma_remove(struct platform_device *pdev)
671 struct device *dev = &pdev->dev;
672 struct edma_cc *ecc = dev_get_drvdata(dev);
674 dma_async_device_unregister(&ecc->dma_slave);
675 edma_free_slot(ecc->dummy_slot);
680 static struct platform_driver edma_driver = {
682 .remove = edma_remove,
684 .name = "edma-dma-engine",
685 .owner = THIS_MODULE,
689 bool edma_filter_fn(struct dma_chan *chan, void *param)
691 if (chan->device->dev->driver == &edma_driver.driver) {
692 struct edma_chan *echan = to_edma_chan(chan);
693 unsigned ch_req = *(unsigned *)param;
694 return ch_req == echan->ch_num;
698 EXPORT_SYMBOL(edma_filter_fn);
700 static struct platform_device *pdev0, *pdev1;
702 static const struct platform_device_info edma_dev_info0 = {
703 .name = "edma-dma-engine",
707 static const struct platform_device_info edma_dev_info1 = {
708 .name = "edma-dma-engine",
712 static int edma_init(void)
714 int ret = platform_driver_register(&edma_driver);
717 pdev0 = platform_device_register_full(&edma_dev_info0);
719 platform_driver_unregister(&edma_driver);
720 ret = PTR_ERR(pdev0);
723 pdev0->dev.dma_mask = &pdev0->dev.coherent_dma_mask;
724 pdev0->dev.coherent_dma_mask = DMA_BIT_MASK(32);
727 if (EDMA_CTLRS == 2) {
728 pdev1 = platform_device_register_full(&edma_dev_info1);
730 platform_driver_unregister(&edma_driver);
731 platform_device_unregister(pdev0);
732 ret = PTR_ERR(pdev1);
734 pdev1->dev.dma_mask = &pdev1->dev.coherent_dma_mask;
735 pdev1->dev.coherent_dma_mask = DMA_BIT_MASK(32);
741 subsys_initcall(edma_init);
743 static void __exit edma_exit(void)
745 platform_device_unregister(pdev0);
747 platform_device_unregister(pdev1);
748 platform_driver_unregister(&edma_driver);
750 module_exit(edma_exit);
752 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
753 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
754 MODULE_LICENSE("GPL v2");