2 * TI EDMA DMA engine driver
4 * Copyright 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/dmaengine.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include <linux/platform_data/edma.h>
29 #include "dmaengine.h"
33 * This will go away when the private EDMA API is folded
34 * into this driver and the platform device(s) are
35 * instantiated in the arch code. We can only get away
36 * with this simplification because DA8XX may not be built
37 * in the same kernel image with other DaVinci parts. This
38 * avoids having to sprinkle dmaengine driver platform devices
39 * and data throughout all the existing board files.
41 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
47 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */
49 /* Max of 16 segments per channel to conserve PaRAM slots */
51 #define EDMA_MAX_SLOTS MAX_NR_SG
52 #define EDMA_DESCRIPTORS 16
55 struct virt_dma_desc vdesc;
56 struct list_head node;
60 struct edmacc_param pset[0];
66 struct virt_dma_chan vchan;
67 struct list_head node;
68 struct edma_desc *edesc;
72 int slot[EDMA_MAX_SLOTS];
74 struct dma_slave_config cfg;
79 struct dma_device dma_slave;
80 struct edma_chan slave_chans[EDMA_CHANS];
85 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
87 return container_of(d, struct edma_cc, dma_slave);
90 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
92 return container_of(c, struct edma_chan, vchan.chan);
95 static inline struct edma_desc
96 *to_edma_desc(struct dma_async_tx_descriptor *tx)
98 return container_of(tx, struct edma_desc, vdesc.tx);
101 static void edma_desc_free(struct virt_dma_desc *vdesc)
103 kfree(container_of(vdesc, struct edma_desc, vdesc));
106 /* Dispatch a queued descriptor to the controller (caller holds lock) */
107 static void edma_execute(struct edma_chan *echan)
109 struct virt_dma_desc *vdesc;
110 struct edma_desc *edesc;
111 struct device *dev = echan->vchan.chan.device->dev;
112 int i, j, left, nslots;
114 /* If either we processed all psets or we're still not started */
116 echan->edesc->pset_nr == echan->edesc->processed) {
118 vdesc = vchan_next_desc(&echan->vchan);
123 list_del(&vdesc->node);
124 echan->edesc = to_edma_desc(&vdesc->tx);
127 edesc = echan->edesc;
129 /* Find out how many left */
130 left = edesc->pset_nr - edesc->processed;
131 nslots = min(MAX_NR_SG, left);
133 /* Write descriptor PaRAM set(s) */
134 for (i = 0; i < nslots; i++) {
135 j = i + edesc->processed;
136 edma_write_slot(echan->slot[i], &edesc->pset[j]);
137 dev_dbg(echan->vchan.chan.device->dev,
149 j, echan->ch_num, echan->slot[i],
153 edesc->pset[j].a_b_cnt,
155 edesc->pset[j].src_dst_bidx,
156 edesc->pset[j].src_dst_cidx,
157 edesc->pset[j].link_bcntrld);
158 /* Link to the previous slot if not the last set */
159 if (i != (nslots - 1))
160 edma_link(echan->slot[i], echan->slot[i+1]);
163 edesc->processed += nslots;
166 * If this is either the last set in a set of SG-list transactions
167 * then setup a link to the dummy slot, this results in all future
168 * events being absorbed and that's OK because we're done
170 if (edesc->processed == edesc->pset_nr)
171 edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot);
173 edma_resume(echan->ch_num);
175 if (edesc->processed <= MAX_NR_SG) {
176 dev_dbg(dev, "first transfer starting %d\n", echan->ch_num);
177 edma_start(echan->ch_num);
181 * This happens due to setup times between intermediate transfers
182 * in long SG lists which have to be broken up into transfers of
186 dev_dbg(dev, "missed event in execute detected\n");
187 edma_clean_channel(echan->ch_num);
188 edma_stop(echan->ch_num);
189 edma_start(echan->ch_num);
190 edma_trigger_channel(echan->ch_num);
195 static int edma_terminate_all(struct edma_chan *echan)
200 spin_lock_irqsave(&echan->vchan.lock, flags);
203 * Stop DMA activity: we assume the callback will not be called
204 * after edma_dma() returns (even if it does, it will see
205 * echan->edesc is NULL and exit.)
209 edma_stop(echan->ch_num);
212 vchan_get_all_descriptors(&echan->vchan, &head);
213 spin_unlock_irqrestore(&echan->vchan.lock, flags);
214 vchan_dma_desc_free_list(&echan->vchan, &head);
219 static int edma_slave_config(struct edma_chan *echan,
220 struct dma_slave_config *cfg)
222 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
223 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
226 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
231 static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
235 struct dma_slave_config *config;
236 struct edma_chan *echan = to_edma_chan(chan);
239 case DMA_TERMINATE_ALL:
240 edma_terminate_all(echan);
242 case DMA_SLAVE_CONFIG:
243 config = (struct dma_slave_config *)arg;
244 ret = edma_slave_config(echan, config);
253 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
254 struct dma_chan *chan, struct scatterlist *sgl,
255 unsigned int sg_len, enum dma_transfer_direction direction,
256 unsigned long tx_flags, void *context)
258 struct edma_chan *echan = to_edma_chan(chan);
259 struct device *dev = chan->device->dev;
260 struct edma_desc *edesc;
262 enum dma_slave_buswidth dev_width;
264 struct scatterlist *sg;
265 int acnt, bcnt, ccnt, src, dst, cidx;
266 int src_bidx, dst_bidx, src_cidx, dst_cidx;
269 if (unlikely(!echan || !sgl || !sg_len))
272 if (direction == DMA_DEV_TO_MEM) {
273 dev_addr = echan->cfg.src_addr;
274 dev_width = echan->cfg.src_addr_width;
275 burst = echan->cfg.src_maxburst;
276 } else if (direction == DMA_MEM_TO_DEV) {
277 dev_addr = echan->cfg.dst_addr;
278 dev_width = echan->cfg.dst_addr_width;
279 burst = echan->cfg.dst_maxburst;
281 dev_err(dev, "%s: bad direction?\n", __func__);
285 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
286 dev_err(dev, "Undefined slave buswidth\n");
290 edesc = kzalloc(sizeof(*edesc) + sg_len *
291 sizeof(edesc->pset[0]), GFP_ATOMIC);
293 dev_dbg(dev, "Failed to allocate a descriptor\n");
297 edesc->pset_nr = sg_len;
299 /* Allocate a PaRAM slot, if needed */
300 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
302 for (i = 0; i < nslots; i++) {
303 if (echan->slot[i] < 0) {
305 edma_alloc_slot(EDMA_CTLR(echan->ch_num),
307 if (echan->slot[i] < 0) {
309 dev_err(dev, "Failed to allocate slot\n");
316 /* Configure PaRAM sets for each SG */
317 for_each_sg(sgl, sg, sg_len, i) {
322 * If the maxburst is equal to the fifo width, use
323 * A-synced transfers. This allows for large contiguous
324 * buffer transfers using only one PaRAM set.
327 edesc->absync = false;
328 ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
329 bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
336 * If maxburst is greater than the fifo address_width,
337 * use AB-synced transfers where A count is the fifo
338 * address_width and B count is the maxburst. In this
339 * case, we are limited to transfers of C count frames
340 * of (address_width * maxburst) where C count is limited
341 * to SZ_64K-1. This places an upper bound on the length
342 * of an SG segment that can be handled.
345 edesc->absync = true;
347 ccnt = sg_dma_len(sg) / (acnt * bcnt);
348 if (ccnt > (SZ_64K - 1)) {
349 dev_err(dev, "Exceeded max SG segment size\n");
356 if (direction == DMA_MEM_TO_DEV) {
357 src = sg_dma_address(sg);
365 dst = sg_dma_address(sg);
372 edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
373 /* Configure A or AB synchronized transfers */
375 edesc->pset[i].opt |= SYNCDIM;
377 /* If this is the last in a current SG set of transactions,
378 enable interrupts so that next set is processed */
379 if (!((i+1) % MAX_NR_SG))
380 edesc->pset[i].opt |= TCINTEN;
382 /* If this is the last set, enable completion interrupt flag */
384 edesc->pset[i].opt |= TCINTEN;
386 edesc->pset[i].src = src;
387 edesc->pset[i].dst = dst;
389 edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
390 edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
392 edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
393 edesc->pset[i].ccnt = ccnt;
394 edesc->pset[i].link_bcntrld = 0xffffffff;
398 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
401 static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
403 struct edma_chan *echan = data;
404 struct device *dev = echan->vchan.chan.device->dev;
405 struct edma_desc *edesc;
407 struct edmacc_param p;
409 /* Pause the channel */
410 edma_pause(echan->ch_num);
414 spin_lock_irqsave(&echan->vchan.lock, flags);
416 edesc = echan->edesc;
418 if (edesc->processed == edesc->pset_nr) {
419 dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
420 edma_stop(echan->ch_num);
421 vchan_cookie_complete(&edesc->vdesc);
423 dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
429 spin_unlock_irqrestore(&echan->vchan.lock, flags);
433 spin_lock_irqsave(&echan->vchan.lock, flags);
435 edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
438 * Issue later based on missed flag which will be sure
440 * (1) we finished transmitting an intermediate slot and
441 * edma_execute is coming up.
442 * (2) or we finished current transfer and issue will
445 * Important note: issuing can be dangerous here and
446 * lead to some nasty recursion when we are in a NULL
447 * slot. So we avoid doing so and set the missed flag.
449 if (p.a_b_cnt == 0 && p.ccnt == 0) {
450 dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n");
454 * The slot is already programmed but the event got
455 * missed, so its safe to issue it here.
457 dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
458 edma_clean_channel(echan->ch_num);
459 edma_stop(echan->ch_num);
460 edma_start(echan->ch_num);
461 edma_trigger_channel(echan->ch_num);
464 spin_unlock_irqrestore(&echan->vchan.lock, flags);
472 /* Alloc channel resources */
473 static int edma_alloc_chan_resources(struct dma_chan *chan)
475 struct edma_chan *echan = to_edma_chan(chan);
476 struct device *dev = chan->device->dev;
481 a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
482 chan, EVENTQ_DEFAULT);
489 if (a_ch_num != echan->ch_num) {
490 dev_err(dev, "failed to allocate requested channel %u:%u\n",
491 EDMA_CTLR(echan->ch_num),
492 EDMA_CHAN_SLOT(echan->ch_num));
497 echan->alloced = true;
498 echan->slot[0] = echan->ch_num;
500 dev_info(dev, "allocated channel for %u:%u\n",
501 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
506 edma_free_channel(a_ch_num);
511 /* Free channel resources */
512 static void edma_free_chan_resources(struct dma_chan *chan)
514 struct edma_chan *echan = to_edma_chan(chan);
515 struct device *dev = chan->device->dev;
518 /* Terminate transfers */
519 edma_stop(echan->ch_num);
521 vchan_free_chan_resources(&echan->vchan);
523 /* Free EDMA PaRAM slots */
524 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
525 if (echan->slot[i] >= 0) {
526 edma_free_slot(echan->slot[i]);
531 /* Free EDMA channel */
532 if (echan->alloced) {
533 edma_free_channel(echan->ch_num);
534 echan->alloced = false;
537 dev_info(dev, "freeing channel for %u\n", echan->ch_num);
540 /* Send pending descriptor to hardware */
541 static void edma_issue_pending(struct dma_chan *chan)
543 struct edma_chan *echan = to_edma_chan(chan);
546 spin_lock_irqsave(&echan->vchan.lock, flags);
547 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
549 spin_unlock_irqrestore(&echan->vchan.lock, flags);
552 static size_t edma_desc_size(struct edma_desc *edesc)
558 for (size = i = 0; i < edesc->pset_nr; i++)
559 size += (edesc->pset[i].a_b_cnt & 0xffff) *
560 (edesc->pset[i].a_b_cnt >> 16) *
563 size = (edesc->pset[0].a_b_cnt & 0xffff) *
564 (edesc->pset[0].a_b_cnt >> 16) +
565 (edesc->pset[0].a_b_cnt & 0xffff) *
566 (SZ_64K - 1) * edesc->pset[0].ccnt;
571 /* Check request completion status */
572 static enum dma_status edma_tx_status(struct dma_chan *chan,
574 struct dma_tx_state *txstate)
576 struct edma_chan *echan = to_edma_chan(chan);
577 struct virt_dma_desc *vdesc;
581 ret = dma_cookie_status(chan, cookie, txstate);
582 if (ret == DMA_SUCCESS || !txstate)
585 spin_lock_irqsave(&echan->vchan.lock, flags);
586 vdesc = vchan_find_desc(&echan->vchan, cookie);
588 txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx));
589 } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) {
590 struct edma_desc *edesc = echan->edesc;
591 txstate->residue = edma_desc_size(edesc);
593 spin_unlock_irqrestore(&echan->vchan.lock, flags);
598 static void __init edma_chan_init(struct edma_cc *ecc,
599 struct dma_device *dma,
600 struct edma_chan *echans)
604 for (i = 0; i < EDMA_CHANS; i++) {
605 struct edma_chan *echan = &echans[i];
606 echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i);
608 echan->vchan.desc_free = edma_desc_free;
610 vchan_init(&echan->vchan, dma);
612 INIT_LIST_HEAD(&echan->node);
613 for (j = 0; j < EDMA_MAX_SLOTS; j++)
618 static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
621 dma->device_prep_slave_sg = edma_prep_slave_sg;
622 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
623 dma->device_free_chan_resources = edma_free_chan_resources;
624 dma->device_issue_pending = edma_issue_pending;
625 dma->device_tx_status = edma_tx_status;
626 dma->device_control = edma_control;
629 INIT_LIST_HEAD(&dma->channels);
632 static int edma_probe(struct platform_device *pdev)
637 ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL);
639 dev_err(&pdev->dev, "Can't allocate controller\n");
643 ecc->ctlr = pdev->id;
644 ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
645 if (ecc->dummy_slot < 0) {
646 dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
650 dma_cap_zero(ecc->dma_slave.cap_mask);
651 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
653 edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev);
655 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
657 ret = dma_async_device_register(&ecc->dma_slave);
661 platform_set_drvdata(pdev, ecc);
663 dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
668 edma_free_slot(ecc->dummy_slot);
672 static int edma_remove(struct platform_device *pdev)
674 struct device *dev = &pdev->dev;
675 struct edma_cc *ecc = dev_get_drvdata(dev);
677 dma_async_device_unregister(&ecc->dma_slave);
678 edma_free_slot(ecc->dummy_slot);
683 static struct platform_driver edma_driver = {
685 .remove = edma_remove,
687 .name = "edma-dma-engine",
688 .owner = THIS_MODULE,
692 bool edma_filter_fn(struct dma_chan *chan, void *param)
694 if (chan->device->dev->driver == &edma_driver.driver) {
695 struct edma_chan *echan = to_edma_chan(chan);
696 unsigned ch_req = *(unsigned *)param;
697 return ch_req == echan->ch_num;
701 EXPORT_SYMBOL(edma_filter_fn);
703 static struct platform_device *pdev0, *pdev1;
705 static const struct platform_device_info edma_dev_info0 = {
706 .name = "edma-dma-engine",
710 static const struct platform_device_info edma_dev_info1 = {
711 .name = "edma-dma-engine",
715 static int edma_init(void)
717 int ret = platform_driver_register(&edma_driver);
720 pdev0 = platform_device_register_full(&edma_dev_info0);
722 platform_driver_unregister(&edma_driver);
723 ret = PTR_ERR(pdev0);
726 pdev0->dev.dma_mask = &pdev0->dev.coherent_dma_mask;
727 pdev0->dev.coherent_dma_mask = DMA_BIT_MASK(32);
730 if (EDMA_CTLRS == 2) {
731 pdev1 = platform_device_register_full(&edma_dev_info1);
733 platform_driver_unregister(&edma_driver);
734 platform_device_unregister(pdev0);
735 ret = PTR_ERR(pdev1);
737 pdev1->dev.dma_mask = &pdev1->dev.coherent_dma_mask;
738 pdev1->dev.coherent_dma_mask = DMA_BIT_MASK(32);
744 subsys_initcall(edma_init);
746 static void __exit edma_exit(void)
748 platform_device_unregister(pdev0);
750 platform_device_unregister(pdev1);
751 platform_driver_unregister(&edma_driver);
753 module_exit(edma_exit);
755 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
756 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
757 MODULE_LICENSE("GPL v2");