1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA v0 core
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
9 #include <linux/bitfield.h>
11 #include "dw-edma-core.h"
12 #include "dw-edma-v0-core.h"
13 #include "dw-edma-v0-regs.h"
14 #include "dw-edma-v0-debugfs.h"
16 enum dw_edma_control {
17 DW_EDMA_V0_CB = BIT(0),
18 DW_EDMA_V0_TCB = BIT(1),
19 DW_EDMA_V0_LLP = BIT(2),
20 DW_EDMA_V0_LIE = BIT(3),
21 DW_EDMA_V0_RIE = BIT(4),
22 DW_EDMA_V0_CCS = BIT(8),
23 DW_EDMA_V0_LLE = BIT(9),
26 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
28 return dw->chip->reg_base;
31 #define SET_32(dw, name, value) \
32 writel(value, &(__dw_regs(dw)->name))
34 #define GET_32(dw, name) \
35 readl(&(__dw_regs(dw)->name))
37 #define SET_RW_32(dw, dir, name, value) \
39 if ((dir) == EDMA_DIR_WRITE) \
40 SET_32(dw, wr_##name, value); \
42 SET_32(dw, rd_##name, value); \
45 #define GET_RW_32(dw, dir, name) \
46 ((dir) == EDMA_DIR_WRITE \
47 ? GET_32(dw, wr_##name) \
48 : GET_32(dw, rd_##name))
50 #define SET_BOTH_32(dw, name, value) \
52 SET_32(dw, wr_##name, value); \
53 SET_32(dw, rd_##name, value); \
58 #define SET_64(dw, name, value) \
59 writeq(value, &(__dw_regs(dw)->name))
61 #define GET_64(dw, name) \
62 readq(&(__dw_regs(dw)->name))
64 #define SET_RW_64(dw, dir, name, value) \
66 if ((dir) == EDMA_DIR_WRITE) \
67 SET_64(dw, wr_##name, value); \
69 SET_64(dw, rd_##name, value); \
72 #define GET_RW_64(dw, dir, name) \
73 ((dir) == EDMA_DIR_WRITE \
74 ? GET_64(dw, wr_##name) \
75 : GET_64(dw, rd_##name))
77 #define SET_BOTH_64(dw, name, value) \
79 SET_64(dw, wr_##name, value); \
80 SET_64(dw, rd_##name, value); \
83 #endif /* CONFIG_64BIT */
85 #define SET_COMPAT(dw, name, value) \
86 writel(value, &(__dw_regs(dw)->type.unroll.name))
88 #define SET_RW_COMPAT(dw, dir, name, value) \
90 if ((dir) == EDMA_DIR_WRITE) \
91 SET_COMPAT(dw, wr_##name, value); \
93 SET_COMPAT(dw, rd_##name, value); \
96 static inline struct dw_edma_v0_ch_regs __iomem *
97 __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch)
99 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY)
100 return &(__dw_regs(dw)->type.legacy.ch);
102 if (dir == EDMA_DIR_WRITE)
103 return &__dw_regs(dw)->type.unroll.ch[ch].wr;
105 return &__dw_regs(dw)->type.unroll.ch[ch].rd;
108 static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
109 u32 value, void __iomem *addr)
111 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
115 raw_spin_lock_irqsave(&dw->lock, flags);
117 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch);
118 if (dir == EDMA_DIR_READ)
119 viewport_sel |= BIT(31);
122 &(__dw_regs(dw)->type.legacy.viewport_sel));
125 raw_spin_unlock_irqrestore(&dw->lock, flags);
131 static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
132 const void __iomem *addr)
136 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
140 raw_spin_lock_irqsave(&dw->lock, flags);
142 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch);
143 if (dir == EDMA_DIR_READ)
144 viewport_sel |= BIT(31);
147 &(__dw_regs(dw)->type.legacy.viewport_sel));
150 raw_spin_unlock_irqrestore(&dw->lock, flags);
158 #define SET_CH_32(dw, dir, ch, name, value) \
159 writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
161 #define GET_CH_32(dw, dir, ch, name) \
162 readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
164 #define SET_LL_32(ll, value) \
169 static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
170 u64 value, void __iomem *addr)
172 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
176 raw_spin_lock_irqsave(&dw->lock, flags);
178 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch);
179 if (dir == EDMA_DIR_READ)
180 viewport_sel |= BIT(31);
183 &(__dw_regs(dw)->type.legacy.viewport_sel));
186 raw_spin_unlock_irqrestore(&dw->lock, flags);
192 static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
193 const void __iomem *addr)
197 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) {
201 raw_spin_lock_irqsave(&dw->lock, flags);
203 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch);
204 if (dir == EDMA_DIR_READ)
205 viewport_sel |= BIT(31);
208 &(__dw_regs(dw)->type.legacy.viewport_sel));
211 raw_spin_unlock_irqrestore(&dw->lock, flags);
219 #define SET_CH_64(dw, dir, ch, name, value) \
220 writeq_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
222 #define GET_CH_64(dw, dir, ch, name) \
223 readq_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
225 #define SET_LL_64(ll, value) \
228 #endif /* CONFIG_64BIT */
230 /* eDMA management callbacks */
231 void dw_edma_v0_core_off(struct dw_edma *dw)
233 SET_BOTH_32(dw, int_mask,
234 EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK);
235 SET_BOTH_32(dw, int_clear,
236 EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK);
237 SET_BOTH_32(dw, engine_en, 0);
240 u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
244 if (dir == EDMA_DIR_WRITE)
245 num_ch = FIELD_GET(EDMA_V0_WRITE_CH_COUNT_MASK,
248 num_ch = FIELD_GET(EDMA_V0_READ_CH_COUNT_MASK,
251 if (num_ch > EDMA_V0_MAX_NR_CH)
252 num_ch = EDMA_V0_MAX_NR_CH;
257 enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
259 struct dw_edma *dw = chan->dw;
262 tmp = FIELD_GET(EDMA_V0_CH_STATUS_MASK,
263 GET_CH_32(dw, chan->dir, chan->id, ch_control1));
266 return DMA_IN_PROGRESS;
273 void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
275 struct dw_edma *dw = chan->dw;
277 SET_RW_32(dw, chan->dir, int_clear,
278 FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)));
281 void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
283 struct dw_edma *dw = chan->dw;
285 SET_RW_32(dw, chan->dir, int_clear,
286 FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)));
289 u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir)
291 return FIELD_GET(EDMA_V0_DONE_INT_MASK,
292 GET_RW_32(dw, dir, int_status));
295 u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
297 return FIELD_GET(EDMA_V0_ABORT_INT_MASK,
298 GET_RW_32(dw, dir, int_status));
301 static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
303 struct dw_edma_burst *child;
304 struct dw_edma_v0_lli __iomem *lli;
305 struct dw_edma_v0_llp __iomem *llp;
306 u32 control = 0, i = 0;
309 lli = chunk->ll_region.vaddr;
312 control = DW_EDMA_V0_CB;
314 j = chunk->bursts_alloc;
315 list_for_each_entry(child, &chunk->burst->list, list) {
318 control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE);
320 /* Channel control */
321 SET_LL_32(&lli[i].control, control);
323 SET_LL_32(&lli[i].transfer_size, child->sz);
326 SET_LL_64(&lli[i].sar.reg, child->sar);
327 #else /* CONFIG_64BIT */
328 SET_LL_32(&lli[i].sar.lsb, lower_32_bits(child->sar));
329 SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar));
330 #endif /* CONFIG_64BIT */
333 SET_LL_64(&lli[i].dar.reg, child->dar);
334 #else /* CONFIG_64BIT */
335 SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar));
336 SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar));
337 #endif /* CONFIG_64BIT */
341 llp = (void __iomem *)&lli[i];
342 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB;
344 control |= DW_EDMA_V0_CB;
346 /* Channel control */
347 SET_LL_32(&llp->control, control);
350 SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr);
351 #else /* CONFIG_64BIT */
352 SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr));
353 SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr));
354 #endif /* CONFIG_64BIT */
357 void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
359 struct dw_edma_chan *chan = chunk->chan;
360 struct dw_edma *dw = chan->dw;
363 dw_edma_v0_core_write_chunk(chunk);
367 SET_RW_32(dw, chan->dir, engine_en, BIT(0));
368 if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) {
371 SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en,
375 SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en,
379 SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en,
383 SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en,
387 SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en,
391 SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en,
395 SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en,
399 SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en,
404 /* Interrupt unmask - done, abort */
405 tmp = GET_RW_32(dw, chan->dir, int_mask);
406 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
407 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
408 SET_RW_32(dw, chan->dir, int_mask, tmp);
409 /* Linked list error */
410 tmp = GET_RW_32(dw, chan->dir, linked_list_err_en);
411 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id));
412 SET_RW_32(dw, chan->dir, linked_list_err_en, tmp);
413 /* Channel control */
414 SET_CH_32(dw, chan->dir, chan->id, ch_control1,
415 (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
419 /* llp is not aligned on 64bit -> keep 32bit accesses */
420 SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
421 lower_32_bits(chunk->ll_region.paddr));
422 SET_CH_32(dw, chan->dir, chan->id, llp.msb,
423 upper_32_bits(chunk->ll_region.paddr));
424 #else /* CONFIG_64BIT */
425 SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
426 lower_32_bits(chunk->ll_region.paddr));
427 SET_CH_32(dw, chan->dir, chan->id, llp.msb,
428 upper_32_bits(chunk->ll_region.paddr));
429 #endif /* CONFIG_64BIT */
432 SET_RW_32(dw, chan->dir, doorbell,
433 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
436 int dw_edma_v0_core_device_config(struct dw_edma_chan *chan)
438 struct dw_edma *dw = chan->dw;
441 /* MSI done addr - low, high */
442 SET_RW_32(dw, chan->dir, done_imwr.lsb, chan->msi.address_lo);
443 SET_RW_32(dw, chan->dir, done_imwr.msb, chan->msi.address_hi);
444 /* MSI abort addr - low, high */
445 SET_RW_32(dw, chan->dir, abort_imwr.lsb, chan->msi.address_lo);
446 SET_RW_32(dw, chan->dir, abort_imwr.msb, chan->msi.address_hi);
447 /* MSI data - low, high */
451 tmp = GET_RW_32(dw, chan->dir, ch01_imwr_data);
456 tmp = GET_RW_32(dw, chan->dir, ch23_imwr_data);
461 tmp = GET_RW_32(dw, chan->dir, ch45_imwr_data);
466 tmp = GET_RW_32(dw, chan->dir, ch67_imwr_data);
470 if (chan->id & BIT(0)) {
471 /* Channel odd {1, 3, 5, 7} */
472 tmp &= EDMA_V0_CH_EVEN_MSI_DATA_MASK;
473 tmp |= FIELD_PREP(EDMA_V0_CH_ODD_MSI_DATA_MASK,
476 /* Channel even {0, 2, 4, 6} */
477 tmp &= EDMA_V0_CH_ODD_MSI_DATA_MASK;
478 tmp |= FIELD_PREP(EDMA_V0_CH_EVEN_MSI_DATA_MASK,
485 SET_RW_32(dw, chan->dir, ch01_imwr_data, tmp);
490 SET_RW_32(dw, chan->dir, ch23_imwr_data, tmp);
495 SET_RW_32(dw, chan->dir, ch45_imwr_data, tmp);
500 SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp);
507 /* eDMA debugfs callbacks */
508 void dw_edma_v0_core_debugfs_on(struct dw_edma *dw)
510 dw_edma_v0_debugfs_on(dw);
513 void dw_edma_v0_core_debugfs_off(struct dw_edma *dw)
515 dw_edma_v0_debugfs_off(dw);