drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
   3
   4 /*
   5  * Synopsys DesignWare AXI DMA Controller driver.
   6  *
   7  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/io-64-nonatomic-lo-hi.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/property.h>
  28 #include <linux/slab.h>
  29 #include <linux/types.h>
  30
  31 #include "dw-axi-dmac.h"
  32 #include "../dmaengine.h"
  33 #include "../virt-dma.h"
  34
  35 /*
  36  * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
  37  * master data bus width up to 512 bits (for both AXI master interfaces), but
  38  * it depends on IP block configuration.
  39  */
  40 #define AXI_DMA_BUSWIDTHS                 \
  41         (DMA_SLAVE_BUSWIDTH_1_BYTE      | \
  42         DMA_SLAVE_BUSWIDTH_2_BYTES      | \
  43         DMA_SLAVE_BUSWIDTH_4_BYTES      | \
  44         DMA_SLAVE_BUSWIDTH_8_BYTES      | \
  45         DMA_SLAVE_BUSWIDTH_16_BYTES     | \
  46         DMA_SLAVE_BUSWIDTH_32_BYTES     | \
  47         DMA_SLAVE_BUSWIDTH_64_BYTES)
  48
  49 static inline void
  50 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
  51 {
  52         iowrite32(val, chip->regs + reg);
  53 }
  54
  55 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg)
  56 {
  57         return ioread32(chip->regs + reg);
  58 }
  59
  60 static inline void
  61 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
  62 {
  63         iowrite32(val, chan->chan_regs + reg);
  64 }
  65
  66 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg)
  67 {
  68         return ioread32(chan->chan_regs + reg);
  69 }
  70
  71 static inline void
  72 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
  73 {
  74         /*
  75          * We split one 64 bit write for two 32 bit write as some HW doesn't
  76          * support 64 bit access.
  77          */
  78         iowrite32(lower_32_bits(val), chan->chan_regs + reg);
  79         iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
  80 }
  81
  82 static inline void axi_chan_config_write(struct axi_dma_chan *chan,
  83                                          struct axi_dma_chan_config *config)
  84 {
  85         u32 cfg_lo, cfg_hi;
  86
  87         cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
  88                   config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
  89         if (!IS_ENABLED(CONFIG_SOC_STARFIVE) && chan->chip->dw->hdata->reg_map_8_channels) {
  90                 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
  91                          config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
  92                          config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
  93                          config->src_per << CH_CFG_H_SRC_PER_POS |
  94                          config->dst_per << CH_CFG_H_DST_PER_POS |
  95                          config->prior << CH_CFG_H_PRIORITY_POS;
  96         } else {
  97                 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
  98                           config->dst_per << CH_CFG2_L_DST_PER_POS;
  99                 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
 100                          config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
 101                          config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
 102                          config->prior << CH_CFG2_H_PRIORITY_POS;
 103         }
 104         axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo);
 105         axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi);
 106 }
 107
 108 static inline void axi_dma_disable(struct axi_dma_chip *chip)
 109 {
 110         u32 val;
 111
 112         val = axi_dma_ioread32(chip, DMAC_CFG);
 113         val &= ~DMAC_EN_MASK;
 114         axi_dma_iowrite32(chip, DMAC_CFG, val);
 115 }
 116
 117 static inline void axi_dma_enable(struct axi_dma_chip *chip)
 118 {
 119         u32 val;
 120
 121         val = axi_dma_ioread32(chip, DMAC_CFG);
 122         val |= DMAC_EN_MASK;
 123         axi_dma_iowrite32(chip, DMAC_CFG, val);
 124 }
 125
 126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
 127 {
 128         u32 val;
 129
 130         val = axi_dma_ioread32(chip, DMAC_CFG);
 131         val &= ~INT_EN_MASK;
 132         axi_dma_iowrite32(chip, DMAC_CFG, val);
 133 }
 134
 135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
 136 {
 137         u32 val;
 138
 139         val = axi_dma_ioread32(chip, DMAC_CFG);
 140         val |= INT_EN_MASK;
 141         axi_dma_iowrite32(chip, DMAC_CFG, val);
 142 }
 143
 144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
 145 {
 146         u32 val;
 147
 148         if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) {
 149                 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE);
 150         } else {
 151                 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
 152                 val &= ~irq_mask;
 153                 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
 154         }
 155 }
 156
 157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask)
 158 {
 159         axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask);
 160 }
 161
 162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask)
 163 {
 164         axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask);
 165 }
 166
 167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask)
 168 {
 169         axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask);
 170 }
 171
 172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
 173 {
 174         return axi_chan_ioread32(chan, CH_INTSTATUS);
 175 }
 176
 177 static inline void axi_chan_disable(struct axi_dma_chan *chan)
 178 {
 179         u32 val;
 180
 181         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 182         val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
 183         if (chan->chip->dw->hdata->reg_map_8_channels)
 184                 val |=   BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
 185         else
 186                 val |=   BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
 187         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 188 }
 189
 190 static inline void axi_chan_enable(struct axi_dma_chan *chan)
 191 {
 192         u32 val;
 193
 194         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 195         if (chan->chip->dw->hdata->reg_map_8_channels)
 196                 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
 197                         BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
 198         else
 199                 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
 200                         BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
 201         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 202 }
 203
 204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
 205 {
 206         u32 val;
 207
 208         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 209
 210         return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
 211 }
 212
 213 static void axi_dma_hw_init(struct axi_dma_chip *chip)
 214 {
 215         int ret;
 216         u32 i;
 217
 218         for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
 219                 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
 220                 axi_chan_disable(&chip->dw->chan[i]);
 221         }
 222         ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
 223         if (ret)
 224                 dev_warn(chip->dev, "Unable to set coherent mask\n");
 225 }
 226
 227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
 228                                    dma_addr_t dst, size_t len)
 229 {
 230         u32 max_width = chan->chip->dw->hdata->m_data_width;
 231
 232         return __ffs(src | dst | len | BIT(max_width));
 233 }
 234
 235 static inline const char *axi_chan_name(struct axi_dma_chan *chan)
 236 {
 237         return dma_chan_name(&chan->vc.chan);
 238 }
 239
 240 static struct axi_dma_desc *axi_desc_alloc(u32 num)
 241 {
 242         struct axi_dma_desc *desc;
 243
 244         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 245         if (!desc)
 246                 return NULL;
 247
 248         desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
 249         if (!desc->hw_desc) {
 250                 kfree(desc);
 251                 return NULL;
 252         }
 253
 254         return desc;
 255 }
 256
 257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
 258                                         dma_addr_t *addr)
 259 {
 260         struct axi_dma_lli *lli;
 261         dma_addr_t phys;
 262
 263         lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
 264         if (unlikely(!lli)) {
 265                 dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
 266                         axi_chan_name(chan));
 267                 return NULL;
 268         }
 269
 270         atomic_inc(&chan->descs_allocated);
 271         *addr = phys;
 272
 273         return lli;
 274 }
 275
 276 static void axi_desc_put(struct axi_dma_desc *desc)
 277 {
 278         struct axi_dma_chan *chan = desc->chan;
 279         int count = atomic_read(&chan->descs_allocated);
 280         struct axi_dma_hw_desc *hw_desc;
 281         int descs_put;
 282
 283         for (descs_put = 0; descs_put < count; descs_put++) {
 284                 hw_desc = &desc->hw_desc[descs_put];
 285                 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
 286         }
 287
 288         kfree(desc->hw_desc);
 289         kfree(desc);
 290         atomic_sub(descs_put, &chan->descs_allocated);
 291         dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
 292                 axi_chan_name(chan), descs_put,
 293                 atomic_read(&chan->descs_allocated));
 294 }
 295
 296 static void vchan_desc_put(struct virt_dma_desc *vdesc)
 297 {
 298         axi_desc_put(vd_to_axi_desc(vdesc));
 299 }
 300
 301 static enum dma_status
 302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
 303                   struct dma_tx_state *txstate)
 304 {
 305         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 306         struct virt_dma_desc *vdesc;
 307         enum dma_status status;
 308         u32 completed_length;
 309         unsigned long flags;
 310         u32 completed_blocks;
 311         size_t bytes = 0;
 312         u32 length;
 313         u32 len;
 314
 315         status = dma_cookie_status(dchan, cookie, txstate);
 316         if (status == DMA_COMPLETE || !txstate)
 317                 return status;
 318
 319         spin_lock_irqsave(&chan->vc.lock, flags);
 320
 321         vdesc = vchan_find_desc(&chan->vc, cookie);
 322         if (vdesc) {
 323                 length = vd_to_axi_desc(vdesc)->length;
 324                 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
 325                 len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
 326                 completed_length = completed_blocks * len;
 327                 bytes = length - completed_length;
 328         } else {
 329                 bytes = vd_to_axi_desc(vdesc)->length;
 330         }
 331
 332         spin_unlock_irqrestore(&chan->vc.lock, flags);
 333         dma_set_residue(txstate, bytes);
 334
 335         return status;
 336 }
 337
 338 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 339 {
 340         desc->lli->llp = cpu_to_le64(adr);
 341 }
 342
 343 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
 344 {
 345         axi_chan_iowrite64(chan, CH_LLP, adr);
 346 }
 347
 348 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
 349 {
 350         u32 offset = DMAC_APB_BYTE_WR_CH_EN;
 351         u32 reg_width, val;
 352
 353         if (!chan->chip->apb_regs) {
 354                 dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
 355                 return;
 356         }
 357
 358         reg_width = __ffs(chan->config.dst_addr_width);
 359         if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
 360                 offset = DMAC_APB_HALFWORD_WR_CH_EN;
 361
 362         val = ioread32(chan->chip->apb_regs + offset);
 363
 364         if (set)
 365                 val |= BIT(chan->id);
 366         else
 367                 val &= ~BIT(chan->id);
 368
 369         iowrite32(val, chan->chip->apb_regs + offset);
 370 }
 371 /* Called in chan locked context */
 372 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
 373                                       struct axi_dma_desc *first)
 374 {
 375         u32 priority = chan->chip->dw->hdata->priority[chan->id];
 376         struct axi_dma_chan_config config = {};
 377         u32 irq_mask;
 378         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 379
 380         chan->is_err = false;
 381         if (unlikely(axi_chan_is_hw_enable(chan))) {
 382                 dev_err(chan2dev(chan), "%s is non-idle!\n",
 383                         axi_chan_name(chan));
 384
 385                 axi_chan_disable(chan);
 386                 chan->is_err = true;
 387         }
 388
 389         axi_dma_enable(chan->chip);
 390
 391         config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
 392         config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
 393         config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
 394         config.prior = priority;
 395         config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
 396         config.hs_sel_src = DWAXIDMAC_HS_SEL_HW;
 397         switch (chan->direction) {
 398         case DMA_MEM_TO_DEV:
 399                 dw_axi_dma_set_byte_halfword(chan, true);
 400                 config.tt_fc = chan->config.device_fc ?
 401                                 DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
 402                                 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
 403                 if (chan->chip->apb_regs)
 404                         config.dst_per = chan->id;
 405                 else
 406                         config.dst_per = chan->hw_handshake_num;
 407                 break;
 408         case DMA_DEV_TO_MEM:
 409                 config.tt_fc = chan->config.device_fc ?
 410                                 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
 411                                 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
 412                 if (chan->chip->apb_regs)
 413                         config.src_per = chan->id;
 414                 else
 415                         config.src_per = chan->hw_handshake_num;
 416                 break;
 417         default:
 418                 break;
 419         }
 420         axi_chan_config_write(chan, &config);
 421
 422         write_chan_llp(chan, first->hw_desc[0].llp | lms);
 423
 424         irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
 425         axi_chan_irq_sig_set(chan, irq_mask);
 426
 427         /* Generate 'suspend' status but don't generate interrupt */
 428         irq_mask |= DWAXIDMAC_IRQ_SUSPENDED;
 429         axi_chan_irq_set(chan, irq_mask);
 430
 431         axi_chan_enable(chan);
 432 }
 433
 434 static void axi_chan_start_first_queued(struct axi_dma_chan *chan)
 435 {
 436         struct axi_dma_desc *desc;
 437         struct virt_dma_desc *vd;
 438
 439         vd = vchan_next_desc(&chan->vc);
 440         if (!vd)
 441                 return;
 442
 443         desc = vd_to_axi_desc(vd);
 444         dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan),
 445                 vd->tx.cookie);
 446         axi_chan_block_xfer_start(chan, desc);
 447 }
 448
 449 static void dma_chan_issue_pending(struct dma_chan *dchan)
 450 {
 451         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 452         unsigned long flags;
 453
 454         spin_lock_irqsave(&chan->vc.lock, flags);
 455         if (vchan_issue_pending(&chan->vc))
 456                 axi_chan_start_first_queued(chan);
 457         spin_unlock_irqrestore(&chan->vc.lock, flags);
 458 }
 459
 460 static void dw_axi_dma_synchronize(struct dma_chan *dchan)
 461 {
 462         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 463
 464         vchan_synchronize(&chan->vc);
 465 }
 466
 467 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
 468 {
 469         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 470
 471         /* ASSERT: channel is idle */
 472         if (axi_chan_is_hw_enable(chan)) {
 473                 dev_err(chan2dev(chan), "%s is non-idle!\n",
 474                         axi_chan_name(chan));
 475                 return -EBUSY;
 476         }
 477
 478         /* LLI address must be aligned to a 64-byte boundary */
 479         chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
 480                                           chan->chip->dev,
 481                                           sizeof(struct axi_dma_lli),
 482                                           64, 0);
 483         if (!chan->desc_pool) {
 484                 dev_err(chan2dev(chan), "No memory for descriptors\n");
 485                 return -ENOMEM;
 486         }
 487         dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
 488
 489         pm_runtime_get(chan->chip->dev);
 490
 491         return 0;
 492 }
 493
 494 static void dma_chan_free_chan_resources(struct dma_chan *dchan)
 495 {
 496         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 497
 498         /* ASSERT: channel is idle */
 499         if (axi_chan_is_hw_enable(chan))
 500                 dev_err(dchan2dev(dchan), "%s is non-idle!\n",
 501                         axi_chan_name(chan));
 502
 503         axi_chan_disable(chan);
 504         axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
 505
 506         vchan_free_chan_resources(&chan->vc);
 507
 508         dma_pool_destroy(chan->desc_pool);
 509         chan->desc_pool = NULL;
 510         dev_vdbg(dchan2dev(dchan),
 511                  "%s: free resources, descriptor still allocated: %u\n",
 512                  axi_chan_name(chan), atomic_read(&chan->descs_allocated));
 513
 514         pm_runtime_put(chan->chip->dev);
 515 }
 516
 517 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
 518 {
 519         struct axi_dma_chip *chip = chan->chip;
 520         unsigned long reg_value, val;
 521
 522         if (!chip->apb_regs) {
 523                 dev_err(chip->dev, "apb_regs not initialized\n");
 524                 return;
 525         }
 526
 527         /*
 528          * An unused DMA channel has a default value of 0x3F.
 529          * Lock the DMA channel by assign a handshake number to the channel.
 530          * Unlock the DMA channel by assign 0x3F to the channel.
 531          */
 532         if (set)
 533                 val = chan->hw_handshake_num;
 534         else
 535                 val = UNUSED_CHANNEL;
 536
 537         reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
 538
 539         /* Channel is already allocated, set handshake as per channel ID */
 540         /* 64 bit write should handle for 8 channels */
 541
 542         reg_value &= ~(DMA_APB_HS_SEL_MASK <<
 543                         (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
 544         reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
 545         lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
 546
 547         return;
 548 }
 549
 550 /*
 551  * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
 552  * as 1, it understands that the current block is the final block in the
 553  * transfer and completes the DMA transfer operation at the end of current
 554  * block transfer.
 555  */
 556 static void set_desc_last(struct axi_dma_hw_desc *desc)
 557 {
 558         u32 val;
 559
 560         val = le32_to_cpu(desc->lli->ctl_hi);
 561         val |= CH_CTL_H_LLI_LAST;
 562         desc->lli->ctl_hi = cpu_to_le32(val);
 563 }
 564
 565 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 566 {
 567         desc->lli->sar = cpu_to_le64(adr);
 568 }
 569
 570 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 571 {
 572         desc->lli->dar = cpu_to_le64(adr);
 573 }
 574
 575 static void set_desc_src_master(struct axi_dma_hw_desc *desc)
 576 {
 577         u32 val;
 578
 579         /* Select AXI0 for source master */
 580         val = le32_to_cpu(desc->lli->ctl_lo);
 581         val &= ~CH_CTL_L_SRC_MAST;
 582         desc->lli->ctl_lo = cpu_to_le32(val);
 583 }
 584
 585 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
 586                                  struct axi_dma_desc *desc)
 587 {
 588         u32 val;
 589
 590         /* Select AXI1 for source master if available */
 591         val = le32_to_cpu(hw_desc->lli->ctl_lo);
 592         if (desc->chan->chip->dw->hdata->nr_masters > 1)
 593                 val |= CH_CTL_L_DST_MAST;
 594         else
 595                 val &= ~CH_CTL_L_DST_MAST;
 596
 597         hw_desc->lli->ctl_lo = cpu_to_le32(val);
 598 }
 599
 600 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
 601                                   struct axi_dma_hw_desc *hw_desc,
 602                                   dma_addr_t mem_addr, size_t len)
 603 {
 604         unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
 605         unsigned int reg_width;
 606         unsigned int mem_width;
 607         dma_addr_t device_addr;
 608         size_t axi_block_ts;
 609         size_t block_ts;
 610         u32 ctllo, ctlhi;
 611         u32 burst_len;
 612
 613         axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 614
 615         mem_width = __ffs(data_width | mem_addr | len);
 616         if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
 617                 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
 618
 619         if (!IS_ALIGNED(mem_addr, 4)) {
 620                 dev_err(chan->chip->dev, "invalid buffer alignment\n");
 621                 return -EINVAL;
 622         }
 623
 624         switch (chan->direction) {
 625         case DMA_MEM_TO_DEV:
 626                 reg_width = __ffs(chan->config.dst_addr_width);
 627                 device_addr = chan->config.dst_addr;
 628                 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
 629                         mem_width << CH_CTL_L_SRC_WIDTH_POS |
 630                         DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
 631                         DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
 632                 block_ts = len >> mem_width;
 633                 break;
 634         case DMA_DEV_TO_MEM:
 635                 reg_width = __ffs(chan->config.src_addr_width);
 636                 device_addr = chan->config.src_addr;
 637                 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
 638                         mem_width << CH_CTL_L_DST_WIDTH_POS |
 639                         DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
 640                         DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
 641                 block_ts = len >> reg_width;
 642                 break;
 643         default:
 644                 return -EINVAL;
 645         }
 646
 647         if (block_ts > axi_block_ts)
 648                 return -EINVAL;
 649
 650         hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
 651         if (unlikely(!hw_desc->lli))
 652                 return -ENOMEM;
 653
 654         ctlhi = CH_CTL_H_LLI_VALID;
 655
 656         if (chan->chip->dw->hdata->restrict_axi_burst_len) {
 657                 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
 658                 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
 659                          burst_len << CH_CTL_H_ARLEN_POS |
 660                          burst_len << CH_CTL_H_AWLEN_POS;
 661         }
 662
 663         hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
 664
 665         if (chan->direction == DMA_MEM_TO_DEV) {
 666                 write_desc_sar(hw_desc, mem_addr);
 667                 write_desc_dar(hw_desc, device_addr);
 668         } else {
 669                 write_desc_sar(hw_desc, device_addr);
 670                 write_desc_dar(hw_desc, mem_addr);
 671         }
 672
 673         hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
 674
 675 #ifdef CONFIG_SOC_STARFIVE
 676         ctllo |= DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_DST_MSIZE_POS |
 677                  DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_SRC_MSIZE_POS;
 678 #else
 679         ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
 680                  DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
 681 #endif
 682         hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
 683
 684         set_desc_src_master(hw_desc);
 685
 686         hw_desc->len = len;
 687         return 0;
 688 }
 689
 690 static size_t calculate_block_len(struct axi_dma_chan *chan,
 691                                   dma_addr_t dma_addr, size_t buf_len,
 692                                   enum dma_transfer_direction direction)
 693 {
 694         u32 data_width, reg_width, mem_width;
 695         size_t axi_block_ts, block_len;
 696
 697         axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 698
 699         switch (direction) {
 700         case DMA_MEM_TO_DEV:
 701                 data_width = BIT(chan->chip->dw->hdata->m_data_width);
 702                 mem_width = __ffs(data_width | dma_addr | buf_len);
 703                 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
 704                         mem_width = DWAXIDMAC_TRANS_WIDTH_32;
 705
 706                 block_len = axi_block_ts << mem_width;
 707                 break;
 708         case DMA_DEV_TO_MEM:
 709                 reg_width = __ffs(chan->config.src_addr_width);
 710                 block_len = axi_block_ts << reg_width;
 711                 break;
 712         default:
 713                 block_len = 0;
 714         }
 715
 716         return block_len;
 717 }
 718
 719 static struct dma_async_tx_descriptor *
 720 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
 721                             size_t buf_len, size_t period_len,
 722                             enum dma_transfer_direction direction,
 723                             unsigned long flags)
 724 {
 725         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 726         struct axi_dma_hw_desc *hw_desc = NULL;
 727         struct axi_dma_desc *desc = NULL;
 728         dma_addr_t src_addr = dma_addr;
 729         u32 num_periods, num_segments;
 730         size_t axi_block_len;
 731         u32 total_segments;
 732         u32 segment_len;
 733         unsigned int i;
 734         int status;
 735         u64 llp = 0;
 736         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 737
 738         num_periods = buf_len / period_len;
 739
 740         axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
 741         if (axi_block_len == 0)
 742                 return NULL;
 743
 744         num_segments = DIV_ROUND_UP(period_len, axi_block_len);
 745         segment_len = DIV_ROUND_UP(period_len, num_segments);
 746
 747         total_segments = num_periods * num_segments;
 748
 749         desc = axi_desc_alloc(total_segments);
 750         if (unlikely(!desc))
 751                 goto err_desc_get;
 752
 753         chan->direction = direction;
 754         desc->chan = chan;
 755         chan->cyclic = true;
 756         desc->length = 0;
 757         desc->period_len = period_len;
 758
 759         for (i = 0; i < total_segments; i++) {
 760                 hw_desc = &desc->hw_desc[i];
 761
 762                 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
 763                                                 segment_len);
 764                 if (status < 0)
 765                         goto err_desc_get;
 766
 767                 desc->length += hw_desc->len;
 768                 /* Set end-of-link to the linked descriptor, so that cyclic
 769                  * callback function can be triggered during interrupt.
 770                  */
 771                 set_desc_last(hw_desc);
 772
 773                 src_addr += segment_len;
 774         }
 775
 776         llp = desc->hw_desc[0].llp;
 777
 778         /* Managed transfer list */
 779         do {
 780                 hw_desc = &desc->hw_desc[--total_segments];
 781                 write_desc_llp(hw_desc, llp | lms);
 782                 llp = hw_desc->llp;
 783         } while (total_segments);
 784
 785         dw_axi_dma_set_hw_channel(chan, true);
 786
 787         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 788
 789 err_desc_get:
 790         if (desc)
 791                 axi_desc_put(desc);
 792
 793         return NULL;
 794 }
 795
 796 static struct dma_async_tx_descriptor *
 797 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
 798                               unsigned int sg_len,
 799                               enum dma_transfer_direction direction,
 800                               unsigned long flags, void *context)
 801 {
 802         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 803         struct axi_dma_hw_desc *hw_desc = NULL;
 804         struct axi_dma_desc *desc = NULL;
 805         u32 num_segments, segment_len;
 806         unsigned int loop = 0;
 807         struct scatterlist *sg;
 808         size_t axi_block_len;
 809         u32 len, num_sgs = 0;
 810         unsigned int i;
 811         dma_addr_t mem;
 812         int status;
 813         u64 llp = 0;
 814         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 815
 816         if (unlikely(!is_slave_direction(direction) || !sg_len))
 817                 return NULL;
 818
 819         mem = sg_dma_address(sgl);
 820         len = sg_dma_len(sgl);
 821
 822         axi_block_len = calculate_block_len(chan, mem, len, direction);
 823         if (axi_block_len == 0)
 824                 return NULL;
 825
 826         for_each_sg(sgl, sg, sg_len, i)
 827                 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
 828
 829         desc = axi_desc_alloc(num_sgs);
 830         if (unlikely(!desc))
 831                 goto err_desc_get;
 832
 833         desc->chan = chan;
 834         desc->length = 0;
 835         chan->direction = direction;
 836
 837         for_each_sg(sgl, sg, sg_len, i) {
 838                 mem = sg_dma_address(sg);
 839                 len = sg_dma_len(sg);
 840                 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
 841                 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
 842
 843                 do {
 844                         hw_desc = &desc->hw_desc[loop++];
 845                         status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
 846                         if (status < 0)
 847                                 goto err_desc_get;
 848
 849                         desc->length += hw_desc->len;
 850                         len -= segment_len;
 851                         mem += segment_len;
 852                 } while (len >= segment_len);
 853         }
 854
 855         /* Set end-of-link to the last link descriptor of list */
 856         set_desc_last(&desc->hw_desc[num_sgs - 1]);
 857
 858         /* Managed transfer list */
 859         do {
 860                 hw_desc = &desc->hw_desc[--num_sgs];
 861                 write_desc_llp(hw_desc, llp | lms);
 862                 llp = hw_desc->llp;
 863         } while (num_sgs);
 864
 865         dw_axi_dma_set_hw_channel(chan, true);
 866
 867         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 868
 869 err_desc_get:
 870         if (desc)
 871                 axi_desc_put(desc);
 872
 873         return NULL;
 874 }
 875
 876 static struct dma_async_tx_descriptor *
 877 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
 878                          dma_addr_t src_adr, size_t len, unsigned long flags)
 879 {
 880         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 881         size_t block_ts, max_block_ts, xfer_len;
 882         struct axi_dma_hw_desc *hw_desc = NULL;
 883         struct axi_dma_desc *desc = NULL;
 884         u32 xfer_width, reg, num;
 885         u64 llp = 0;
 886         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 887
 888         dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
 889                 axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
 890
 891         max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 892         xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
 893         num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
 894         desc = axi_desc_alloc(num);
 895         if (unlikely(!desc))
 896                 goto err_desc_get;
 897
 898         desc->chan = chan;
 899         num = 0;
 900         desc->length = 0;
 901         while (len) {
 902                 xfer_len = len;
 903
 904                 hw_desc = &desc->hw_desc[num];
 905                 /*
 906                  * Take care for the alignment.
 907                  * Actually source and destination widths can be different, but
 908                  * make them same to be simpler.
 909                  */
 910                 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len);
 911
 912                 /*
 913                  * block_ts indicates the total number of data of width
 914                  * to be transferred in a DMA block transfer.
 915                  * BLOCK_TS register should be set to block_ts - 1
 916                  */
 917                 block_ts = xfer_len >> xfer_width;
 918                 if (block_ts > max_block_ts) {
 919                         block_ts = max_block_ts;
 920                         xfer_len = max_block_ts << xfer_width;
 921                 }
 922
 923                 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
 924                 if (unlikely(!hw_desc->lli))
 925                         goto err_desc_get;
 926
 927                 write_desc_sar(hw_desc, src_adr);
 928                 write_desc_dar(hw_desc, dst_adr);
 929                 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
 930
 931                 reg = CH_CTL_H_LLI_VALID;
 932                 if (chan->chip->dw->hdata->restrict_axi_burst_len) {
 933                         u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
 934
 935                         reg |= (CH_CTL_H_ARLEN_EN |
 936                                 burst_len << CH_CTL_H_ARLEN_POS |
 937                                 CH_CTL_H_AWLEN_EN |
 938                                 burst_len << CH_CTL_H_AWLEN_POS);
 939                 }
 940                 hw_desc->lli->ctl_hi = cpu_to_le32(reg);
 941
 942                 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
 943                        DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
 944                        xfer_width << CH_CTL_L_DST_WIDTH_POS |
 945                        xfer_width << CH_CTL_L_SRC_WIDTH_POS |
 946                        DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
 947                        DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
 948                 hw_desc->lli->ctl_lo = cpu_to_le32(reg);
 949
 950                 set_desc_src_master(hw_desc);
 951                 set_desc_dest_master(hw_desc, desc);
 952
 953                 hw_desc->len = xfer_len;
 954                 desc->length += hw_desc->len;
 955                 /* update the length and addresses for the next loop cycle */
 956                 len -= xfer_len;
 957                 dst_adr += xfer_len;
 958                 src_adr += xfer_len;
 959                 num++;
 960         }
 961
 962         /* Set end-of-link to the last link descriptor of list */
 963         set_desc_last(&desc->hw_desc[num - 1]);
 964         /* Managed transfer list */
 965         do {
 966                 hw_desc = &desc->hw_desc[--num];
 967                 write_desc_llp(hw_desc, llp | lms);
 968                 llp = hw_desc->llp;
 969         } while (num);
 970
 971         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 972
 973 err_desc_get:
 974         if (desc)
 975                 axi_desc_put(desc);
 976         return NULL;
 977 }
 978
 979 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
 980                                         struct dma_slave_config *config)
 981 {
 982         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 983
 984         memcpy(&chan->config, config, sizeof(*config));
 985
 986         return 0;
 987 }
 988
 989 static void axi_chan_dump_lli(struct axi_dma_chan *chan,
 990                               struct axi_dma_hw_desc *desc)
 991 {
 992         if (!desc->lli) {
 993                 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n");
 994                 return;
 995         }
 996
 997         dev_err(dchan2dev(&chan->vc.chan),
 998                 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
 999                 le64_to_cpu(desc->lli->sar),
1000                 le64_to_cpu(desc->lli->dar),
1001                 le64_to_cpu(desc->lli->llp),
1002                 le32_to_cpu(desc->lli->block_ts_lo),
1003                 le32_to_cpu(desc->lli->ctl_hi),
1004                 le32_to_cpu(desc->lli->ctl_lo));
1005 }
1006
1007 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
1008                                    struct axi_dma_desc *desc_head)
1009 {
1010         int count = atomic_read(&chan->descs_allocated);
1011         int i;
1012
1013         for (i = 0; i < count; i++)
1014                 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
1015 }
1016
1017 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
1018 {
1019         struct virt_dma_desc *vd;
1020         unsigned long flags;
1021
1022         spin_lock_irqsave(&chan->vc.lock, flags);
1023
1024         axi_chan_disable(chan);
1025
1026         /* The bad descriptor currently is in the head of vc list */
1027         vd = vchan_next_desc(&chan->vc);
1028         if (!vd) {
1029                 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1030                         axi_chan_name(chan));
1031                 goto out;
1032         }
1033
1034         if (chan->is_err) {
1035                 struct axi_dma_desc *desc = vd_to_axi_desc(vd);
1036
1037                 axi_chan_block_xfer_start(chan, desc);
1038                 chan->is_err = false;
1039                 goto out;
1040         }
1041
1042         /* Remove the completed descriptor from issued list */
1043         list_del(&vd->node);
1044
1045         /* WARN about bad descriptor */
1046         dev_err(chan2dev(chan),
1047                 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
1048                 axi_chan_name(chan), vd->tx.cookie, status);
1049         axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
1050
1051         vchan_cookie_complete(vd);
1052
1053         /* Try to restart the controller */
1054         axi_chan_start_first_queued(chan);
1055
1056 out:
1057         spin_unlock_irqrestore(&chan->vc.lock, flags);
1058 }
1059
1060 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
1061 {
1062         int count = atomic_read(&chan->descs_allocated);
1063         struct axi_dma_hw_desc *hw_desc;
1064         struct axi_dma_desc *desc;
1065         struct virt_dma_desc *vd;
1066         unsigned long flags;
1067         u64 llp;
1068         int i;
1069
1070         spin_lock_irqsave(&chan->vc.lock, flags);
1071         if (unlikely(axi_chan_is_hw_enable(chan))) {
1072                 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n",
1073                         axi_chan_name(chan));
1074                 axi_chan_disable(chan);
1075         }
1076
1077         /* The completed descriptor currently is in the head of vc list */
1078         vd = vchan_next_desc(&chan->vc);
1079         if (!vd) {
1080                 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1081                         axi_chan_name(chan));
1082                 goto out;
1083         }
1084
1085         if (chan->cyclic) {
1086                 desc = vd_to_axi_desc(vd);
1087                 if (desc) {
1088                         llp = lo_hi_readq(chan->chan_regs + CH_LLP);
1089                         for (i = 0; i < count; i++) {
1090                                 hw_desc = &desc->hw_desc[i];
1091                                 if (hw_desc->llp == llp) {
1092                                         axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
1093                                         hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
1094                                         desc->completed_blocks = i;
1095
1096                                         if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
1097                                                 vchan_cyclic_callback(vd);
1098                                         break;
1099                                 }
1100                         }
1101
1102                         axi_chan_enable(chan);
1103                 }
1104         } else {
1105                 /* Remove the completed descriptor from issued list before completing */
1106                 list_del(&vd->node);
1107                 vchan_cookie_complete(vd);
1108
1109                 /* Submit queued descriptors after processing the completed ones */
1110                 axi_chan_start_first_queued(chan);
1111         }
1112
1113 out:
1114         spin_unlock_irqrestore(&chan->vc.lock, flags);
1115 }
1116
1117 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
1118 {
1119         struct axi_dma_chip *chip = dev_id;
1120         struct dw_axi_dma *dw = chip->dw;
1121         struct axi_dma_chan *chan;
1122
1123         u32 status, i;
1124
1125         /* Disable DMAC interrupts. We'll enable them after processing channels */
1126         axi_dma_irq_disable(chip);
1127
1128         /* Poll, clear and process every channel interrupt status */
1129         for (i = 0; i < dw->hdata->nr_channels; i++) {
1130                 chan = &dw->chan[i];
1131                 status = axi_chan_irq_read(chan);
1132                 axi_chan_irq_clear(chan, status);
1133
1134                 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
1135                         axi_chan_name(chan), i, status);
1136
1137                 if (status & DWAXIDMAC_IRQ_ALL_ERR)
1138                         axi_chan_handle_err(chan, status);
1139                 else if (status & DWAXIDMAC_IRQ_DMA_TRF)
1140                         axi_chan_block_xfer_complete(chan);
1141         }
1142
1143         /* Re-enable interrupts */
1144         axi_dma_irq_enable(chip);
1145
1146         return IRQ_HANDLED;
1147 }
1148
1149 static int dma_chan_terminate_all(struct dma_chan *dchan)
1150 {
1151         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1152         u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
1153         unsigned long flags;
1154         u32 val;
1155         int ret;
1156         LIST_HEAD(head);
1157
1158         axi_chan_disable(chan);
1159
1160         ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
1161                                         !(val & chan_active), 1000, 10000);
1162         if (ret == -ETIMEDOUT)
1163                 dev_warn(dchan2dev(dchan),
1164                          "%s failed to stop\n", axi_chan_name(chan));
1165
1166         if (chan->direction != DMA_MEM_TO_MEM)
1167                 dw_axi_dma_set_hw_channel(chan, false);
1168         if (chan->direction == DMA_MEM_TO_DEV)
1169                 dw_axi_dma_set_byte_halfword(chan, false);
1170
1171         spin_lock_irqsave(&chan->vc.lock, flags);
1172
1173         vchan_get_all_descriptors(&chan->vc, &head);
1174
1175         chan->cyclic = false;
1176         spin_unlock_irqrestore(&chan->vc.lock, flags);
1177
1178         vchan_dma_desc_free_list(&chan->vc, &head);
1179
1180         dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan));
1181
1182         return 0;
1183 }
1184
1185 static int dma_chan_pause(struct dma_chan *dchan)
1186 {
1187         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1188         unsigned long flags;
1189         unsigned int timeout = 20; /* timeout iterations */
1190         u32 val;
1191
1192         spin_lock_irqsave(&chan->vc.lock, flags);
1193
1194         if (chan->chip->dw->hdata->reg_map_8_channels) {
1195                 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1196                 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
1197                         BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
1198                 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1199         } else {
1200                 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1201                 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
1202                         BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
1203                 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1204         }
1205
1206         do  {
1207                 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
1208                         break;
1209
1210                 udelay(2);
1211         } while (--timeout);
1212
1213         axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED);
1214
1215         chan->is_paused = true;
1216
1217         spin_unlock_irqrestore(&chan->vc.lock, flags);
1218
1219         return timeout ? 0 : -EAGAIN;
1220 }
1221
1222 /* Called in chan locked context */
1223 static inline void axi_chan_resume(struct axi_dma_chan *chan)
1224 {
1225         u32 val;
1226
1227         if (chan->chip->dw->hdata->reg_map_8_channels) {
1228                 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1229                 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
1230                 val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
1231                 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1232         } else {
1233                 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1234                 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
1235                 val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
1236                 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1237         }
1238
1239         chan->is_paused = false;
1240 }
1241
1242 static int dma_chan_resume(struct dma_chan *dchan)
1243 {
1244         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1245         unsigned long flags;
1246
1247         spin_lock_irqsave(&chan->vc.lock, flags);
1248
1249         if (chan->is_paused)
1250                 axi_chan_resume(chan);
1251
1252         spin_unlock_irqrestore(&chan->vc.lock, flags);
1253
1254         return 0;
1255 }
1256
1257 static int axi_dma_suspend(struct axi_dma_chip *chip)
1258 {
1259         axi_dma_irq_disable(chip);
1260         axi_dma_disable(chip);
1261
1262         clk_disable_unprepare(chip->core_clk);
1263         clk_disable_unprepare(chip->cfgr_clk);
1264
1265         return 0;
1266 }
1267
1268 static int axi_dma_resume(struct axi_dma_chip *chip)
1269 {
1270         int ret;
1271
1272         ret = clk_prepare_enable(chip->cfgr_clk);
1273         if (ret < 0)
1274                 return ret;
1275
1276         ret = clk_prepare_enable(chip->core_clk);
1277         if (ret < 0)
1278                 return ret;
1279
1280         axi_dma_enable(chip);
1281         axi_dma_irq_enable(chip);
1282
1283         return 0;
1284 }
1285
1286 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
1287 {
1288         struct axi_dma_chip *chip = dev_get_drvdata(dev);
1289
1290         return axi_dma_suspend(chip);
1291 }
1292
1293 static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
1294 {
1295         struct axi_dma_chip *chip = dev_get_drvdata(dev);
1296
1297         return axi_dma_resume(chip);
1298 }
1299
1300 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
1301                                             struct of_dma *ofdma)
1302 {
1303         struct dw_axi_dma *dw = ofdma->of_dma_data;
1304         struct axi_dma_chan *chan;
1305         struct dma_chan *dchan;
1306
1307         dchan = dma_get_any_slave_channel(&dw->dma);
1308         if (!dchan)
1309                 return NULL;
1310
1311         chan = dchan_to_axi_dma_chan(dchan);
1312         chan->hw_handshake_num = dma_spec->args[0];
1313         return dchan;
1314 }
1315
1316 static int parse_device_properties(struct axi_dma_chip *chip)
1317 {
1318         struct device *dev = chip->dev;
1319         u32 tmp, carr[DMAC_MAX_CHANNELS];
1320         int ret;
1321
1322         ret = device_property_read_u32(dev, "dma-channels", &tmp);
1323         if (ret)
1324                 return ret;
1325         if (tmp == 0 || tmp > DMAC_MAX_CHANNELS)
1326                 return -EINVAL;
1327
1328         chip->dw->hdata->nr_channels = tmp;
1329         if (tmp <= DMA_REG_MAP_CH_REF)
1330                 chip->dw->hdata->reg_map_8_channels = true;
1331
1332         ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
1333         if (ret)
1334                 return ret;
1335         if (tmp == 0 || tmp > DMAC_MAX_MASTERS)
1336                 return -EINVAL;
1337
1338         chip->dw->hdata->nr_masters = tmp;
1339
1340         ret = device_property_read_u32(dev, "snps,data-width", &tmp);
1341         if (ret)
1342                 return ret;
1343         if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX)
1344                 return -EINVAL;
1345
1346         chip->dw->hdata->m_data_width = tmp;
1347
1348         ret = device_property_read_u32_array(dev, "snps,block-size", carr,
1349                                              chip->dw->hdata->nr_channels);
1350         if (ret)
1351                 return ret;
1352         for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1353                 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE)
1354                         return -EINVAL;
1355
1356                 chip->dw->hdata->block_size[tmp] = carr[tmp];
1357         }
1358
1359         ret = device_property_read_u32_array(dev, "snps,priority", carr,
1360                                              chip->dw->hdata->nr_channels);
1361         if (ret)
1362                 return ret;
1363         /* Priority value must be programmed within [0:nr_channels-1] range */
1364         for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1365                 if (carr[tmp] >= chip->dw->hdata->nr_channels)
1366                         return -EINVAL;
1367
1368                 chip->dw->hdata->priority[tmp] = carr[tmp];
1369         }
1370
1371         /* axi-max-burst-len is optional property */
1372         ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp);
1373         if (!ret) {
1374                 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1)
1375                         return -EINVAL;
1376                 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1)
1377                         return -EINVAL;
1378
1379                 chip->dw->hdata->restrict_axi_burst_len = true;
1380                 chip->dw->hdata->axi_rw_burst_len = tmp;
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int dw_probe(struct platform_device *pdev)
1387 {
1388         struct device_node *node = pdev->dev.of_node;
1389         struct axi_dma_chip *chip;
1390         struct resource *mem;
1391         struct dw_axi_dma *dw;
1392         struct dw_axi_dma_hcfg *hdata;
1393         u32 i;
1394         int ret;
1395
1396         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1397         if (!chip)
1398                 return -ENOMEM;
1399
1400         dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
1401         if (!dw)
1402                 return -ENOMEM;
1403
1404         hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
1405         if (!hdata)
1406                 return -ENOMEM;
1407
1408         chip->dw = dw;
1409         chip->dev = &pdev->dev;
1410         chip->dw->hdata = hdata;
1411
1412         chip->irq = platform_get_irq(pdev, 0);
1413         if (chip->irq < 0)
1414                 return chip->irq;
1415
1416         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1417         chip->regs = devm_ioremap_resource(chip->dev, mem);
1418         if (IS_ERR(chip->regs))
1419                 return PTR_ERR(chip->regs);
1420
1421         if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
1422                 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
1423                 if (IS_ERR(chip->apb_regs))
1424                         return PTR_ERR(chip->apb_regs);
1425         }
1426
1427         chip->core_clk = devm_clk_get(chip->dev, "core-clk");
1428         if (IS_ERR(chip->core_clk))
1429                 return PTR_ERR(chip->core_clk);
1430
1431         chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
1432         if (IS_ERR(chip->cfgr_clk))
1433                 return PTR_ERR(chip->cfgr_clk);
1434
1435         ret = parse_device_properties(chip);
1436         if (ret)
1437                 return ret;
1438
1439         dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
1440                                 sizeof(*dw->chan), GFP_KERNEL);
1441         if (!dw->chan)
1442                 return -ENOMEM;
1443
1444         ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
1445                                IRQF_SHARED, KBUILD_MODNAME, chip);
1446         if (ret)
1447                 return ret;
1448
1449         INIT_LIST_HEAD(&dw->dma.channels);
1450         for (i = 0; i < hdata->nr_channels; i++) {
1451                 struct axi_dma_chan *chan = &dw->chan[i];
1452
1453                 chan->chip = chip;
1454                 chan->id = i;
1455                 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
1456                 atomic_set(&chan->descs_allocated, 0);
1457
1458                 chan->vc.desc_free = vchan_desc_put;
1459                 vchan_init(&chan->vc, &dw->dma);
1460         }
1461
1462         /* Set capabilities */
1463         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1464         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1465         dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
1466
1467         /* DMA capabilities */
1468         dw->dma.chancnt = hdata->nr_channels;
1469         dw->dma.max_burst = hdata->axi_rw_burst_len;
1470         dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
1471         dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
1472         dw->dma.directions = BIT(DMA_MEM_TO_MEM);
1473         dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1474         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1475
1476         dw->dma.dev = chip->dev;
1477         dw->dma.device_tx_status = dma_chan_tx_status;
1478         dw->dma.device_issue_pending = dma_chan_issue_pending;
1479         dw->dma.device_terminate_all = dma_chan_terminate_all;
1480         dw->dma.device_pause = dma_chan_pause;
1481         dw->dma.device_resume = dma_chan_resume;
1482
1483         dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
1484         dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
1485
1486         dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
1487         dw->dma.device_synchronize = dw_axi_dma_synchronize;
1488         dw->dma.device_config = dw_axi_dma_chan_slave_config;
1489         dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
1490         dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
1491
1492         /*
1493          * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
1494          * supported blocks is 1024. Device register width is 4 bytes.
1495          * Therefore, set constraint to 1024 * 4.
1496          */
1497         dw->dma.dev->dma_parms = &dw->dma_parms;
1498 #ifdef CONFIG_SOC_STARFIVE
1499         dma_set_max_seg_size(&pdev->dev, DMAC_MAX_BLK_SIZE);
1500 #else
1501         dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
1502 #endif
1503         platform_set_drvdata(pdev, chip);
1504
1505         pm_runtime_enable(chip->dev);
1506
1507         /*
1508          * We can't just call pm_runtime_get here instead of
1509          * pm_runtime_get_noresume + axi_dma_resume because we need
1510          * driver to work also without Runtime PM.
1511          */
1512         pm_runtime_get_noresume(chip->dev);
1513         ret = axi_dma_resume(chip);
1514         if (ret < 0)
1515                 goto err_pm_disable;
1516
1517         axi_dma_hw_init(chip);
1518
1519         pm_runtime_put(chip->dev);
1520
1521         ret = dmaenginem_async_device_register(&dw->dma);
1522         if (ret)
1523                 goto err_pm_disable;
1524
1525         /* Register with OF helpers for DMA lookups */
1526         ret = of_dma_controller_register(pdev->dev.of_node,
1527                                          dw_axi_dma_of_xlate, dw);
1528         if (ret < 0)
1529                 dev_warn(&pdev->dev,
1530                          "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
1531
1532         dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
1533                  dw->hdata->nr_channels);
1534
1535         return 0;
1536
1537 err_pm_disable:
1538         pm_runtime_disable(chip->dev);
1539
1540         return ret;
1541 }
1542
1543 static int dw_remove(struct platform_device *pdev)
1544 {
1545         struct axi_dma_chip *chip = platform_get_drvdata(pdev);
1546         struct dw_axi_dma *dw = chip->dw;
1547         struct axi_dma_chan *chan, *_chan;
1548         u32 i;
1549
1550         /* Enable clk before accessing to registers */
1551         clk_prepare_enable(chip->cfgr_clk);
1552         clk_prepare_enable(chip->core_clk);
1553         axi_dma_irq_disable(chip);
1554         for (i = 0; i < dw->hdata->nr_channels; i++) {
1555                 axi_chan_disable(&chip->dw->chan[i]);
1556                 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
1557         }
1558         axi_dma_disable(chip);
1559
1560         pm_runtime_disable(chip->dev);
1561         axi_dma_suspend(chip);
1562
1563         devm_free_irq(chip->dev, chip->irq, chip);
1564
1565         of_dma_controller_free(chip->dev->of_node);
1566
1567         list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
1568                         vc.chan.device_node) {
1569                 list_del(&chan->vc.chan.device_node);
1570                 tasklet_kill(&chan->vc.task);
1571         }
1572
1573         return 0;
1574 }
1575
1576 static const struct dev_pm_ops dw_axi_dma_pm_ops = {
1577         SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL)
1578 };
1579
1580 static const struct of_device_id dw_dma_of_id_table[] = {
1581         { .compatible = "snps,axi-dma-1.01a" },
1582         { .compatible = "intel,kmb-axi-dma" },
1583         {}
1584 };
1585 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
1586
1587 static struct platform_driver dw_driver = {
1588         .probe          = dw_probe,
1589         .remove         = dw_remove,
1590         .driver = {
1591                 .name   = KBUILD_MODNAME,
1592                 .of_match_table = dw_dma_of_id_table,
1593                 .pm = &dw_axi_dma_pm_ops,
1594         },
1595 };
1596 module_platform_driver(dw_driver);
1597
1598 MODULE_LICENSE("GPL v2");
1599 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver");
1600 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");