drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
   3
   4 /*
   5  * Synopsys DesignWare AXI DMA Controller driver.
   6  *
   7  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
   8  */
   9
  10 #include <linux/bitops.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/dmapool.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/err.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/io-64-nonatomic-lo-hi.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/property.h>
  28 #include <linux/slab.h>
  29 #include <linux/types.h>
  30
  31 #include "dw-axi-dmac.h"
  32 #include "../dmaengine.h"
  33 #include "../virt-dma.h"
  34
  35 /*
  36  * The set of bus widths supported by the DMA controller. DW AXI DMAC supports
  37  * master data bus width up to 512 bits (for both AXI master interfaces), but
  38  * it depends on IP block configuration.
  39  */
  40 #define AXI_DMA_BUSWIDTHS                 \
  41         (DMA_SLAVE_BUSWIDTH_1_BYTE      | \
  42         DMA_SLAVE_BUSWIDTH_2_BYTES      | \
  43         DMA_SLAVE_BUSWIDTH_4_BYTES      | \
  44         DMA_SLAVE_BUSWIDTH_8_BYTES      | \
  45         DMA_SLAVE_BUSWIDTH_16_BYTES     | \
  46         DMA_SLAVE_BUSWIDTH_32_BYTES     | \
  47         DMA_SLAVE_BUSWIDTH_64_BYTES)
  48
  49 static inline void
  50 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
  51 {
  52         iowrite32(val, chip->regs + reg);
  53 }
  54
  55 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg)
  56 {
  57         return ioread32(chip->regs + reg);
  58 }
  59
  60 static inline void
  61 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
  62 {
  63         iowrite32(val, chan->chan_regs + reg);
  64 }
  65
  66 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg)
  67 {
  68         return ioread32(chan->chan_regs + reg);
  69 }
  70
  71 static inline void
  72 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
  73 {
  74         /*
  75          * We split one 64 bit write for two 32 bit write as some HW doesn't
  76          * support 64 bit access.
  77          */
  78         iowrite32(lower_32_bits(val), chan->chan_regs + reg);
  79         iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
  80 }
  81
  82 static inline void axi_chan_config_write(struct axi_dma_chan *chan,
  83                                          struct axi_dma_chan_config *config)
  84 {
  85         u32 cfg_lo, cfg_hi;
  86
  87         cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
  88                   config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
  89         if (chan->chip->dw->hdata->reg_map_8_channels) {
  90                 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
  91                          config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
  92                          config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
  93                          config->src_per << CH_CFG_H_SRC_PER_POS |
  94                          config->dst_per << CH_CFG_H_DST_PER_POS |
  95                          config->prior << CH_CFG_H_PRIORITY_POS;
  96         } else {
  97                 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS |
  98                           config->dst_per << CH_CFG2_L_DST_PER_POS;
  99                 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS |
 100                          config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS |
 101                          config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS |
 102                          config->prior << CH_CFG2_H_PRIORITY_POS;
 103         }
 104         axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo);
 105         axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi);
 106 }
 107
 108 static inline void axi_dma_disable(struct axi_dma_chip *chip)
 109 {
 110         u32 val;
 111
 112         val = axi_dma_ioread32(chip, DMAC_CFG);
 113         val &= ~DMAC_EN_MASK;
 114         axi_dma_iowrite32(chip, DMAC_CFG, val);
 115 }
 116
 117 static inline void axi_dma_enable(struct axi_dma_chip *chip)
 118 {
 119         u32 val;
 120
 121         val = axi_dma_ioread32(chip, DMAC_CFG);
 122         val |= DMAC_EN_MASK;
 123         axi_dma_iowrite32(chip, DMAC_CFG, val);
 124 }
 125
 126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip)
 127 {
 128         u32 val;
 129
 130         val = axi_dma_ioread32(chip, DMAC_CFG);
 131         val &= ~INT_EN_MASK;
 132         axi_dma_iowrite32(chip, DMAC_CFG, val);
 133 }
 134
 135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip)
 136 {
 137         u32 val;
 138
 139         val = axi_dma_ioread32(chip, DMAC_CFG);
 140         val |= INT_EN_MASK;
 141         axi_dma_iowrite32(chip, DMAC_CFG, val);
 142 }
 143
 144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask)
 145 {
 146         u32 val;
 147
 148         if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) {
 149                 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE);
 150         } else {
 151                 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
 152                 val &= ~irq_mask;
 153                 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
 154         }
 155 }
 156
 157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask)
 158 {
 159         axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask);
 160 }
 161
 162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask)
 163 {
 164         axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask);
 165 }
 166
 167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask)
 168 {
 169         axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask);
 170 }
 171
 172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan)
 173 {
 174         return axi_chan_ioread32(chan, CH_INTSTATUS);
 175 }
 176
 177 static inline void axi_chan_disable(struct axi_dma_chan *chan)
 178 {
 179         u32 val;
 180
 181         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 182         val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
 183         if (chan->chip->dw->hdata->reg_map_8_channels)
 184                 val |=   BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
 185         else
 186                 val |=   BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
 187         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 188 }
 189
 190 static inline void axi_chan_enable(struct axi_dma_chan *chan)
 191 {
 192         u32 val;
 193
 194         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 195         if (chan->chip->dw->hdata->reg_map_8_channels)
 196                 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
 197                         BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
 198         else
 199                 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
 200                         BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT;
 201         axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
 202 }
 203
 204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
 205 {
 206         u32 val;
 207
 208         val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
 209
 210         return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
 211 }
 212
 213 static void axi_dma_hw_init(struct axi_dma_chip *chip)
 214 {
 215         int ret;
 216         u32 i;
 217
 218         for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
 219                 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
 220                 axi_chan_disable(&chip->dw->chan[i]);
 221         }
 222         ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
 223         if (ret)
 224                 dev_warn(chip->dev, "Unable to set coherent mask\n");
 225 }
 226
 227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
 228                                    dma_addr_t dst, size_t len)
 229 {
 230         u32 max_width = chan->chip->dw->hdata->m_data_width;
 231
 232         return __ffs(src | dst | len | BIT(max_width));
 233 }
 234
 235 static inline const char *axi_chan_name(struct axi_dma_chan *chan)
 236 {
 237         return dma_chan_name(&chan->vc.chan);
 238 }
 239
 240 static struct axi_dma_desc *axi_desc_alloc(u32 num)
 241 {
 242         struct axi_dma_desc *desc;
 243
 244         desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
 245         if (!desc)
 246                 return NULL;
 247
 248         desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
 249         if (!desc->hw_desc) {
 250                 kfree(desc);
 251                 return NULL;
 252         }
 253
 254         return desc;
 255 }
 256
 257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
 258                                         dma_addr_t *addr)
 259 {
 260         struct axi_dma_lli *lli;
 261         dma_addr_t phys;
 262
 263         lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
 264         if (unlikely(!lli)) {
 265                 dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
 266                         axi_chan_name(chan));
 267                 return NULL;
 268         }
 269
 270         atomic_inc(&chan->descs_allocated);
 271         *addr = phys;
 272
 273         return lli;
 274 }
 275
 276 static void axi_desc_put(struct axi_dma_desc *desc)
 277 {
 278         struct axi_dma_chan *chan = desc->chan;
 279         int count = atomic_read(&chan->descs_allocated);
 280         struct axi_dma_hw_desc *hw_desc;
 281         int descs_put;
 282
 283         for (descs_put = 0; descs_put < count; descs_put++) {
 284                 hw_desc = &desc->hw_desc[descs_put];
 285                 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
 286         }
 287
 288         kfree(desc->hw_desc);
 289         kfree(desc);
 290         atomic_sub(descs_put, &chan->descs_allocated);
 291         dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
 292                 axi_chan_name(chan), descs_put,
 293                 atomic_read(&chan->descs_allocated));
 294 }
 295
 296 static void vchan_desc_put(struct virt_dma_desc *vdesc)
 297 {
 298         axi_desc_put(vd_to_axi_desc(vdesc));
 299 }
 300
 301 static enum dma_status
 302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
 303                   struct dma_tx_state *txstate)
 304 {
 305         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 306         struct virt_dma_desc *vdesc;
 307         enum dma_status status;
 308         u32 completed_length;
 309         unsigned long flags;
 310         u32 completed_blocks;
 311         size_t bytes = 0;
 312         u32 length;
 313         u32 len;
 314
 315         status = dma_cookie_status(dchan, cookie, txstate);
 316         if (status == DMA_COMPLETE || !txstate)
 317                 return status;
 318
 319         spin_lock_irqsave(&chan->vc.lock, flags);
 320
 321         vdesc = vchan_find_desc(&chan->vc, cookie);
 322         if (vdesc) {
 323                 length = vd_to_axi_desc(vdesc)->length;
 324                 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
 325                 len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
 326                 completed_length = completed_blocks * len;
 327                 bytes = length - completed_length;
 328         } else {
 329                 bytes = vd_to_axi_desc(vdesc)->length;
 330         }
 331
 332         spin_unlock_irqrestore(&chan->vc.lock, flags);
 333         dma_set_residue(txstate, bytes);
 334
 335         return status;
 336 }
 337
 338 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 339 {
 340         desc->lli->llp = cpu_to_le64(adr);
 341 }
 342
 343 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
 344 {
 345         axi_chan_iowrite64(chan, CH_LLP, adr);
 346 }
 347
 348 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set)
 349 {
 350         u32 offset = DMAC_APB_BYTE_WR_CH_EN;
 351         u32 reg_width, val;
 352
 353         if (!chan->chip->apb_regs) {
 354                 dev_dbg(chan->chip->dev, "apb_regs not initialized\n");
 355                 return;
 356         }
 357
 358         reg_width = __ffs(chan->config.dst_addr_width);
 359         if (reg_width == DWAXIDMAC_TRANS_WIDTH_16)
 360                 offset = DMAC_APB_HALFWORD_WR_CH_EN;
 361
 362         val = ioread32(chan->chip->apb_regs + offset);
 363
 364         if (set)
 365                 val |= BIT(chan->id);
 366         else
 367                 val &= ~BIT(chan->id);
 368
 369         iowrite32(val, chan->chip->apb_regs + offset);
 370 }
 371 /* Called in chan locked context */
 372 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
 373                                       struct axi_dma_desc *first)
 374 {
 375         u32 priority = chan->chip->dw->hdata->priority[chan->id];
 376         struct axi_dma_chan_config config = {};
 377         u32 irq_mask;
 378         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 379
 380         chan->is_err = false;
 381         if (unlikely(axi_chan_is_hw_enable(chan))) {
 382                 dev_err(chan2dev(chan), "%s is non-idle!\n",
 383                         axi_chan_name(chan));
 384
 385                 axi_chan_disable(chan);
 386                 chan->is_err = true;
 387         }
 388
 389         axi_dma_enable(chan->chip);
 390
 391         config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
 392         config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL;
 393         config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC;
 394         config.prior = priority;
 395         config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW;
 396         config.hs_sel_src = DWAXIDMAC_HS_SEL_HW;
 397         switch (chan->direction) {
 398         case DMA_MEM_TO_DEV:
 399                 dw_axi_dma_set_byte_halfword(chan, true);
 400                 config.tt_fc = chan->config.device_fc ?
 401                                 DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
 402                                 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC;
 403                 if (chan->chip->apb_regs)
 404                         config.dst_per = chan->id;
 405                 else
 406                         config.dst_per = chan->hw_handshake_num;
 407                 break;
 408         case DMA_DEV_TO_MEM:
 409                 config.tt_fc = chan->config.device_fc ?
 410                                 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
 411                                 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC;
 412                 if (chan->chip->apb_regs)
 413                         config.src_per = chan->id;
 414                 else
 415                         config.src_per = chan->hw_handshake_num;
 416                 break;
 417         default:
 418                 break;
 419         }
 420         axi_chan_config_write(chan, &config);
 421
 422         write_chan_llp(chan, first->hw_desc[0].llp | lms);
 423
 424         irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
 425         axi_chan_irq_sig_set(chan, irq_mask);
 426
 427         /* Generate 'suspend' status but don't generate interrupt */
 428         irq_mask |= DWAXIDMAC_IRQ_SUSPENDED;
 429         axi_chan_irq_set(chan, irq_mask);
 430
 431         axi_chan_enable(chan);
 432 }
 433
 434 static void axi_chan_start_first_queued(struct axi_dma_chan *chan)
 435 {
 436         struct axi_dma_desc *desc;
 437         struct virt_dma_desc *vd;
 438
 439         vd = vchan_next_desc(&chan->vc);
 440         if (!vd)
 441                 return;
 442
 443         desc = vd_to_axi_desc(vd);
 444         dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan),
 445                 vd->tx.cookie);
 446         axi_chan_block_xfer_start(chan, desc);
 447 }
 448
 449 static void dma_chan_issue_pending(struct dma_chan *dchan)
 450 {
 451         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 452         unsigned long flags;
 453
 454         spin_lock_irqsave(&chan->vc.lock, flags);
 455         if (vchan_issue_pending(&chan->vc))
 456                 axi_chan_start_first_queued(chan);
 457         spin_unlock_irqrestore(&chan->vc.lock, flags);
 458 }
 459
 460 static void dw_axi_dma_synchronize(struct dma_chan *dchan)
 461 {
 462         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 463
 464         vchan_synchronize(&chan->vc);
 465 }
 466
 467 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
 468 {
 469         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 470
 471         /* ASSERT: channel is idle */
 472         if (axi_chan_is_hw_enable(chan)) {
 473                 dev_err(chan2dev(chan), "%s is non-idle!\n",
 474                         axi_chan_name(chan));
 475                 return -EBUSY;
 476         }
 477
 478         /* LLI address must be aligned to a 64-byte boundary */
 479         chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
 480                                           chan->chip->dev,
 481                                           sizeof(struct axi_dma_lli),
 482                                           64, 0);
 483         if (!chan->desc_pool) {
 484                 dev_err(chan2dev(chan), "No memory for descriptors\n");
 485                 return -ENOMEM;
 486         }
 487         dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
 488
 489         pm_runtime_get(chan->chip->dev);
 490
 491         return 0;
 492 }
 493
 494 static void dma_chan_free_chan_resources(struct dma_chan *dchan)
 495 {
 496         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 497
 498         /* ASSERT: channel is idle */
 499         if (axi_chan_is_hw_enable(chan))
 500                 dev_err(dchan2dev(dchan), "%s is non-idle!\n",
 501                         axi_chan_name(chan));
 502
 503         axi_chan_disable(chan);
 504         axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL);
 505
 506         vchan_free_chan_resources(&chan->vc);
 507
 508         dma_pool_destroy(chan->desc_pool);
 509         chan->desc_pool = NULL;
 510         dev_vdbg(dchan2dev(dchan),
 511                  "%s: free resources, descriptor still allocated: %u\n",
 512                  axi_chan_name(chan), atomic_read(&chan->descs_allocated));
 513
 514         pm_runtime_put(chan->chip->dev);
 515 }
 516
 517 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
 518 {
 519         struct axi_dma_chip *chip = chan->chip;
 520         unsigned long reg_value, val;
 521
 522         if (!chip->apb_regs) {
 523                 dev_err(chip->dev, "apb_regs not initialized\n");
 524                 return;
 525         }
 526
 527         /*
 528          * An unused DMA channel has a default value of 0x3F.
 529          * Lock the DMA channel by assign a handshake number to the channel.
 530          * Unlock the DMA channel by assign 0x3F to the channel.
 531          */
 532         if (set)
 533                 val = chan->hw_handshake_num;
 534         else
 535                 val = UNUSED_CHANNEL;
 536
 537         reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
 538
 539         /* Channel is already allocated, set handshake as per channel ID */
 540         /* 64 bit write should handle for 8 channels */
 541
 542         reg_value &= ~(DMA_APB_HS_SEL_MASK <<
 543                         (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
 544         reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
 545         lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
 546
 547         return;
 548 }
 549
 550 /*
 551  * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
 552  * as 1, it understands that the current block is the final block in the
 553  * transfer and completes the DMA transfer operation at the end of current
 554  * block transfer.
 555  */
 556 static void set_desc_last(struct axi_dma_hw_desc *desc)
 557 {
 558         u32 val;
 559
 560         val = le32_to_cpu(desc->lli->ctl_hi);
 561         val |= CH_CTL_H_LLI_LAST;
 562         desc->lli->ctl_hi = cpu_to_le32(val);
 563 }
 564
 565 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 566 {
 567         desc->lli->sar = cpu_to_le64(adr);
 568 }
 569
 570 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
 571 {
 572         desc->lli->dar = cpu_to_le64(adr);
 573 }
 574
 575 static void set_desc_src_master(struct axi_dma_hw_desc *desc)
 576 {
 577         u32 val;
 578
 579         /* Select AXI0 for source master */
 580         val = le32_to_cpu(desc->lli->ctl_lo);
 581         val &= ~CH_CTL_L_SRC_MAST;
 582         desc->lli->ctl_lo = cpu_to_le32(val);
 583 }
 584
 585 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
 586                                  struct axi_dma_desc *desc)
 587 {
 588         u32 val;
 589
 590         /* Select AXI1 for source master if available */
 591         val = le32_to_cpu(hw_desc->lli->ctl_lo);
 592         if (desc->chan->chip->dw->hdata->nr_masters > 1)
 593                 val |= CH_CTL_L_DST_MAST;
 594         else
 595                 val &= ~CH_CTL_L_DST_MAST;
 596
 597         hw_desc->lli->ctl_lo = cpu_to_le32(val);
 598 }
 599
 600 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
 601                                   struct axi_dma_hw_desc *hw_desc,
 602                                   dma_addr_t mem_addr, size_t len)
 603 {
 604         unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
 605         unsigned int reg_width;
 606         unsigned int mem_width;
 607         dma_addr_t device_addr;
 608         size_t axi_block_ts;
 609         size_t block_ts;
 610         u32 ctllo, ctlhi;
 611         u32 burst_len;
 612
 613         axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 614
 615         mem_width = __ffs(data_width | mem_addr | len);
 616         if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
 617                 mem_width = DWAXIDMAC_TRANS_WIDTH_32;
 618
 619         if (!IS_ALIGNED(mem_addr, 4)) {
 620                 dev_err(chan->chip->dev, "invalid buffer alignment\n");
 621                 return -EINVAL;
 622         }
 623
 624         switch (chan->direction) {
 625         case DMA_MEM_TO_DEV:
 626                 reg_width = __ffs(chan->config.dst_addr_width);
 627                 device_addr = chan->config.dst_addr;
 628                 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
 629                         mem_width << CH_CTL_L_SRC_WIDTH_POS |
 630                         DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
 631                         DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
 632                 block_ts = len >> mem_width;
 633                 break;
 634         case DMA_DEV_TO_MEM:
 635                 reg_width = __ffs(chan->config.src_addr_width);
 636                 device_addr = chan->config.src_addr;
 637                 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
 638                         mem_width << CH_CTL_L_DST_WIDTH_POS |
 639                         DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
 640                         DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
 641                 block_ts = len >> reg_width;
 642                 break;
 643         default:
 644                 return -EINVAL;
 645         }
 646
 647         if (block_ts > axi_block_ts)
 648                 return -EINVAL;
 649
 650         hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
 651         if (unlikely(!hw_desc->lli))
 652                 return -ENOMEM;
 653
 654         ctlhi = CH_CTL_H_LLI_VALID;
 655
 656         if (chan->chip->dw->hdata->restrict_axi_burst_len) {
 657                 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
 658                 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
 659                          burst_len << CH_CTL_H_ARLEN_POS |
 660                          burst_len << CH_CTL_H_AWLEN_POS;
 661         }
 662
 663         hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
 664
 665         if (chan->direction == DMA_MEM_TO_DEV) {
 666                 write_desc_sar(hw_desc, mem_addr);
 667                 write_desc_dar(hw_desc, device_addr);
 668         } else {
 669                 write_desc_sar(hw_desc, device_addr);
 670                 write_desc_dar(hw_desc, mem_addr);
 671         }
 672
 673         hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
 674
 675         ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
 676                  DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
 677         hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
 678
 679         set_desc_src_master(hw_desc);
 680
 681         hw_desc->len = len;
 682         return 0;
 683 }
 684
 685 static size_t calculate_block_len(struct axi_dma_chan *chan,
 686                                   dma_addr_t dma_addr, size_t buf_len,
 687                                   enum dma_transfer_direction direction)
 688 {
 689         u32 data_width, reg_width, mem_width;
 690         size_t axi_block_ts, block_len;
 691
 692         axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 693
 694         switch (direction) {
 695         case DMA_MEM_TO_DEV:
 696                 data_width = BIT(chan->chip->dw->hdata->m_data_width);
 697                 mem_width = __ffs(data_width | dma_addr | buf_len);
 698                 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
 699                         mem_width = DWAXIDMAC_TRANS_WIDTH_32;
 700
 701                 block_len = axi_block_ts << mem_width;
 702                 break;
 703         case DMA_DEV_TO_MEM:
 704                 reg_width = __ffs(chan->config.src_addr_width);
 705                 block_len = axi_block_ts << reg_width;
 706                 break;
 707         default:
 708                 block_len = 0;
 709         }
 710
 711         return block_len;
 712 }
 713
 714 static struct dma_async_tx_descriptor *
 715 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
 716                             size_t buf_len, size_t period_len,
 717                             enum dma_transfer_direction direction,
 718                             unsigned long flags)
 719 {
 720         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 721         struct axi_dma_hw_desc *hw_desc = NULL;
 722         struct axi_dma_desc *desc = NULL;
 723         dma_addr_t src_addr = dma_addr;
 724         u32 num_periods, num_segments;
 725         size_t axi_block_len;
 726         u32 total_segments;
 727         u32 segment_len;
 728         unsigned int i;
 729         int status;
 730         u64 llp = 0;
 731         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 732
 733         num_periods = buf_len / period_len;
 734
 735         axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
 736         if (axi_block_len == 0)
 737                 return NULL;
 738
 739         num_segments = DIV_ROUND_UP(period_len, axi_block_len);
 740         segment_len = DIV_ROUND_UP(period_len, num_segments);
 741
 742         total_segments = num_periods * num_segments;
 743
 744         desc = axi_desc_alloc(total_segments);
 745         if (unlikely(!desc))
 746                 goto err_desc_get;
 747
 748         chan->direction = direction;
 749         desc->chan = chan;
 750         chan->cyclic = true;
 751         desc->length = 0;
 752         desc->period_len = period_len;
 753
 754         for (i = 0; i < total_segments; i++) {
 755                 hw_desc = &desc->hw_desc[i];
 756
 757                 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
 758                                                 segment_len);
 759                 if (status < 0)
 760                         goto err_desc_get;
 761
 762                 desc->length += hw_desc->len;
 763                 /* Set end-of-link to the linked descriptor, so that cyclic
 764                  * callback function can be triggered during interrupt.
 765                  */
 766                 set_desc_last(hw_desc);
 767
 768                 src_addr += segment_len;
 769         }
 770
 771         llp = desc->hw_desc[0].llp;
 772
 773         /* Managed transfer list */
 774         do {
 775                 hw_desc = &desc->hw_desc[--total_segments];
 776                 write_desc_llp(hw_desc, llp | lms);
 777                 llp = hw_desc->llp;
 778         } while (total_segments);
 779
 780         dw_axi_dma_set_hw_channel(chan, true);
 781
 782         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 783
 784 err_desc_get:
 785         if (desc)
 786                 axi_desc_put(desc);
 787
 788         return NULL;
 789 }
 790
 791 static struct dma_async_tx_descriptor *
 792 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
 793                               unsigned int sg_len,
 794                               enum dma_transfer_direction direction,
 795                               unsigned long flags, void *context)
 796 {
 797         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 798         struct axi_dma_hw_desc *hw_desc = NULL;
 799         struct axi_dma_desc *desc = NULL;
 800         u32 num_segments, segment_len;
 801         unsigned int loop = 0;
 802         struct scatterlist *sg;
 803         size_t axi_block_len;
 804         u32 len, num_sgs = 0;
 805         unsigned int i;
 806         dma_addr_t mem;
 807         int status;
 808         u64 llp = 0;
 809         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 810
 811         if (unlikely(!is_slave_direction(direction) || !sg_len))
 812                 return NULL;
 813
 814         mem = sg_dma_address(sgl);
 815         len = sg_dma_len(sgl);
 816
 817         axi_block_len = calculate_block_len(chan, mem, len, direction);
 818         if (axi_block_len == 0)
 819                 return NULL;
 820
 821         for_each_sg(sgl, sg, sg_len, i)
 822                 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
 823
 824         desc = axi_desc_alloc(num_sgs);
 825         if (unlikely(!desc))
 826                 goto err_desc_get;
 827
 828         desc->chan = chan;
 829         desc->length = 0;
 830         chan->direction = direction;
 831
 832         for_each_sg(sgl, sg, sg_len, i) {
 833                 mem = sg_dma_address(sg);
 834                 len = sg_dma_len(sg);
 835                 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
 836                 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
 837
 838                 do {
 839                         hw_desc = &desc->hw_desc[loop++];
 840                         status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
 841                         if (status < 0)
 842                                 goto err_desc_get;
 843
 844                         desc->length += hw_desc->len;
 845                         len -= segment_len;
 846                         mem += segment_len;
 847                 } while (len >= segment_len);
 848         }
 849
 850         /* Set end-of-link to the last link descriptor of list */
 851         set_desc_last(&desc->hw_desc[num_sgs - 1]);
 852
 853         /* Managed transfer list */
 854         do {
 855                 hw_desc = &desc->hw_desc[--num_sgs];
 856                 write_desc_llp(hw_desc, llp | lms);
 857                 llp = hw_desc->llp;
 858         } while (num_sgs);
 859
 860         dw_axi_dma_set_hw_channel(chan, true);
 861
 862         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 863
 864 err_desc_get:
 865         if (desc)
 866                 axi_desc_put(desc);
 867
 868         return NULL;
 869 }
 870
 871 static struct dma_async_tx_descriptor *
 872 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
 873                          dma_addr_t src_adr, size_t len, unsigned long flags)
 874 {
 875         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 876         size_t block_ts, max_block_ts, xfer_len;
 877         struct axi_dma_hw_desc *hw_desc = NULL;
 878         struct axi_dma_desc *desc = NULL;
 879         u32 xfer_width, reg, num;
 880         u64 llp = 0;
 881         u8 lms = 0; /* Select AXI0 master for LLI fetching */
 882
 883         dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
 884                 axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
 885
 886         max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
 887         xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
 888         num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
 889         desc = axi_desc_alloc(num);
 890         if (unlikely(!desc))
 891                 goto err_desc_get;
 892
 893         desc->chan = chan;
 894         num = 0;
 895         desc->length = 0;
 896         while (len) {
 897                 xfer_len = len;
 898
 899                 hw_desc = &desc->hw_desc[num];
 900                 /*
 901                  * Take care for the alignment.
 902                  * Actually source and destination widths can be different, but
 903                  * make them same to be simpler.
 904                  */
 905                 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len);
 906
 907                 /*
 908                  * block_ts indicates the total number of data of width
 909                  * to be transferred in a DMA block transfer.
 910                  * BLOCK_TS register should be set to block_ts - 1
 911                  */
 912                 block_ts = xfer_len >> xfer_width;
 913                 if (block_ts > max_block_ts) {
 914                         block_ts = max_block_ts;
 915                         xfer_len = max_block_ts << xfer_width;
 916                 }
 917
 918                 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
 919                 if (unlikely(!hw_desc->lli))
 920                         goto err_desc_get;
 921
 922                 write_desc_sar(hw_desc, src_adr);
 923                 write_desc_dar(hw_desc, dst_adr);
 924                 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
 925
 926                 reg = CH_CTL_H_LLI_VALID;
 927                 if (chan->chip->dw->hdata->restrict_axi_burst_len) {
 928                         u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
 929
 930                         reg |= (CH_CTL_H_ARLEN_EN |
 931                                 burst_len << CH_CTL_H_ARLEN_POS |
 932                                 CH_CTL_H_AWLEN_EN |
 933                                 burst_len << CH_CTL_H_AWLEN_POS);
 934                 }
 935                 hw_desc->lli->ctl_hi = cpu_to_le32(reg);
 936
 937                 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
 938                        DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
 939                        xfer_width << CH_CTL_L_DST_WIDTH_POS |
 940                        xfer_width << CH_CTL_L_SRC_WIDTH_POS |
 941                        DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
 942                        DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
 943                 hw_desc->lli->ctl_lo = cpu_to_le32(reg);
 944
 945                 set_desc_src_master(hw_desc);
 946                 set_desc_dest_master(hw_desc, desc);
 947
 948                 hw_desc->len = xfer_len;
 949                 desc->length += hw_desc->len;
 950                 /* update the length and addresses for the next loop cycle */
 951                 len -= xfer_len;
 952                 dst_adr += xfer_len;
 953                 src_adr += xfer_len;
 954                 num++;
 955         }
 956
 957         /* Set end-of-link to the last link descriptor of list */
 958         set_desc_last(&desc->hw_desc[num - 1]);
 959         /* Managed transfer list */
 960         do {
 961                 hw_desc = &desc->hw_desc[--num];
 962                 write_desc_llp(hw_desc, llp | lms);
 963                 llp = hw_desc->llp;
 964         } while (num);
 965
 966         return vchan_tx_prep(&chan->vc, &desc->vd, flags);
 967
 968 err_desc_get:
 969         if (desc)
 970                 axi_desc_put(desc);
 971         return NULL;
 972 }
 973
 974 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
 975                                         struct dma_slave_config *config)
 976 {
 977         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
 978
 979         memcpy(&chan->config, config, sizeof(*config));
 980
 981         return 0;
 982 }
 983
 984 static void axi_chan_dump_lli(struct axi_dma_chan *chan,
 985                               struct axi_dma_hw_desc *desc)
 986 {
 987         if (!desc->lli) {
 988                 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n");
 989                 return;
 990         }
 991
 992         dev_err(dchan2dev(&chan->vc.chan),
 993                 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
 994                 le64_to_cpu(desc->lli->sar),
 995                 le64_to_cpu(desc->lli->dar),
 996                 le64_to_cpu(desc->lli->llp),
 997                 le32_to_cpu(desc->lli->block_ts_lo),
 998                 le32_to_cpu(desc->lli->ctl_hi),
 999                 le32_to_cpu(desc->lli->ctl_lo));
1000 }
1001
1002 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
1003                                    struct axi_dma_desc *desc_head)
1004 {
1005         int count = atomic_read(&chan->descs_allocated);
1006         int i;
1007
1008         for (i = 0; i < count; i++)
1009                 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
1010 }
1011
1012 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
1013 {
1014         struct virt_dma_desc *vd;
1015         unsigned long flags;
1016
1017         spin_lock_irqsave(&chan->vc.lock, flags);
1018
1019         axi_chan_disable(chan);
1020
1021         /* The bad descriptor currently is in the head of vc list */
1022         vd = vchan_next_desc(&chan->vc);
1023         if (!vd) {
1024                 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1025                         axi_chan_name(chan));
1026                 goto out;
1027         }
1028
1029         if (chan->is_err) {
1030                 struct axi_dma_desc *desc = vd_to_axi_desc(vd);
1031
1032                 axi_chan_block_xfer_start(chan, desc);
1033                 chan->is_err = false;
1034                 goto out;
1035         }
1036
1037         /* Remove the completed descriptor from issued list */
1038         list_del(&vd->node);
1039
1040         /* WARN about bad descriptor */
1041         dev_err(chan2dev(chan),
1042                 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n",
1043                 axi_chan_name(chan), vd->tx.cookie, status);
1044         axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd));
1045
1046         vchan_cookie_complete(vd);
1047
1048         /* Try to restart the controller */
1049         axi_chan_start_first_queued(chan);
1050
1051 out:
1052         spin_unlock_irqrestore(&chan->vc.lock, flags);
1053 }
1054
1055 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
1056 {
1057         int count = atomic_read(&chan->descs_allocated);
1058         struct axi_dma_hw_desc *hw_desc;
1059         struct axi_dma_desc *desc;
1060         struct virt_dma_desc *vd;
1061         unsigned long flags;
1062         u64 llp;
1063         int i;
1064
1065         spin_lock_irqsave(&chan->vc.lock, flags);
1066         if (unlikely(axi_chan_is_hw_enable(chan))) {
1067                 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n",
1068                         axi_chan_name(chan));
1069                 axi_chan_disable(chan);
1070         }
1071
1072         /* The completed descriptor currently is in the head of vc list */
1073         vd = vchan_next_desc(&chan->vc);
1074         if (!vd) {
1075                 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n",
1076                         axi_chan_name(chan));
1077                 goto out;
1078         }
1079
1080         if (chan->cyclic) {
1081                 desc = vd_to_axi_desc(vd);
1082                 if (desc) {
1083                         llp = lo_hi_readq(chan->chan_regs + CH_LLP);
1084                         for (i = 0; i < count; i++) {
1085                                 hw_desc = &desc->hw_desc[i];
1086                                 if (hw_desc->llp == llp) {
1087                                         axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
1088                                         hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
1089                                         desc->completed_blocks = i;
1090
1091                                         if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
1092                                                 vchan_cyclic_callback(vd);
1093                                         break;
1094                                 }
1095                         }
1096
1097                         axi_chan_enable(chan);
1098                 }
1099         } else {
1100                 /* Remove the completed descriptor from issued list before completing */
1101                 list_del(&vd->node);
1102                 vchan_cookie_complete(vd);
1103
1104                 /* Submit queued descriptors after processing the completed ones */
1105                 axi_chan_start_first_queued(chan);
1106         }
1107
1108 out:
1109         spin_unlock_irqrestore(&chan->vc.lock, flags);
1110 }
1111
1112 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
1113 {
1114         struct axi_dma_chip *chip = dev_id;
1115         struct dw_axi_dma *dw = chip->dw;
1116         struct axi_dma_chan *chan;
1117
1118         u32 status, i;
1119
1120         /* Disable DMAC interrupts. We'll enable them after processing channels */
1121         axi_dma_irq_disable(chip);
1122
1123         /* Poll, clear and process every channel interrupt status */
1124         for (i = 0; i < dw->hdata->nr_channels; i++) {
1125                 chan = &dw->chan[i];
1126                 status = axi_chan_irq_read(chan);
1127                 axi_chan_irq_clear(chan, status);
1128
1129                 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n",
1130                         axi_chan_name(chan), i, status);
1131
1132                 if (status & DWAXIDMAC_IRQ_ALL_ERR)
1133                         axi_chan_handle_err(chan, status);
1134                 else if (status & DWAXIDMAC_IRQ_DMA_TRF)
1135                         axi_chan_block_xfer_complete(chan);
1136         }
1137
1138         /* Re-enable interrupts */
1139         axi_dma_irq_enable(chip);
1140
1141         return IRQ_HANDLED;
1142 }
1143
1144 static int dma_chan_terminate_all(struct dma_chan *dchan)
1145 {
1146         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1147         u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
1148         unsigned long flags;
1149         u32 val;
1150         int ret;
1151         LIST_HEAD(head);
1152
1153         axi_chan_disable(chan);
1154
1155         ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
1156                                         !(val & chan_active), 1000, 10000);
1157         if (ret == -ETIMEDOUT)
1158                 dev_warn(dchan2dev(dchan),
1159                          "%s failed to stop\n", axi_chan_name(chan));
1160
1161         if (chan->direction != DMA_MEM_TO_MEM)
1162                 dw_axi_dma_set_hw_channel(chan, false);
1163         if (chan->direction == DMA_MEM_TO_DEV)
1164                 dw_axi_dma_set_byte_halfword(chan, false);
1165
1166         spin_lock_irqsave(&chan->vc.lock, flags);
1167
1168         vchan_get_all_descriptors(&chan->vc, &head);
1169
1170         chan->cyclic = false;
1171         spin_unlock_irqrestore(&chan->vc.lock, flags);
1172
1173         vchan_dma_desc_free_list(&chan->vc, &head);
1174
1175         dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan));
1176
1177         return 0;
1178 }
1179
1180 static int dma_chan_pause(struct dma_chan *dchan)
1181 {
1182         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1183         unsigned long flags;
1184         unsigned int timeout = 20; /* timeout iterations */
1185         u32 val;
1186
1187         spin_lock_irqsave(&chan->vc.lock, flags);
1188
1189         if (chan->chip->dw->hdata->reg_map_8_channels) {
1190                 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1191                 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
1192                         BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT;
1193                 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1194         } else {
1195                 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1196                 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT |
1197                         BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT;
1198                 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1199         }
1200
1201         do  {
1202                 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED)
1203                         break;
1204
1205                 udelay(2);
1206         } while (--timeout);
1207
1208         axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED);
1209
1210         chan->is_paused = true;
1211
1212         spin_unlock_irqrestore(&chan->vc.lock, flags);
1213
1214         return timeout ? 0 : -EAGAIN;
1215 }
1216
1217 /* Called in chan locked context */
1218 static inline void axi_chan_resume(struct axi_dma_chan *chan)
1219 {
1220         u32 val;
1221
1222         if (chan->chip->dw->hdata->reg_map_8_channels) {
1223                 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
1224                 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
1225                 val |=  (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
1226                 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
1227         } else {
1228                 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG);
1229                 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT);
1230                 val |=  (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT);
1231                 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val);
1232         }
1233
1234         chan->is_paused = false;
1235 }
1236
1237 static int dma_chan_resume(struct dma_chan *dchan)
1238 {
1239         struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
1240         unsigned long flags;
1241
1242         spin_lock_irqsave(&chan->vc.lock, flags);
1243
1244         if (chan->is_paused)
1245                 axi_chan_resume(chan);
1246
1247         spin_unlock_irqrestore(&chan->vc.lock, flags);
1248
1249         return 0;
1250 }
1251
1252 static int axi_dma_suspend(struct axi_dma_chip *chip)
1253 {
1254         axi_dma_irq_disable(chip);
1255         axi_dma_disable(chip);
1256
1257         clk_disable_unprepare(chip->core_clk);
1258         clk_disable_unprepare(chip->cfgr_clk);
1259
1260         return 0;
1261 }
1262
1263 static int axi_dma_resume(struct axi_dma_chip *chip)
1264 {
1265         int ret;
1266
1267         ret = clk_prepare_enable(chip->cfgr_clk);
1268         if (ret < 0)
1269                 return ret;
1270
1271         ret = clk_prepare_enable(chip->core_clk);
1272         if (ret < 0)
1273                 return ret;
1274
1275         axi_dma_enable(chip);
1276         axi_dma_irq_enable(chip);
1277
1278         return 0;
1279 }
1280
1281 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev)
1282 {
1283         struct axi_dma_chip *chip = dev_get_drvdata(dev);
1284
1285         return axi_dma_suspend(chip);
1286 }
1287
1288 static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
1289 {
1290         struct axi_dma_chip *chip = dev_get_drvdata(dev);
1291
1292         return axi_dma_resume(chip);
1293 }
1294
1295 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
1296                                             struct of_dma *ofdma)
1297 {
1298         struct dw_axi_dma *dw = ofdma->of_dma_data;
1299         struct axi_dma_chan *chan;
1300         struct dma_chan *dchan;
1301
1302         dchan = dma_get_any_slave_channel(&dw->dma);
1303         if (!dchan)
1304                 return NULL;
1305
1306         chan = dchan_to_axi_dma_chan(dchan);
1307         chan->hw_handshake_num = dma_spec->args[0];
1308         return dchan;
1309 }
1310
1311 static int parse_device_properties(struct axi_dma_chip *chip)
1312 {
1313         struct device *dev = chip->dev;
1314         u32 tmp, carr[DMAC_MAX_CHANNELS];
1315         int ret;
1316
1317         ret = device_property_read_u32(dev, "dma-channels", &tmp);
1318         if (ret)
1319                 return ret;
1320         if (tmp == 0 || tmp > DMAC_MAX_CHANNELS)
1321                 return -EINVAL;
1322
1323         chip->dw->hdata->nr_channels = tmp;
1324         if (tmp <= DMA_REG_MAP_CH_REF)
1325                 chip->dw->hdata->reg_map_8_channels = true;
1326
1327         ret = device_property_read_u32(dev, "snps,dma-masters", &tmp);
1328         if (ret)
1329                 return ret;
1330         if (tmp == 0 || tmp > DMAC_MAX_MASTERS)
1331                 return -EINVAL;
1332
1333         chip->dw->hdata->nr_masters = tmp;
1334
1335         ret = device_property_read_u32(dev, "snps,data-width", &tmp);
1336         if (ret)
1337                 return ret;
1338         if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX)
1339                 return -EINVAL;
1340
1341         chip->dw->hdata->m_data_width = tmp;
1342
1343         ret = device_property_read_u32_array(dev, "snps,block-size", carr,
1344                                              chip->dw->hdata->nr_channels);
1345         if (ret)
1346                 return ret;
1347         for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1348                 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE)
1349                         return -EINVAL;
1350
1351                 chip->dw->hdata->block_size[tmp] = carr[tmp];
1352         }
1353
1354         ret = device_property_read_u32_array(dev, "snps,priority", carr,
1355                                              chip->dw->hdata->nr_channels);
1356         if (ret)
1357                 return ret;
1358         /* Priority value must be programmed within [0:nr_channels-1] range */
1359         for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
1360                 if (carr[tmp] >= chip->dw->hdata->nr_channels)
1361                         return -EINVAL;
1362
1363                 chip->dw->hdata->priority[tmp] = carr[tmp];
1364         }
1365
1366         /* axi-max-burst-len is optional property */
1367         ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp);
1368         if (!ret) {
1369                 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1)
1370                         return -EINVAL;
1371                 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1)
1372                         return -EINVAL;
1373
1374                 chip->dw->hdata->restrict_axi_burst_len = true;
1375                 chip->dw->hdata->axi_rw_burst_len = tmp;
1376         }
1377
1378         return 0;
1379 }
1380
1381 static int dw_probe(struct platform_device *pdev)
1382 {
1383         struct device_node *node = pdev->dev.of_node;
1384         struct axi_dma_chip *chip;
1385         struct resource *mem;
1386         struct dw_axi_dma *dw;
1387         struct dw_axi_dma_hcfg *hdata;
1388         u32 i;
1389         int ret;
1390
1391         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1392         if (!chip)
1393                 return -ENOMEM;
1394
1395         dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
1396         if (!dw)
1397                 return -ENOMEM;
1398
1399         hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL);
1400         if (!hdata)
1401                 return -ENOMEM;
1402
1403         chip->dw = dw;
1404         chip->dev = &pdev->dev;
1405         chip->dw->hdata = hdata;
1406
1407         chip->irq = platform_get_irq(pdev, 0);
1408         if (chip->irq < 0)
1409                 return chip->irq;
1410
1411         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412         chip->regs = devm_ioremap_resource(chip->dev, mem);
1413         if (IS_ERR(chip->regs))
1414                 return PTR_ERR(chip->regs);
1415
1416         if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
1417                 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
1418                 if (IS_ERR(chip->apb_regs))
1419                         return PTR_ERR(chip->apb_regs);
1420         }
1421
1422         chip->core_clk = devm_clk_get(chip->dev, "core-clk");
1423         if (IS_ERR(chip->core_clk))
1424                 return PTR_ERR(chip->core_clk);
1425
1426         chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
1427         if (IS_ERR(chip->cfgr_clk))
1428                 return PTR_ERR(chip->cfgr_clk);
1429
1430         ret = parse_device_properties(chip);
1431         if (ret)
1432                 return ret;
1433
1434         dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
1435                                 sizeof(*dw->chan), GFP_KERNEL);
1436         if (!dw->chan)
1437                 return -ENOMEM;
1438
1439         ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt,
1440                                IRQF_SHARED, KBUILD_MODNAME, chip);
1441         if (ret)
1442                 return ret;
1443
1444         INIT_LIST_HEAD(&dw->dma.channels);
1445         for (i = 0; i < hdata->nr_channels; i++) {
1446                 struct axi_dma_chan *chan = &dw->chan[i];
1447
1448                 chan->chip = chip;
1449                 chan->id = i;
1450                 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN;
1451                 atomic_set(&chan->descs_allocated, 0);
1452
1453                 chan->vc.desc_free = vchan_desc_put;
1454                 vchan_init(&chan->vc, &dw->dma);
1455         }
1456
1457         /* Set capabilities */
1458         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1459         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1460         dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
1461
1462         /* DMA capabilities */
1463         dw->dma.chancnt = hdata->nr_channels;
1464         dw->dma.max_burst = hdata->axi_rw_burst_len;
1465         dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
1466         dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
1467         dw->dma.directions = BIT(DMA_MEM_TO_MEM);
1468         dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1469         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1470
1471         dw->dma.dev = chip->dev;
1472         dw->dma.device_tx_status = dma_chan_tx_status;
1473         dw->dma.device_issue_pending = dma_chan_issue_pending;
1474         dw->dma.device_terminate_all = dma_chan_terminate_all;
1475         dw->dma.device_pause = dma_chan_pause;
1476         dw->dma.device_resume = dma_chan_resume;
1477
1478         dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
1479         dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
1480
1481         dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
1482         dw->dma.device_synchronize = dw_axi_dma_synchronize;
1483         dw->dma.device_config = dw_axi_dma_chan_slave_config;
1484         dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
1485         dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
1486
1487         /*
1488          * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
1489          * supported blocks is 1024. Device register width is 4 bytes.
1490          * Therefore, set constraint to 1024 * 4.
1491          */
1492         dw->dma.dev->dma_parms = &dw->dma_parms;
1493         dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
1494         platform_set_drvdata(pdev, chip);
1495
1496         pm_runtime_enable(chip->dev);
1497
1498         /*
1499          * We can't just call pm_runtime_get here instead of
1500          * pm_runtime_get_noresume + axi_dma_resume because we need
1501          * driver to work also without Runtime PM.
1502          */
1503         pm_runtime_get_noresume(chip->dev);
1504         ret = axi_dma_resume(chip);
1505         if (ret < 0)
1506                 goto err_pm_disable;
1507
1508         axi_dma_hw_init(chip);
1509
1510         pm_runtime_put(chip->dev);
1511
1512         ret = dmaenginem_async_device_register(&dw->dma);
1513         if (ret)
1514                 goto err_pm_disable;
1515
1516         /* Register with OF helpers for DMA lookups */
1517         ret = of_dma_controller_register(pdev->dev.of_node,
1518                                          dw_axi_dma_of_xlate, dw);
1519         if (ret < 0)
1520                 dev_warn(&pdev->dev,
1521                          "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
1522
1523         dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
1524                  dw->hdata->nr_channels);
1525
1526         return 0;
1527
1528 err_pm_disable:
1529         pm_runtime_disable(chip->dev);
1530
1531         return ret;
1532 }
1533
1534 static int dw_remove(struct platform_device *pdev)
1535 {
1536         struct axi_dma_chip *chip = platform_get_drvdata(pdev);
1537         struct dw_axi_dma *dw = chip->dw;
1538         struct axi_dma_chan *chan, *_chan;
1539         u32 i;
1540
1541         /* Enable clk before accessing to registers */
1542         clk_prepare_enable(chip->cfgr_clk);
1543         clk_prepare_enable(chip->core_clk);
1544         axi_dma_irq_disable(chip);
1545         for (i = 0; i < dw->hdata->nr_channels; i++) {
1546                 axi_chan_disable(&chip->dw->chan[i]);
1547                 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
1548         }
1549         axi_dma_disable(chip);
1550
1551         pm_runtime_disable(chip->dev);
1552         axi_dma_suspend(chip);
1553
1554         devm_free_irq(chip->dev, chip->irq, chip);
1555
1556         of_dma_controller_free(chip->dev->of_node);
1557
1558         list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
1559                         vc.chan.device_node) {
1560                 list_del(&chan->vc.chan.device_node);
1561                 tasklet_kill(&chan->vc.task);
1562         }
1563
1564         return 0;
1565 }
1566
1567 static const struct dev_pm_ops dw_axi_dma_pm_ops = {
1568         SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL)
1569 };
1570
1571 static const struct of_device_id dw_dma_of_id_table[] = {
1572         { .compatible = "snps,axi-dma-1.01a" },
1573         { .compatible = "intel,kmb-axi-dma" },
1574         {}
1575 };
1576 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
1577
1578 static struct platform_driver dw_driver = {
1579         .probe          = dw_probe,
1580         .remove         = dw_remove,
1581         .driver = {
1582                 .name   = KBUILD_MODNAME,
1583                 .of_match_table = dw_dma_of_id_table,
1584                 .pm = &dw_axi_dma_pm_ops,
1585         },
1586 };
1587 module_platform_driver(dw_driver);
1588
1589 MODULE_LICENSE("GPL v2");
1590 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver");
1591 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");