2 * DMA Engine test module
4 * Copyright (C) 2007 Atmel Corporation
5 * Copyright (C) 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/freezer.h>
17 #include <linux/init.h>
18 #include <linux/kthread.h>
19 #include <linux/sched/task.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/random.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
26 static unsigned int test_buf_size = 16384;
27 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
28 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
30 static char test_channel[20];
31 module_param_string(channel, test_channel, sizeof(test_channel),
33 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
35 static char test_device[32];
36 module_param_string(device, test_device, sizeof(test_device),
38 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
40 static unsigned int threads_per_chan = 1;
41 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(threads_per_chan,
43 "Number of threads to start per channel (default: 1)");
45 static unsigned int max_channels;
46 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
47 MODULE_PARM_DESC(max_channels,
48 "Maximum number of channels to use (default: all)");
50 static unsigned int iterations;
51 module_param(iterations, uint, S_IRUGO | S_IWUSR);
52 MODULE_PARM_DESC(iterations,
53 "Iterations before stopping test (default: infinite)");
55 static unsigned int dmatest;
56 module_param(dmatest, uint, S_IRUGO | S_IWUSR);
57 MODULE_PARM_DESC(dmatest,
58 "dmatest 0-memcpy 1-memset (default: 0)");
60 static unsigned int xor_sources = 3;
61 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
62 MODULE_PARM_DESC(xor_sources,
63 "Number of xor source buffers (default: 3)");
65 static unsigned int pq_sources = 3;
66 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
67 MODULE_PARM_DESC(pq_sources,
68 "Number of p+q source buffers (default: 3)");
70 static int timeout = 3000;
71 module_param(timeout, uint, S_IRUGO | S_IWUSR);
72 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
73 "Pass -1 for infinite timeout");
76 module_param(noverify, bool, S_IRUGO | S_IWUSR);
77 MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
80 module_param(verbose, bool, S_IRUGO | S_IWUSR);
81 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
84 * struct dmatest_params - test parameters.
85 * @buf_size: size of the memcpy test buffer
86 * @channel: bus ID of the channel to test
87 * @device: bus ID of the DMA Engine to test
88 * @threads_per_chan: number of threads to start per channel
89 * @max_channels: maximum number of channels to use
90 * @iterations: iterations before stopping test
91 * @xor_sources: number of xor source buffers
92 * @pq_sources: number of p+q source buffers
93 * @timeout: transfer timeout in msec, -1 for infinite timeout
95 struct dmatest_params {
96 unsigned int buf_size;
99 unsigned int threads_per_chan;
100 unsigned int max_channels;
101 unsigned int iterations;
102 unsigned int xor_sources;
103 unsigned int pq_sources;
109 * struct dmatest_info - test information.
110 * @params: test parameters
111 * @lock: access protection to the fields of this structure
113 static struct dmatest_info {
114 /* Test parameters */
115 struct dmatest_params params;
118 struct list_head channels;
119 unsigned int nr_channels;
123 .channels = LIST_HEAD_INIT(test_info.channels),
124 .lock = __MUTEX_INITIALIZER(test_info.lock),
127 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
128 static int dmatest_run_get(char *val, const struct kernel_param *kp);
129 static const struct kernel_param_ops run_ops = {
130 .set = dmatest_run_set,
131 .get = dmatest_run_get,
133 static bool dmatest_run;
134 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
135 MODULE_PARM_DESC(run, "Run the test (default: false)");
137 /* Maximum amount of mismatched bytes in buffer to print */
138 #define MAX_ERROR_COUNT 32
141 * Initialization patterns. All bytes in the source buffer has bit 7
142 * set, all bytes in the destination buffer has bit 7 cleared.
144 * Bit 6 is set for all bytes which are to be copied by the DMA
145 * engine. Bit 5 is set for all bytes which are to be overwritten by
148 * The remaining bits are the inverse of a counter which increments by
149 * one for each byte address.
151 #define PATTERN_SRC 0x80
152 #define PATTERN_DST 0x00
153 #define PATTERN_COPY 0x40
154 #define PATTERN_OVERWRITE 0x20
155 #define PATTERN_COUNT_MASK 0x1f
156 #define PATTERN_MEMSET_IDX 0x01
158 struct dmatest_thread {
159 struct list_head node;
160 struct dmatest_info *info;
161 struct task_struct *task;
162 struct dma_chan *chan;
167 enum dma_transaction_type type;
171 struct dmatest_chan {
172 struct list_head node;
173 struct dma_chan *chan;
174 struct list_head threads;
177 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
180 static bool is_threaded_test_run(struct dmatest_info *info)
182 struct dmatest_chan *dtc;
184 list_for_each_entry(dtc, &info->channels, node) {
185 struct dmatest_thread *thread;
187 list_for_each_entry(thread, &dtc->threads, node) {
196 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
198 struct dmatest_info *info = &test_info;
199 struct dmatest_params *params = &info->params;
201 if (params->iterations)
202 wait_event(thread_wait, !is_threaded_test_run(info));
204 return param_get_bool(val, kp);
207 static const struct kernel_param_ops wait_ops = {
208 .get = dmatest_wait_get,
209 .set = param_set_bool,
211 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
212 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
214 static bool dmatest_match_channel(struct dmatest_params *params,
215 struct dma_chan *chan)
217 if (params->channel[0] == '\0')
219 return strcmp(dma_chan_name(chan), params->channel) == 0;
222 static bool dmatest_match_device(struct dmatest_params *params,
223 struct dma_device *device)
225 if (params->device[0] == '\0')
227 return strcmp(dev_name(device->dev), params->device) == 0;
230 static unsigned long dmatest_random(void)
234 prandom_bytes(&buf, sizeof(buf));
238 static inline u8 gen_inv_idx(u8 index, bool is_memset)
240 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
242 return ~val & PATTERN_COUNT_MASK;
245 static inline u8 gen_src_value(u8 index, bool is_memset)
247 return PATTERN_SRC | gen_inv_idx(index, is_memset);
250 static inline u8 gen_dst_value(u8 index, bool is_memset)
252 return PATTERN_DST | gen_inv_idx(index, is_memset);
255 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
256 unsigned int buf_size, bool is_memset)
261 for (; (buf = *bufs); bufs++) {
262 for (i = 0; i < start; i++)
263 buf[i] = gen_src_value(i, is_memset);
264 for ( ; i < start + len; i++)
265 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
266 for ( ; i < buf_size; i++)
267 buf[i] = gen_src_value(i, is_memset);
272 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
273 unsigned int buf_size, bool is_memset)
278 for (; (buf = *bufs); bufs++) {
279 for (i = 0; i < start; i++)
280 buf[i] = gen_dst_value(i, is_memset);
281 for ( ; i < start + len; i++)
282 buf[i] = gen_dst_value(i, is_memset) |
284 for ( ; i < buf_size; i++)
285 buf[i] = gen_dst_value(i, is_memset);
289 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
290 unsigned int counter, bool is_srcbuf, bool is_memset)
292 u8 diff = actual ^ pattern;
293 u8 expected = pattern | gen_inv_idx(counter, is_memset);
294 const char *thread_name = current->comm;
297 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
298 thread_name, index, expected, actual);
299 else if ((pattern & PATTERN_COPY)
300 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
301 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
302 thread_name, index, expected, actual);
303 else if (diff & PATTERN_SRC)
304 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
305 thread_name, index, expected, actual);
307 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
308 thread_name, index, expected, actual);
311 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
312 unsigned int end, unsigned int counter, u8 pattern,
313 bool is_srcbuf, bool is_memset)
316 unsigned int error_count = 0;
320 unsigned int counter_orig = counter;
322 for (; (buf = *bufs); bufs++) {
323 counter = counter_orig;
324 for (i = start; i < end; i++) {
326 expected = pattern | gen_inv_idx(counter, is_memset);
327 if (actual != expected) {
328 if (error_count < MAX_ERROR_COUNT)
329 dmatest_mismatch(actual, pattern, i,
338 if (error_count > MAX_ERROR_COUNT)
339 pr_warn("%s: %u errors suppressed\n",
340 current->comm, error_count - MAX_ERROR_COUNT);
345 /* poor man's completion - we want to use wait_event_freezable() on it */
346 struct dmatest_done {
348 wait_queue_head_t *wait;
351 static void dmatest_callback(void *arg)
353 struct dmatest_done *done = arg;
356 wake_up_all(done->wait);
359 static unsigned int min_odd(unsigned int x, unsigned int y)
361 unsigned int val = min(x, y);
363 return val % 2 ? val : val - 1;
366 static void result(const char *err, unsigned int n, unsigned int src_off,
367 unsigned int dst_off, unsigned int len, unsigned long data)
369 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
370 current->comm, n, err, src_off, dst_off, len, data);
373 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
374 unsigned int dst_off, unsigned int len,
377 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
378 current->comm, n, err, src_off, dst_off, len, data);
381 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \
383 result(err, n, src_off, dst_off, len, data); \
385 dbg_result(err, n, src_off, dst_off, len, data);\
388 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
390 unsigned long long per_sec = 1000000;
395 /* drop precision until runtime is 32-bits */
396 while (runtime > UINT_MAX) {
402 do_div(per_sec, runtime);
406 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
408 return dmatest_persec(runtime, len >> 10);
412 * This function repeatedly tests DMA transfers of various lengths and
413 * offsets for a given operation type until it is told to exit by
414 * kthread_stop(). There may be multiple threads running this function
415 * in parallel for a single channel, and there may be multiple channels
416 * being tested in parallel.
418 * Before each test, the source and destination buffer is initialized
419 * with a known pattern. This pattern is different depending on
420 * whether it's in an area which is supposed to be copied or
421 * overwritten, and different in the source and destination buffers.
422 * So if the DMA engine doesn't copy exactly what we tell it to copy,
425 static int dmatest_func(void *data)
427 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
428 struct dmatest_thread *thread = data;
429 struct dmatest_done done = { .wait = &done_wait };
430 struct dmatest_info *info;
431 struct dmatest_params *params;
432 struct dma_chan *chan;
433 struct dma_device *dev;
434 unsigned int error_count;
435 unsigned int failed_tests = 0;
436 unsigned int total_tests = 0;
438 enum dma_status status;
439 enum dma_ctrl_flags flags;
445 ktime_t ktime, start, diff;
446 ktime_t filltime = 0;
447 ktime_t comparetime = 0;
449 unsigned long long total_len = 0;
451 bool is_memset = false;
459 params = &info->params;
462 if (thread->type == DMA_MEMCPY) {
463 align = dev->copy_align;
464 src_cnt = dst_cnt = 1;
465 } else if (thread->type == DMA_MEMSET) {
466 align = dev->fill_align;
467 src_cnt = dst_cnt = 1;
469 } else if (thread->type == DMA_XOR) {
470 /* force odd to ensure dst = src */
471 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
473 align = dev->xor_align;
474 } else if (thread->type == DMA_PQ) {
475 /* force odd to ensure dst = src */
476 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
478 align = dev->pq_align;
480 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
482 goto err_thread_type;
484 for (i = 0; i < src_cnt; i++)
487 goto err_thread_type;
489 thread->srcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
493 thread->usrcs = kcalloc(src_cnt + 1, sizeof(u8 *), GFP_KERNEL);
497 for (i = 0; i < src_cnt; i++) {
498 thread->usrcs[i] = kmalloc(params->buf_size + align,
500 if (!thread->usrcs[i])
503 /* align srcs to alignment restriction */
505 thread->srcs[i] = PTR_ALIGN(thread->usrcs[i], align);
507 thread->srcs[i] = thread->usrcs[i];
509 thread->srcs[i] = NULL;
511 thread->dsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
515 thread->udsts = kcalloc(dst_cnt + 1, sizeof(u8 *), GFP_KERNEL);
519 for (i = 0; i < dst_cnt; i++) {
520 thread->udsts[i] = kmalloc(params->buf_size + align,
522 if (!thread->udsts[i])
525 /* align dsts to alignment restriction */
527 thread->dsts[i] = PTR_ALIGN(thread->udsts[i], align);
529 thread->dsts[i] = thread->udsts[i];
531 thread->dsts[i] = NULL;
533 set_user_nice(current, 10);
536 * src and dst buffers are freed by ourselves below
538 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
541 while (!kthread_should_stop()
542 && !(params->iterations && total_tests >= params->iterations)) {
543 struct dma_async_tx_descriptor *tx = NULL;
544 struct dmaengine_unmap_data *um;
545 dma_addr_t srcs[src_cnt];
547 unsigned int src_off, dst_off, len;
551 /* Check if buffer count fits into map count variable (u8) */
552 if ((src_cnt + dst_cnt) >= 255) {
553 pr_err("too many buffers (%d of 255 supported)\n",
558 if (1 << align > params->buf_size) {
559 pr_err("%u-byte buffer too small for %d-byte alignment\n",
560 params->buf_size, 1 << align);
564 if (params->noverify)
565 len = params->buf_size;
567 len = dmatest_random() % params->buf_size + 1;
569 len = (len >> align) << align;
575 if (params->noverify) {
580 src_off = dmatest_random() % (params->buf_size - len + 1);
581 dst_off = dmatest_random() % (params->buf_size - len + 1);
583 src_off = (src_off >> align) << align;
584 dst_off = (dst_off >> align) << align;
586 dmatest_init_srcs(thread->srcs, src_off, len,
587 params->buf_size, is_memset);
588 dmatest_init_dsts(thread->dsts, dst_off, len,
589 params->buf_size, is_memset);
591 diff = ktime_sub(ktime_get(), start);
592 filltime = ktime_add(filltime, diff);
595 um = dmaengine_get_unmap_data(dev->dev, src_cnt + dst_cnt,
599 result("unmap data NULL", total_tests,
600 src_off, dst_off, len, ret);
604 um->len = params->buf_size;
605 for (i = 0; i < src_cnt; i++) {
606 void *buf = thread->srcs[i];
607 struct page *pg = virt_to_page(buf);
608 unsigned long pg_off = offset_in_page(buf);
610 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
611 um->len, DMA_TO_DEVICE);
612 srcs[i] = um->addr[i] + src_off;
613 ret = dma_mapping_error(dev->dev, um->addr[i]);
615 dmaengine_unmap_put(um);
616 result("src mapping error", total_tests,
617 src_off, dst_off, len, ret);
623 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
624 dsts = &um->addr[src_cnt];
625 for (i = 0; i < dst_cnt; i++) {
626 void *buf = thread->dsts[i];
627 struct page *pg = virt_to_page(buf);
628 unsigned long pg_off = offset_in_page(buf);
630 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
632 ret = dma_mapping_error(dev->dev, dsts[i]);
634 dmaengine_unmap_put(um);
635 result("dst mapping error", total_tests,
636 src_off, dst_off, len, ret);
643 if (thread->type == DMA_MEMCPY)
644 tx = dev->device_prep_dma_memcpy(chan,
646 srcs[0], len, flags);
647 else if (thread->type == DMA_MEMSET)
648 tx = dev->device_prep_dma_memset(chan,
650 *(thread->srcs[0] + src_off),
652 else if (thread->type == DMA_XOR)
653 tx = dev->device_prep_dma_xor(chan,
657 else if (thread->type == DMA_PQ) {
658 dma_addr_t dma_pq[dst_cnt];
660 for (i = 0; i < dst_cnt; i++)
661 dma_pq[i] = dsts[i] + dst_off;
662 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
668 dmaengine_unmap_put(um);
669 result("prep error", total_tests, src_off,
677 tx->callback = dmatest_callback;
678 tx->callback_param = &done;
679 cookie = tx->tx_submit(tx);
681 if (dma_submit_error(cookie)) {
682 dmaengine_unmap_put(um);
683 result("submit error", total_tests, src_off,
689 dma_async_issue_pending(chan);
691 wait_event_freezable_timeout(done_wait, done.done,
692 msecs_to_jiffies(params->timeout));
694 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
698 * We're leaving the timed out dma operation with
699 * dangling pointer to done_wait. To make this
700 * correct, we'll need to allocate wait_done for
701 * each test iteration and perform "who's gonna
702 * free it this time?" dancing. For now, just
705 WARN(1, "dmatest: Kernel stack may be corrupted!!\n");
706 dmaengine_unmap_put(um);
707 result("test timed out", total_tests, src_off, dst_off,
711 } else if (status != DMA_COMPLETE) {
712 dmaengine_unmap_put(um);
713 result(status == DMA_ERROR ?
714 "completion error status" :
715 "completion busy status", total_tests, src_off,
721 dmaengine_unmap_put(um);
723 if (params->noverify) {
724 verbose_result("test passed", total_tests, src_off,
730 pr_debug("%s: verifying source buffer...\n", current->comm);
731 error_count = dmatest_verify(thread->srcs, 0, src_off,
732 0, PATTERN_SRC, true, is_memset);
733 error_count += dmatest_verify(thread->srcs, src_off,
734 src_off + len, src_off,
735 PATTERN_SRC | PATTERN_COPY, true, is_memset);
736 error_count += dmatest_verify(thread->srcs, src_off + len,
737 params->buf_size, src_off + len,
738 PATTERN_SRC, true, is_memset);
740 pr_debug("%s: verifying dest buffer...\n", current->comm);
741 error_count += dmatest_verify(thread->dsts, 0, dst_off,
742 0, PATTERN_DST, false, is_memset);
744 error_count += dmatest_verify(thread->dsts, dst_off,
745 dst_off + len, src_off,
746 PATTERN_SRC | PATTERN_COPY, false, is_memset);
748 error_count += dmatest_verify(thread->dsts, dst_off + len,
749 params->buf_size, dst_off + len,
750 PATTERN_DST, false, is_memset);
752 diff = ktime_sub(ktime_get(), start);
753 comparetime = ktime_add(comparetime, diff);
756 result("data error", total_tests, src_off, dst_off,
760 verbose_result("test passed", total_tests, src_off,
764 ktime = ktime_sub(ktime_get(), ktime);
765 ktime = ktime_sub(ktime, comparetime);
766 ktime = ktime_sub(ktime, filltime);
767 runtime = ktime_to_us(ktime);
771 for (i = 0; thread->udsts[i]; i++)
772 kfree(thread->udsts[i]);
773 kfree(thread->udsts);
778 for (i = 0; thread->usrcs[i]; i++)
779 kfree(thread->usrcs[i]);
780 kfree(thread->usrcs);
786 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
787 current->comm, total_tests, failed_tests,
788 dmatest_persec(runtime, total_tests),
789 dmatest_KBs(runtime, total_len), ret);
791 /* terminate all transfers on specified channels */
793 dmaengine_terminate_all(chan);
796 wake_up(&thread_wait);
801 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
803 struct dmatest_thread *thread;
804 struct dmatest_thread *_thread;
807 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
808 ret = kthread_stop(thread->task);
809 pr_debug("thread %s exited with status %d\n",
810 thread->task->comm, ret);
811 list_del(&thread->node);
812 put_task_struct(thread->task);
816 /* terminate all transfers on specified channels */
817 dmaengine_terminate_all(dtc->chan);
822 static int dmatest_add_threads(struct dmatest_info *info,
823 struct dmatest_chan *dtc, enum dma_transaction_type type)
825 struct dmatest_params *params = &info->params;
826 struct dmatest_thread *thread;
827 struct dma_chan *chan = dtc->chan;
831 if (type == DMA_MEMCPY)
833 else if (type == DMA_MEMSET)
835 else if (type == DMA_XOR)
837 else if (type == DMA_PQ)
842 for (i = 0; i < params->threads_per_chan; i++) {
843 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
845 pr_warn("No memory for %s-%s%u\n",
846 dma_chan_name(chan), op, i);
850 thread->chan = dtc->chan;
853 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
854 dma_chan_name(chan), op, i);
855 if (IS_ERR(thread->task)) {
856 pr_warn("Failed to create thread %s-%s%u\n",
857 dma_chan_name(chan), op, i);
862 /* srcbuf and dstbuf are allocated by the thread itself */
863 get_task_struct(thread->task);
864 list_add_tail(&thread->node, &dtc->threads);
865 wake_up_process(thread->task);
871 static int dmatest_add_channel(struct dmatest_info *info,
872 struct dma_chan *chan)
874 struct dmatest_chan *dtc;
875 struct dma_device *dma_dev = chan->device;
876 unsigned int thread_count = 0;
879 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
881 pr_warn("No memory for %s\n", dma_chan_name(chan));
886 INIT_LIST_HEAD(&dtc->threads);
888 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
890 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
891 thread_count += cnt > 0 ? cnt : 0;
895 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
897 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
898 thread_count += cnt > 0 ? cnt : 0;
902 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
903 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
904 thread_count += cnt > 0 ? cnt : 0;
906 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
907 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
908 thread_count += cnt > 0 ? cnt : 0;
911 pr_info("Started %u threads using %s\n",
912 thread_count, dma_chan_name(chan));
914 list_add_tail(&dtc->node, &info->channels);
920 static bool filter(struct dma_chan *chan, void *param)
922 struct dmatest_params *params = param;
924 if (!dmatest_match_channel(params, chan) ||
925 !dmatest_match_device(params, chan->device))
931 static void request_channels(struct dmatest_info *info,
932 enum dma_transaction_type type)
937 dma_cap_set(type, mask);
939 struct dmatest_params *params = &info->params;
940 struct dma_chan *chan;
942 chan = dma_request_channel(mask, filter, params);
944 if (dmatest_add_channel(info, chan)) {
945 dma_release_channel(chan);
946 break; /* add_channel failed, punt */
949 break; /* no more channels available */
950 if (params->max_channels &&
951 info->nr_channels >= params->max_channels)
952 break; /* we have all we need */
956 static void run_threaded_test(struct dmatest_info *info)
958 struct dmatest_params *params = &info->params;
960 /* Copy test parameters */
961 params->buf_size = test_buf_size;
962 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
963 strlcpy(params->device, strim(test_device), sizeof(params->device));
964 params->threads_per_chan = threads_per_chan;
965 params->max_channels = max_channels;
966 params->iterations = iterations;
967 params->xor_sources = xor_sources;
968 params->pq_sources = pq_sources;
969 params->timeout = timeout;
970 params->noverify = noverify;
972 request_channels(info, DMA_MEMCPY);
973 request_channels(info, DMA_MEMSET);
974 request_channels(info, DMA_XOR);
975 request_channels(info, DMA_PQ);
978 static void stop_threaded_test(struct dmatest_info *info)
980 struct dmatest_chan *dtc, *_dtc;
981 struct dma_chan *chan;
983 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
984 list_del(&dtc->node);
986 dmatest_cleanup_channel(dtc);
987 pr_debug("dropped channel %s\n", dma_chan_name(chan));
988 dma_release_channel(chan);
991 info->nr_channels = 0;
994 static void restart_threaded_test(struct dmatest_info *info, bool run)
996 /* we might be called early to set run=, defer running until all
997 * parameters have been evaluated
1002 /* Stop any running test first */
1003 stop_threaded_test(info);
1005 /* Run test with new parameters */
1006 run_threaded_test(info);
1009 static int dmatest_run_get(char *val, const struct kernel_param *kp)
1011 struct dmatest_info *info = &test_info;
1013 mutex_lock(&info->lock);
1014 if (is_threaded_test_run(info)) {
1017 stop_threaded_test(info);
1018 dmatest_run = false;
1020 mutex_unlock(&info->lock);
1022 return param_get_bool(val, kp);
1025 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1027 struct dmatest_info *info = &test_info;
1030 mutex_lock(&info->lock);
1031 ret = param_set_bool(val, kp);
1033 mutex_unlock(&info->lock);
1037 if (is_threaded_test_run(info))
1039 else if (dmatest_run)
1040 restart_threaded_test(info, dmatest_run);
1042 mutex_unlock(&info->lock);
1047 static int __init dmatest_init(void)
1049 struct dmatest_info *info = &test_info;
1050 struct dmatest_params *params = &info->params;
1053 mutex_lock(&info->lock);
1054 run_threaded_test(info);
1055 mutex_unlock(&info->lock);
1058 if (params->iterations && wait)
1059 wait_event(thread_wait, !is_threaded_test_run(info));
1061 /* module parameters are stable, inittime tests are started,
1062 * let userspace take over 'run' control
1064 info->did_init = true;
1068 /* when compiled-in wait for drivers to load first */
1069 late_initcall(dmatest_init);
1071 static void __exit dmatest_exit(void)
1073 struct dmatest_info *info = &test_info;
1075 mutex_lock(&info->lock);
1076 stop_threaded_test(info);
1077 mutex_unlock(&info->lock);
1079 module_exit(dmatest_exit);
1081 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1082 MODULE_LICENSE("GPL v2");