1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Analog Devices AXI-DMAC core
5 * Copyright 2013-2019 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/fpga/adi-axi-common.h>
27 #include <dt-bindings/dma/axi-dmac.h>
29 #include "dmaengine.h"
33 * The AXI-DMAC is a soft IP core that is used in FPGA designs. The core has
34 * various instantiation parameters which decided the exact feature set support
37 * Each channel of the core has a source interface and a destination interface.
38 * The number of channels and the type of the channel interfaces is selected at
39 * configuration time. A interface can either be a connected to a central memory
40 * interconnect, which allows access to system memory, or it can be connected to
41 * a dedicated bus which is directly connected to a data port on a peripheral.
42 * Given that those are configuration options of the core that are selected when
43 * it is instantiated this means that they can not be changed by software at
44 * runtime. By extension this means that each channel is uni-directional. It can
45 * either be device to memory or memory to device, but not both. Also since the
46 * device side is a dedicated data bus only connected to a single peripheral
47 * there is no address than can or needs to be configured for the device side.
50 #define AXI_DMAC_REG_INTERFACE_DESC 0x10
51 #define AXI_DMAC_DMA_SRC_TYPE_MSK GENMASK(13, 12)
52 #define AXI_DMAC_DMA_SRC_TYPE_GET(x) FIELD_GET(AXI_DMAC_DMA_SRC_TYPE_MSK, x)
53 #define AXI_DMAC_DMA_SRC_WIDTH_MSK GENMASK(11, 8)
54 #define AXI_DMAC_DMA_SRC_WIDTH_GET(x) FIELD_GET(AXI_DMAC_DMA_SRC_WIDTH_MSK, x)
55 #define AXI_DMAC_DMA_DST_TYPE_MSK GENMASK(5, 4)
56 #define AXI_DMAC_DMA_DST_TYPE_GET(x) FIELD_GET(AXI_DMAC_DMA_DST_TYPE_MSK, x)
57 #define AXI_DMAC_DMA_DST_WIDTH_MSK GENMASK(3, 0)
58 #define AXI_DMAC_DMA_DST_WIDTH_GET(x) FIELD_GET(AXI_DMAC_DMA_DST_WIDTH_MSK, x)
59 #define AXI_DMAC_REG_COHERENCY_DESC 0x14
60 #define AXI_DMAC_DST_COHERENT_MSK BIT(0)
61 #define AXI_DMAC_DST_COHERENT_GET(x) FIELD_GET(AXI_DMAC_DST_COHERENT_MSK, x)
63 #define AXI_DMAC_REG_IRQ_MASK 0x80
64 #define AXI_DMAC_REG_IRQ_PENDING 0x84
65 #define AXI_DMAC_REG_IRQ_SOURCE 0x88
67 #define AXI_DMAC_REG_CTRL 0x400
68 #define AXI_DMAC_REG_TRANSFER_ID 0x404
69 #define AXI_DMAC_REG_START_TRANSFER 0x408
70 #define AXI_DMAC_REG_FLAGS 0x40c
71 #define AXI_DMAC_REG_DEST_ADDRESS 0x410
72 #define AXI_DMAC_REG_SRC_ADDRESS 0x414
73 #define AXI_DMAC_REG_X_LENGTH 0x418
74 #define AXI_DMAC_REG_Y_LENGTH 0x41c
75 #define AXI_DMAC_REG_DEST_STRIDE 0x420
76 #define AXI_DMAC_REG_SRC_STRIDE 0x424
77 #define AXI_DMAC_REG_TRANSFER_DONE 0x428
78 #define AXI_DMAC_REG_ACTIVE_TRANSFER_ID 0x42c
79 #define AXI_DMAC_REG_STATUS 0x430
80 #define AXI_DMAC_REG_CURRENT_SRC_ADDR 0x434
81 #define AXI_DMAC_REG_CURRENT_DEST_ADDR 0x438
82 #define AXI_DMAC_REG_PARTIAL_XFER_LEN 0x44c
83 #define AXI_DMAC_REG_PARTIAL_XFER_ID 0x450
85 #define AXI_DMAC_CTRL_ENABLE BIT(0)
86 #define AXI_DMAC_CTRL_PAUSE BIT(1)
88 #define AXI_DMAC_IRQ_SOT BIT(0)
89 #define AXI_DMAC_IRQ_EOT BIT(1)
91 #define AXI_DMAC_FLAG_CYCLIC BIT(0)
92 #define AXI_DMAC_FLAG_LAST BIT(1)
93 #define AXI_DMAC_FLAG_PARTIAL_REPORT BIT(2)
95 #define AXI_DMAC_FLAG_PARTIAL_XFER_DONE BIT(31)
97 /* The maximum ID allocated by the hardware is 31 */
98 #define AXI_DMAC_SG_UNUSED 32U
102 dma_addr_t dest_addr;
105 unsigned int dest_stride;
106 unsigned int src_stride;
108 unsigned int partial_len;
109 bool schedule_when_free;
112 struct axi_dmac_desc {
113 struct virt_dma_desc vdesc;
115 bool have_partial_xfer;
117 unsigned int num_submitted;
118 unsigned int num_completed;
119 unsigned int num_sgs;
120 struct axi_dmac_sg sg[];
123 struct axi_dmac_chan {
124 struct virt_dma_chan vchan;
126 struct axi_dmac_desc *next_desc;
127 struct list_head active_descs;
128 enum dma_transfer_direction direction;
130 unsigned int src_width;
131 unsigned int dest_width;
132 unsigned int src_type;
133 unsigned int dest_type;
135 unsigned int max_length;
136 unsigned int address_align_mask;
137 unsigned int length_align_mask;
139 bool hw_partial_xfer;
150 struct dma_device dma_dev;
151 struct axi_dmac_chan chan;
154 static struct axi_dmac *chan_to_axi_dmac(struct axi_dmac_chan *chan)
156 return container_of(chan->vchan.chan.device, struct axi_dmac,
160 static struct axi_dmac_chan *to_axi_dmac_chan(struct dma_chan *c)
162 return container_of(c, struct axi_dmac_chan, vchan.chan);
165 static struct axi_dmac_desc *to_axi_dmac_desc(struct virt_dma_desc *vdesc)
167 return container_of(vdesc, struct axi_dmac_desc, vdesc);
170 static void axi_dmac_write(struct axi_dmac *axi_dmac, unsigned int reg,
173 writel(val, axi_dmac->base + reg);
176 static int axi_dmac_read(struct axi_dmac *axi_dmac, unsigned int reg)
178 return readl(axi_dmac->base + reg);
181 static int axi_dmac_src_is_mem(struct axi_dmac_chan *chan)
183 return chan->src_type == AXI_DMAC_BUS_TYPE_AXI_MM;
186 static int axi_dmac_dest_is_mem(struct axi_dmac_chan *chan)
188 return chan->dest_type == AXI_DMAC_BUS_TYPE_AXI_MM;
191 static bool axi_dmac_check_len(struct axi_dmac_chan *chan, unsigned int len)
195 if ((len & chan->length_align_mask) != 0) /* Not aligned */
200 static bool axi_dmac_check_addr(struct axi_dmac_chan *chan, dma_addr_t addr)
202 if ((addr & chan->address_align_mask) != 0) /* Not aligned */
207 static void axi_dmac_start_transfer(struct axi_dmac_chan *chan)
209 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
210 struct virt_dma_desc *vdesc;
211 struct axi_dmac_desc *desc;
212 struct axi_dmac_sg *sg;
213 unsigned int flags = 0;
216 val = axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER);
217 if (val) /* Queue is full, wait for the next SOT IRQ */
220 desc = chan->next_desc;
223 vdesc = vchan_next_desc(&chan->vchan);
226 list_move_tail(&vdesc->node, &chan->active_descs);
227 desc = to_axi_dmac_desc(vdesc);
229 sg = &desc->sg[desc->num_submitted];
231 /* Already queued in cyclic mode. Wait for it to finish */
232 if (sg->id != AXI_DMAC_SG_UNUSED) {
233 sg->schedule_when_free = true;
237 desc->num_submitted++;
238 if (desc->num_submitted == desc->num_sgs ||
239 desc->have_partial_xfer) {
241 desc->num_submitted = 0; /* Start again */
243 chan->next_desc = NULL;
244 flags |= AXI_DMAC_FLAG_LAST;
246 chan->next_desc = desc;
249 sg->id = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID);
251 if (axi_dmac_dest_is_mem(chan)) {
252 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, sg->dest_addr);
253 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, sg->dest_stride);
256 if (axi_dmac_src_is_mem(chan)) {
257 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, sg->src_addr);
258 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, sg->src_stride);
262 * If the hardware supports cyclic transfers and there is no callback to
263 * call and only a single segment, enable hw cyclic mode to avoid
264 * unnecessary interrupts.
266 if (chan->hw_cyclic && desc->cyclic && !desc->vdesc.tx.callback &&
268 flags |= AXI_DMAC_FLAG_CYCLIC;
270 if (chan->hw_partial_xfer)
271 flags |= AXI_DMAC_FLAG_PARTIAL_REPORT;
273 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1);
274 axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->y_len - 1);
275 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);
276 axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);
279 static struct axi_dmac_desc *axi_dmac_active_desc(struct axi_dmac_chan *chan)
281 return list_first_entry_or_null(&chan->active_descs,
282 struct axi_dmac_desc, vdesc.node);
285 static inline unsigned int axi_dmac_total_sg_bytes(struct axi_dmac_chan *chan,
286 struct axi_dmac_sg *sg)
289 return sg->x_len * sg->y_len;
294 static void axi_dmac_dequeue_partial_xfers(struct axi_dmac_chan *chan)
296 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
297 struct axi_dmac_desc *desc;
298 struct axi_dmac_sg *sg;
299 u32 xfer_done, len, id, i;
303 len = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_LEN);
304 id = axi_dmac_read(dmac, AXI_DMAC_REG_PARTIAL_XFER_ID);
307 list_for_each_entry(desc, &chan->active_descs, vdesc.node) {
308 for (i = 0; i < desc->num_sgs; i++) {
310 if (sg->id == AXI_DMAC_SG_UNUSED)
313 desc->have_partial_xfer = true;
314 sg->partial_len = len;
324 dev_dbg(dmac->dma_dev.dev,
325 "Found partial segment id=%u, len=%u\n",
328 dev_warn(dmac->dma_dev.dev,
329 "Not found partial segment id=%u, len=%u\n",
333 /* Check if we have any more partial transfers */
334 xfer_done = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
335 xfer_done = !(xfer_done & AXI_DMAC_FLAG_PARTIAL_XFER_DONE);
337 } while (!xfer_done);
340 static void axi_dmac_compute_residue(struct axi_dmac_chan *chan,
341 struct axi_dmac_desc *active)
343 struct dmaengine_result *rslt = &active->vdesc.tx_result;
344 unsigned int start = active->num_completed - 1;
345 struct axi_dmac_sg *sg;
346 unsigned int i, total;
348 rslt->result = DMA_TRANS_NOERROR;
352 * We get here if the last completed segment is partial, which
353 * means we can compute the residue from that segment onwards
355 for (i = start; i < active->num_sgs; i++) {
357 total = axi_dmac_total_sg_bytes(chan, sg);
358 rslt->residue += (total - sg->partial_len);
362 static bool axi_dmac_transfer_done(struct axi_dmac_chan *chan,
363 unsigned int completed_transfers)
365 struct axi_dmac_desc *active;
366 struct axi_dmac_sg *sg;
367 bool start_next = false;
369 active = axi_dmac_active_desc(chan);
373 if (chan->hw_partial_xfer &&
374 (completed_transfers & AXI_DMAC_FLAG_PARTIAL_XFER_DONE))
375 axi_dmac_dequeue_partial_xfers(chan);
378 sg = &active->sg[active->num_completed];
379 if (sg->id == AXI_DMAC_SG_UNUSED) /* Not yet submitted */
381 if (!(BIT(sg->id) & completed_transfers))
383 active->num_completed++;
384 sg->id = AXI_DMAC_SG_UNUSED;
385 if (sg->schedule_when_free) {
386 sg->schedule_when_free = false;
391 axi_dmac_compute_residue(chan, active);
394 vchan_cyclic_callback(&active->vdesc);
396 if (active->num_completed == active->num_sgs ||
398 if (active->cyclic) {
399 active->num_completed = 0; /* wrap around */
401 list_del(&active->vdesc.node);
402 vchan_cookie_complete(&active->vdesc);
403 active = axi_dmac_active_desc(chan);
411 static irqreturn_t axi_dmac_interrupt_handler(int irq, void *devid)
413 struct axi_dmac *dmac = devid;
414 unsigned int pending;
415 bool start_next = false;
417 pending = axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING);
421 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, pending);
423 spin_lock(&dmac->chan.vchan.lock);
424 /* One or more transfers have finished */
425 if (pending & AXI_DMAC_IRQ_EOT) {
426 unsigned int completed;
428 completed = axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE);
429 start_next = axi_dmac_transfer_done(&dmac->chan, completed);
431 /* Space has become available in the descriptor queue */
432 if ((pending & AXI_DMAC_IRQ_SOT) || start_next)
433 axi_dmac_start_transfer(&dmac->chan);
434 spin_unlock(&dmac->chan.vchan.lock);
439 static int axi_dmac_terminate_all(struct dma_chan *c)
441 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
442 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
446 spin_lock_irqsave(&chan->vchan.lock, flags);
447 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0);
448 chan->next_desc = NULL;
449 vchan_get_all_descriptors(&chan->vchan, &head);
450 list_splice_tail_init(&chan->active_descs, &head);
451 spin_unlock_irqrestore(&chan->vchan.lock, flags);
453 vchan_dma_desc_free_list(&chan->vchan, &head);
458 static void axi_dmac_synchronize(struct dma_chan *c)
460 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
462 vchan_synchronize(&chan->vchan);
465 static void axi_dmac_issue_pending(struct dma_chan *c)
467 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
468 struct axi_dmac *dmac = chan_to_axi_dmac(chan);
471 axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
473 spin_lock_irqsave(&chan->vchan.lock, flags);
474 if (vchan_issue_pending(&chan->vchan))
475 axi_dmac_start_transfer(chan);
476 spin_unlock_irqrestore(&chan->vchan.lock, flags);
479 static struct axi_dmac_desc *axi_dmac_alloc_desc(unsigned int num_sgs)
481 struct axi_dmac_desc *desc;
484 desc = kzalloc(struct_size(desc, sg, num_sgs), GFP_NOWAIT);
488 for (i = 0; i < num_sgs; i++)
489 desc->sg[i].id = AXI_DMAC_SG_UNUSED;
491 desc->num_sgs = num_sgs;
496 static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan,
497 enum dma_transfer_direction direction, dma_addr_t addr,
498 unsigned int num_periods, unsigned int period_len,
499 struct axi_dmac_sg *sg)
501 unsigned int num_segments, i;
502 unsigned int segment_size;
505 /* Split into multiple equally sized segments if necessary */
506 num_segments = DIV_ROUND_UP(period_len, chan->max_length);
507 segment_size = DIV_ROUND_UP(period_len, num_segments);
508 /* Take care of alignment */
509 segment_size = ((segment_size - 1) | chan->length_align_mask) + 1;
511 for (i = 0; i < num_periods; i++) {
514 while (len > segment_size) {
515 if (direction == DMA_DEV_TO_MEM)
516 sg->dest_addr = addr;
519 sg->x_len = segment_size;
522 addr += segment_size;
526 if (direction == DMA_DEV_TO_MEM)
527 sg->dest_addr = addr;
539 static struct dma_async_tx_descriptor *axi_dmac_prep_slave_sg(
540 struct dma_chan *c, struct scatterlist *sgl,
541 unsigned int sg_len, enum dma_transfer_direction direction,
542 unsigned long flags, void *context)
544 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
545 struct axi_dmac_desc *desc;
546 struct axi_dmac_sg *dsg;
547 struct scatterlist *sg;
548 unsigned int num_sgs;
551 if (direction != chan->direction)
555 for_each_sg(sgl, sg, sg_len, i)
556 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), chan->max_length);
558 desc = axi_dmac_alloc_desc(num_sgs);
564 for_each_sg(sgl, sg, sg_len, i) {
565 if (!axi_dmac_check_addr(chan, sg_dma_address(sg)) ||
566 !axi_dmac_check_len(chan, sg_dma_len(sg))) {
571 dsg = axi_dmac_fill_linear_sg(chan, direction, sg_dma_address(sg), 1,
572 sg_dma_len(sg), dsg);
575 desc->cyclic = false;
577 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
580 static struct dma_async_tx_descriptor *axi_dmac_prep_dma_cyclic(
581 struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
582 size_t period_len, enum dma_transfer_direction direction,
585 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
586 struct axi_dmac_desc *desc;
587 unsigned int num_periods, num_segments;
589 if (direction != chan->direction)
592 if (!axi_dmac_check_len(chan, buf_len) ||
593 !axi_dmac_check_addr(chan, buf_addr))
596 if (period_len == 0 || buf_len % period_len)
599 num_periods = buf_len / period_len;
600 num_segments = DIV_ROUND_UP(period_len, chan->max_length);
602 desc = axi_dmac_alloc_desc(num_periods * num_segments);
606 axi_dmac_fill_linear_sg(chan, direction, buf_addr, num_periods,
607 period_len, desc->sg);
611 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
614 static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
615 struct dma_chan *c, struct dma_interleaved_template *xt,
618 struct axi_dmac_chan *chan = to_axi_dmac_chan(c);
619 struct axi_dmac_desc *desc;
620 size_t dst_icg, src_icg;
622 if (xt->frame_size != 1)
625 if (xt->dir != chan->direction)
628 if (axi_dmac_src_is_mem(chan)) {
629 if (!xt->src_inc || !axi_dmac_check_addr(chan, xt->src_start))
633 if (axi_dmac_dest_is_mem(chan)) {
634 if (!xt->dst_inc || !axi_dmac_check_addr(chan, xt->dst_start))
638 dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]);
639 src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]);
642 if (!axi_dmac_check_len(chan, xt->sgl[0].size) ||
645 if (xt->sgl[0].size + dst_icg > chan->max_length ||
646 xt->sgl[0].size + src_icg > chan->max_length)
649 if (dst_icg != 0 || src_icg != 0)
651 if (chan->max_length / xt->sgl[0].size < xt->numf)
653 if (!axi_dmac_check_len(chan, xt->sgl[0].size * xt->numf))
657 desc = axi_dmac_alloc_desc(1);
661 if (axi_dmac_src_is_mem(chan)) {
662 desc->sg[0].src_addr = xt->src_start;
663 desc->sg[0].src_stride = xt->sgl[0].size + src_icg;
666 if (axi_dmac_dest_is_mem(chan)) {
667 desc->sg[0].dest_addr = xt->dst_start;
668 desc->sg[0].dest_stride = xt->sgl[0].size + dst_icg;
672 desc->sg[0].x_len = xt->sgl[0].size;
673 desc->sg[0].y_len = xt->numf;
675 desc->sg[0].x_len = xt->sgl[0].size * xt->numf;
676 desc->sg[0].y_len = 1;
679 if (flags & DMA_CYCLIC)
682 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
685 static void axi_dmac_free_chan_resources(struct dma_chan *c)
687 vchan_free_chan_resources(to_virt_chan(c));
690 static void axi_dmac_desc_free(struct virt_dma_desc *vdesc)
692 kfree(container_of(vdesc, struct axi_dmac_desc, vdesc));
695 static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg)
698 case AXI_DMAC_REG_IRQ_MASK:
699 case AXI_DMAC_REG_IRQ_SOURCE:
700 case AXI_DMAC_REG_IRQ_PENDING:
701 case AXI_DMAC_REG_CTRL:
702 case AXI_DMAC_REG_TRANSFER_ID:
703 case AXI_DMAC_REG_START_TRANSFER:
704 case AXI_DMAC_REG_FLAGS:
705 case AXI_DMAC_REG_DEST_ADDRESS:
706 case AXI_DMAC_REG_SRC_ADDRESS:
707 case AXI_DMAC_REG_X_LENGTH:
708 case AXI_DMAC_REG_Y_LENGTH:
709 case AXI_DMAC_REG_DEST_STRIDE:
710 case AXI_DMAC_REG_SRC_STRIDE:
711 case AXI_DMAC_REG_TRANSFER_DONE:
712 case AXI_DMAC_REG_ACTIVE_TRANSFER_ID:
713 case AXI_DMAC_REG_STATUS:
714 case AXI_DMAC_REG_CURRENT_SRC_ADDR:
715 case AXI_DMAC_REG_CURRENT_DEST_ADDR:
716 case AXI_DMAC_REG_PARTIAL_XFER_LEN:
717 case AXI_DMAC_REG_PARTIAL_XFER_ID:
724 static const struct regmap_config axi_dmac_regmap_config = {
728 .max_register = AXI_DMAC_REG_PARTIAL_XFER_ID,
729 .readable_reg = axi_dmac_regmap_rdwr,
730 .writeable_reg = axi_dmac_regmap_rdwr,
733 static void axi_dmac_adjust_chan_params(struct axi_dmac_chan *chan)
735 chan->address_align_mask = max(chan->dest_width, chan->src_width) - 1;
737 if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
738 chan->direction = DMA_MEM_TO_MEM;
739 else if (!axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
740 chan->direction = DMA_MEM_TO_DEV;
741 else if (axi_dmac_dest_is_mem(chan) && !axi_dmac_src_is_mem(chan))
742 chan->direction = DMA_DEV_TO_MEM;
744 chan->direction = DMA_DEV_TO_DEV;
748 * The configuration stored in the devicetree matches the configuration
749 * parameters of the peripheral instance and allows the driver to know which
750 * features are implemented and how it should behave.
752 static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
753 struct axi_dmac_chan *chan)
758 ret = of_property_read_u32(of_chan, "reg", &val);
762 /* We only support 1 channel for now */
766 ret = of_property_read_u32(of_chan, "adi,source-bus-type", &val);
769 if (val > AXI_DMAC_BUS_TYPE_FIFO)
771 chan->src_type = val;
773 ret = of_property_read_u32(of_chan, "adi,destination-bus-type", &val);
776 if (val > AXI_DMAC_BUS_TYPE_FIFO)
778 chan->dest_type = val;
780 ret = of_property_read_u32(of_chan, "adi,source-bus-width", &val);
783 chan->src_width = val / 8;
785 ret = of_property_read_u32(of_chan, "adi,destination-bus-width", &val);
788 chan->dest_width = val / 8;
790 axi_dmac_adjust_chan_params(chan);
795 static int axi_dmac_parse_dt(struct device *dev, struct axi_dmac *dmac)
797 struct device_node *of_channels, *of_chan;
800 of_channels = of_get_child_by_name(dev->of_node, "adi,channels");
801 if (of_channels == NULL)
804 for_each_child_of_node(of_channels, of_chan) {
805 ret = axi_dmac_parse_chan_dt(of_chan, &dmac->chan);
807 of_node_put(of_chan);
808 of_node_put(of_channels);
812 of_node_put(of_channels);
817 static int axi_dmac_read_chan_config(struct device *dev, struct axi_dmac *dmac)
819 struct axi_dmac_chan *chan = &dmac->chan;
820 unsigned int val, desc;
822 desc = axi_dmac_read(dmac, AXI_DMAC_REG_INTERFACE_DESC);
824 dev_err(dev, "DMA interface register reads zero\n");
828 val = AXI_DMAC_DMA_SRC_TYPE_GET(desc);
829 if (val > AXI_DMAC_BUS_TYPE_FIFO) {
830 dev_err(dev, "Invalid source bus type read: %d\n", val);
833 chan->src_type = val;
835 val = AXI_DMAC_DMA_DST_TYPE_GET(desc);
836 if (val > AXI_DMAC_BUS_TYPE_FIFO) {
837 dev_err(dev, "Invalid destination bus type read: %d\n", val);
840 chan->dest_type = val;
842 val = AXI_DMAC_DMA_SRC_WIDTH_GET(desc);
844 dev_err(dev, "Source bus width is zero\n");
847 /* widths are stored in log2 */
848 chan->src_width = 1 << val;
850 val = AXI_DMAC_DMA_DST_WIDTH_GET(desc);
852 dev_err(dev, "Destination bus width is zero\n");
855 chan->dest_width = 1 << val;
857 axi_dmac_adjust_chan_params(chan);
862 static int axi_dmac_detect_caps(struct axi_dmac *dmac, unsigned int version)
864 struct axi_dmac_chan *chan = &dmac->chan;
866 axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, AXI_DMAC_FLAG_CYCLIC);
867 if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)
868 chan->hw_cyclic = true;
870 axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 1);
871 if (axi_dmac_read(dmac, AXI_DMAC_REG_Y_LENGTH) == 1)
874 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0xffffffff);
875 chan->max_length = axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
876 if (chan->max_length != UINT_MAX)
879 axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, 0xffffffff);
880 if (axi_dmac_read(dmac, AXI_DMAC_REG_DEST_ADDRESS) == 0 &&
881 chan->dest_type == AXI_DMAC_BUS_TYPE_AXI_MM) {
882 dev_err(dmac->dma_dev.dev,
883 "Destination memory-mapped interface not supported.");
887 axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, 0xffffffff);
888 if (axi_dmac_read(dmac, AXI_DMAC_REG_SRC_ADDRESS) == 0 &&
889 chan->src_type == AXI_DMAC_BUS_TYPE_AXI_MM) {
890 dev_err(dmac->dma_dev.dev,
891 "Source memory-mapped interface not supported.");
895 if (version >= ADI_AXI_PCORE_VER(4, 2, 'a'))
896 chan->hw_partial_xfer = true;
898 if (version >= ADI_AXI_PCORE_VER(4, 1, 'a')) {
899 axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0x00);
900 chan->length_align_mask =
901 axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
903 chan->length_align_mask = chan->address_align_mask;
909 static int axi_dmac_probe(struct platform_device *pdev)
911 struct dma_device *dma_dev;
912 struct axi_dmac *dmac;
913 struct regmap *regmap;
914 unsigned int version;
917 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
921 dmac->irq = platform_get_irq(pdev, 0);
927 dmac->base = devm_platform_ioremap_resource(pdev, 0);
928 if (IS_ERR(dmac->base))
929 return PTR_ERR(dmac->base);
931 dmac->clk = devm_clk_get(&pdev->dev, NULL);
932 if (IS_ERR(dmac->clk))
933 return PTR_ERR(dmac->clk);
935 ret = clk_prepare_enable(dmac->clk);
939 version = axi_dmac_read(dmac, ADI_AXI_REG_VERSION);
941 if (version >= ADI_AXI_PCORE_VER(4, 3, 'a'))
942 ret = axi_dmac_read_chan_config(&pdev->dev, dmac);
944 ret = axi_dmac_parse_dt(&pdev->dev, dmac);
947 goto err_clk_disable;
949 INIT_LIST_HEAD(&dmac->chan.active_descs);
951 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
953 dma_dev = &dmac->dma_dev;
954 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
955 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
956 dma_cap_set(DMA_INTERLEAVE, dma_dev->cap_mask);
957 dma_dev->device_free_chan_resources = axi_dmac_free_chan_resources;
958 dma_dev->device_tx_status = dma_cookie_status;
959 dma_dev->device_issue_pending = axi_dmac_issue_pending;
960 dma_dev->device_prep_slave_sg = axi_dmac_prep_slave_sg;
961 dma_dev->device_prep_dma_cyclic = axi_dmac_prep_dma_cyclic;
962 dma_dev->device_prep_interleaved_dma = axi_dmac_prep_interleaved;
963 dma_dev->device_terminate_all = axi_dmac_terminate_all;
964 dma_dev->device_synchronize = axi_dmac_synchronize;
965 dma_dev->dev = &pdev->dev;
966 dma_dev->src_addr_widths = BIT(dmac->chan.src_width);
967 dma_dev->dst_addr_widths = BIT(dmac->chan.dest_width);
968 dma_dev->directions = BIT(dmac->chan.direction);
969 dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
970 INIT_LIST_HEAD(&dma_dev->channels);
972 dmac->chan.vchan.desc_free = axi_dmac_desc_free;
973 vchan_init(&dmac->chan.vchan, dma_dev);
975 ret = axi_dmac_detect_caps(dmac, version);
977 goto err_clk_disable;
979 dma_dev->copy_align = (dmac->chan.address_align_mask + 1);
981 axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
983 if (of_dma_is_coherent(pdev->dev.of_node)) {
984 ret = axi_dmac_read(dmac, AXI_DMAC_REG_COHERENCY_DESC);
986 if (version < ADI_AXI_PCORE_VER(4, 4, 'a') ||
987 !AXI_DMAC_DST_COHERENT_GET(ret)) {
988 dev_err(dmac->dma_dev.dev,
989 "Coherent DMA not supported in hardware");
991 goto err_clk_disable;
995 ret = dma_async_device_register(dma_dev);
997 goto err_clk_disable;
999 ret = of_dma_controller_register(pdev->dev.of_node,
1000 of_dma_xlate_by_chan_id, dma_dev);
1002 goto err_unregister_device;
1004 ret = request_irq(dmac->irq, axi_dmac_interrupt_handler, IRQF_SHARED,
1005 dev_name(&pdev->dev), dmac);
1007 goto err_unregister_of;
1009 platform_set_drvdata(pdev, dmac);
1011 regmap = devm_regmap_init_mmio(&pdev->dev, dmac->base,
1012 &axi_dmac_regmap_config);
1013 if (IS_ERR(regmap)) {
1014 ret = PTR_ERR(regmap);
1021 free_irq(dmac->irq, dmac);
1023 of_dma_controller_free(pdev->dev.of_node);
1024 err_unregister_device:
1025 dma_async_device_unregister(&dmac->dma_dev);
1027 clk_disable_unprepare(dmac->clk);
1032 static int axi_dmac_remove(struct platform_device *pdev)
1034 struct axi_dmac *dmac = platform_get_drvdata(pdev);
1036 of_dma_controller_free(pdev->dev.of_node);
1037 free_irq(dmac->irq, dmac);
1038 tasklet_kill(&dmac->chan.vchan.task);
1039 dma_async_device_unregister(&dmac->dma_dev);
1040 clk_disable_unprepare(dmac->clk);
1045 static const struct of_device_id axi_dmac_of_match_table[] = {
1046 { .compatible = "adi,axi-dmac-1.00.a" },
1049 MODULE_DEVICE_TABLE(of, axi_dmac_of_match_table);
1051 static struct platform_driver axi_dmac_driver = {
1053 .name = "dma-axi-dmac",
1054 .of_match_table = axi_dmac_of_match_table,
1056 .probe = axi_dmac_probe,
1057 .remove = axi_dmac_remove,
1059 module_platform_driver(axi_dmac_driver);
1061 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1062 MODULE_DESCRIPTION("DMA controller driver for the AXI-DMAC controller");
1063 MODULE_LICENSE("GPL v2");