1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Audio DMA Controller (ADMAC) on t8103 (M1) and other Apple chips
5 * Copyright (C) The Asahi Linux Contributors
8 #include <linux/bits.h>
9 #include <linux/bitfield.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_dma.h>
15 #include <linux/reset.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
19 #include "dmaengine.h"
21 #define NCHANNELS_MAX 64
22 #define IRQ_NOUTPUTS 4
25 * For allocation purposes we split the cache
26 * memory into blocks of fixed size (given in bytes).
28 #define SRAM_BLOCK 2048
30 #define RING_WRITE_SLOT GENMASK(1, 0)
31 #define RING_READ_SLOT GENMASK(5, 4)
32 #define RING_FULL BIT(9)
33 #define RING_EMPTY BIT(8)
34 #define RING_ERR BIT(10)
36 #define STATUS_DESC_DONE BIT(0)
37 #define STATUS_ERR BIT(6)
39 #define FLAG_DESC_NOTIFY BIT(16)
41 #define REG_TX_START 0x0000
42 #define REG_TX_STOP 0x0004
43 #define REG_RX_START 0x0008
44 #define REG_RX_STOP 0x000c
45 #define REG_IMPRINT 0x0090
46 #define REG_TX_SRAM_SIZE 0x0094
47 #define REG_RX_SRAM_SIZE 0x0098
49 #define REG_CHAN_CTL(ch) (0x8000 + (ch) * 0x200)
50 #define REG_CHAN_CTL_RST_RINGS BIT(0)
52 #define REG_DESC_RING(ch) (0x8070 + (ch) * 0x200)
53 #define REG_REPORT_RING(ch) (0x8074 + (ch) * 0x200)
55 #define REG_RESIDUE(ch) (0x8064 + (ch) * 0x200)
57 #define REG_BUS_WIDTH(ch) (0x8040 + (ch) * 0x200)
59 #define BUS_WIDTH_8BIT 0x00
60 #define BUS_WIDTH_16BIT 0x01
61 #define BUS_WIDTH_32BIT 0x02
62 #define BUS_WIDTH_FRAME_2_WORDS 0x10
63 #define BUS_WIDTH_FRAME_4_WORDS 0x20
65 #define REG_CHAN_SRAM_CARVEOUT(ch) (0x8050 + (ch) * 0x200)
66 #define CHAN_SRAM_CARVEOUT_SIZE GENMASK(31, 16)
67 #define CHAN_SRAM_CARVEOUT_BASE GENMASK(15, 0)
69 #define REG_CHAN_FIFOCTL(ch) (0x8054 + (ch) * 0x200)
70 #define CHAN_FIFOCTL_LIMIT GENMASK(31, 16)
71 #define CHAN_FIFOCTL_THRESHOLD GENMASK(15, 0)
73 #define REG_DESC_WRITE(ch) (0x10000 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
74 #define REG_REPORT_READ(ch) (0x10100 + ((ch) / 2) * 0x4 + ((ch) & 1) * 0x4000)
76 #define REG_TX_INTSTATE(idx) (0x0030 + (idx) * 4)
77 #define REG_RX_INTSTATE(idx) (0x0040 + (idx) * 4)
78 #define REG_GLOBAL_INTSTATE(idx) (0x0050 + (idx) * 4)
79 #define REG_CHAN_INTSTATUS(ch, idx) (0x8010 + (ch) * 0x200 + (idx) * 4)
80 #define REG_CHAN_INTMASK(ch, idx) (0x8020 + (ch) * 0x200 + (idx) * 4)
87 struct admac_data *host;
89 struct tasklet_struct tasklet;
94 struct admac_tx *current_tx;
98 * We maintain a 'submitted' and 'issued' list mainly for interface
99 * correctness. Typical use of the driver (per channel) will be
100 * prepping, submitting and issuing a single cyclic transaction which
101 * will stay current until terminate_all is called.
103 struct list_head submitted;
104 struct list_head issued;
106 struct list_head to_free;
112 * SRAM_CARVEOUT has 16-bit fields, so the SRAM cannot be larger than
113 * 64K and a 32-bit bitfield over 2K blocks covers it.
119 struct dma_device dma;
122 struct reset_control *rstc;
124 struct mutex cache_alloc_lock;
125 struct admac_sram txcache, rxcache;
130 struct admac_chan channels[];
134 struct dma_async_tx_descriptor tx;
141 size_t submitted_pos;
142 size_t reclaimed_pos;
144 struct list_head node;
147 static int admac_alloc_sram_carveout(struct admac_data *ad,
148 enum dma_transfer_direction dir,
151 struct admac_sram *sram;
152 int i, ret = 0, nblocks;
154 if (dir == DMA_MEM_TO_DEV)
159 mutex_lock(&ad->cache_alloc_lock);
161 nblocks = sram->size / SRAM_BLOCK;
162 for (i = 0; i < nblocks; i++)
163 if (!(sram->allocated & BIT(i)))
167 *out = FIELD_PREP(CHAN_SRAM_CARVEOUT_BASE, i * SRAM_BLOCK) |
168 FIELD_PREP(CHAN_SRAM_CARVEOUT_SIZE, SRAM_BLOCK);
169 sram->allocated |= BIT(i);
174 mutex_unlock(&ad->cache_alloc_lock);
179 static void admac_free_sram_carveout(struct admac_data *ad,
180 enum dma_transfer_direction dir,
183 struct admac_sram *sram;
184 u32 base = FIELD_GET(CHAN_SRAM_CARVEOUT_BASE, carveout);
187 if (dir == DMA_MEM_TO_DEV)
192 if (WARN_ON(base >= sram->size))
195 mutex_lock(&ad->cache_alloc_lock);
196 i = base / SRAM_BLOCK;
197 sram->allocated &= ~BIT(i);
198 mutex_unlock(&ad->cache_alloc_lock);
201 static void admac_modify(struct admac_data *ad, int reg, u32 mask, u32 val)
203 void __iomem *addr = ad->base + reg;
204 u32 curr = readl_relaxed(addr);
206 writel_relaxed((curr & ~mask) | (val & mask), addr);
209 static struct admac_chan *to_admac_chan(struct dma_chan *chan)
211 return container_of(chan, struct admac_chan, chan);
214 static struct admac_tx *to_admac_tx(struct dma_async_tx_descriptor *tx)
216 return container_of(tx, struct admac_tx, tx);
219 static enum dma_transfer_direction admac_chan_direction(int channo)
221 /* Channel directions are hardwired */
222 return (channo & 1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
225 static dma_cookie_t admac_tx_submit(struct dma_async_tx_descriptor *tx)
227 struct admac_tx *adtx = to_admac_tx(tx);
228 struct admac_chan *adchan = to_admac_chan(tx->chan);
232 spin_lock_irqsave(&adchan->lock, flags);
233 cookie = dma_cookie_assign(tx);
234 list_add_tail(&adtx->node, &adchan->submitted);
235 spin_unlock_irqrestore(&adchan->lock, flags);
240 static int admac_desc_free(struct dma_async_tx_descriptor *tx)
242 kfree(to_admac_tx(tx));
247 static struct dma_async_tx_descriptor *admac_prep_dma_cyclic(
248 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
249 size_t period_len, enum dma_transfer_direction direction,
252 struct admac_chan *adchan = container_of(chan, struct admac_chan, chan);
253 struct admac_tx *adtx;
255 if (direction != admac_chan_direction(adchan->no))
258 adtx = kzalloc(sizeof(*adtx), GFP_NOWAIT);
264 adtx->buf_addr = buf_addr;
265 adtx->buf_len = buf_len;
266 adtx->buf_end = buf_addr + buf_len;
267 adtx->period_len = period_len;
269 adtx->submitted_pos = 0;
270 adtx->reclaimed_pos = 0;
272 dma_async_tx_descriptor_init(&adtx->tx, chan);
273 adtx->tx.tx_submit = admac_tx_submit;
274 adtx->tx.desc_free = admac_desc_free;
280 * Write one hardware descriptor for a dmaengine cyclic transaction.
282 static void admac_cyclic_write_one_desc(struct admac_data *ad, int channo,
287 addr = tx->buf_addr + (tx->submitted_pos % tx->buf_len);
289 /* If happens means we have buggy code */
290 WARN_ON_ONCE(addr + tx->period_len > tx->buf_end);
292 dev_dbg(ad->dev, "ch%d descriptor: addr=0x%pad len=0x%zx flags=0x%lx\n",
293 channo, &addr, tx->period_len, FLAG_DESC_NOTIFY);
295 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
296 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
297 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
298 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
300 tx->submitted_pos += tx->period_len;
301 tx->submitted_pos %= 2 * tx->buf_len;
305 * Write all the hardware descriptors for a dmaengine cyclic
306 * transaction there is space for.
308 static void admac_cyclic_write_desc(struct admac_data *ad, int channo,
313 for (i = 0; i < 4; i++) {
314 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_FULL)
316 admac_cyclic_write_one_desc(ad, channo, tx);
320 static int admac_ring_noccupied_slots(int ringval)
322 int wrslot = FIELD_GET(RING_WRITE_SLOT, ringval);
323 int rdslot = FIELD_GET(RING_READ_SLOT, ringval);
325 if (wrslot != rdslot) {
326 return (wrslot + 4 - rdslot) % 4;
328 WARN_ON((ringval & (RING_FULL | RING_EMPTY)) == 0);
330 if (ringval & RING_FULL)
338 * Read from hardware the residue of a cyclic dmaengine transaction.
340 static u32 admac_cyclic_read_residue(struct admac_data *ad, int channo,
341 struct admac_tx *adtx)
344 u32 residue1, residue2;
348 ring1 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
349 residue1 = readl_relaxed(ad->base + REG_RESIDUE(channo));
350 ring2 = readl_relaxed(ad->base + REG_REPORT_RING(channo));
351 residue2 = readl_relaxed(ad->base + REG_RESIDUE(channo));
353 if (residue2 > residue1) {
355 * Controller must have loaded next descriptor between
356 * the two residue reads
358 nreports = admac_ring_noccupied_slots(ring1) + 1;
360 /* No descriptor load between the two reads, ring2 is safe to use */
361 nreports = admac_ring_noccupied_slots(ring2);
364 pos = adtx->reclaimed_pos + adtx->period_len * (nreports + 1) - residue2;
366 return adtx->buf_len - pos % adtx->buf_len;
369 static enum dma_status admac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
370 struct dma_tx_state *txstate)
372 struct admac_chan *adchan = to_admac_chan(chan);
373 struct admac_data *ad = adchan->host;
374 struct admac_tx *adtx;
380 ret = dma_cookie_status(chan, cookie, txstate);
381 if (ret == DMA_COMPLETE || !txstate)
384 spin_lock_irqsave(&adchan->lock, flags);
385 adtx = adchan->current_tx;
387 if (adtx && adtx->tx.cookie == cookie) {
388 ret = DMA_IN_PROGRESS;
389 residue = admac_cyclic_read_residue(ad, adchan->no, adtx);
391 ret = DMA_IN_PROGRESS;
393 list_for_each_entry(adtx, &adchan->issued, node) {
394 if (adtx->tx.cookie == cookie) {
395 residue = adtx->buf_len;
400 spin_unlock_irqrestore(&adchan->lock, flags);
402 dma_set_residue(txstate, residue);
406 static void admac_start_chan(struct admac_chan *adchan)
408 struct admac_data *ad = adchan->host;
409 u32 startbit = 1 << (adchan->no / 2);
411 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
412 ad->base + REG_CHAN_INTSTATUS(adchan->no, ad->irq_index));
413 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
414 ad->base + REG_CHAN_INTMASK(adchan->no, ad->irq_index));
416 switch (admac_chan_direction(adchan->no)) {
418 writel_relaxed(startbit, ad->base + REG_TX_START);
421 writel_relaxed(startbit, ad->base + REG_RX_START);
426 dev_dbg(adchan->host->dev, "ch%d start\n", adchan->no);
429 static void admac_stop_chan(struct admac_chan *adchan)
431 struct admac_data *ad = adchan->host;
432 u32 stopbit = 1 << (adchan->no / 2);
434 switch (admac_chan_direction(adchan->no)) {
436 writel_relaxed(stopbit, ad->base + REG_TX_STOP);
439 writel_relaxed(stopbit, ad->base + REG_RX_STOP);
444 dev_dbg(adchan->host->dev, "ch%d stop\n", adchan->no);
447 static void admac_reset_rings(struct admac_chan *adchan)
449 struct admac_data *ad = adchan->host;
451 writel_relaxed(REG_CHAN_CTL_RST_RINGS,
452 ad->base + REG_CHAN_CTL(adchan->no));
453 writel_relaxed(0, ad->base + REG_CHAN_CTL(adchan->no));
456 static void admac_start_current_tx(struct admac_chan *adchan)
458 struct admac_data *ad = adchan->host;
461 admac_reset_rings(adchan);
462 writel_relaxed(0, ad->base + REG_CHAN_CTL(ch));
464 admac_cyclic_write_one_desc(ad, ch, adchan->current_tx);
465 admac_start_chan(adchan);
466 admac_cyclic_write_desc(ad, ch, adchan->current_tx);
469 static void admac_issue_pending(struct dma_chan *chan)
471 struct admac_chan *adchan = to_admac_chan(chan);
475 spin_lock_irqsave(&adchan->lock, flags);
476 list_splice_tail_init(&adchan->submitted, &adchan->issued);
477 if (!list_empty(&adchan->issued) && !adchan->current_tx) {
478 tx = list_first_entry(&adchan->issued, struct admac_tx, node);
481 adchan->current_tx = tx;
482 adchan->nperiod_acks = 0;
483 admac_start_current_tx(adchan);
485 spin_unlock_irqrestore(&adchan->lock, flags);
488 static int admac_pause(struct dma_chan *chan)
490 struct admac_chan *adchan = to_admac_chan(chan);
492 admac_stop_chan(adchan);
497 static int admac_resume(struct dma_chan *chan)
499 struct admac_chan *adchan = to_admac_chan(chan);
501 admac_start_chan(adchan);
506 static int admac_terminate_all(struct dma_chan *chan)
508 struct admac_chan *adchan = to_admac_chan(chan);
511 spin_lock_irqsave(&adchan->lock, flags);
512 admac_stop_chan(adchan);
513 admac_reset_rings(adchan);
515 if (adchan->current_tx) {
516 list_add_tail(&adchan->current_tx->node, &adchan->to_free);
517 adchan->current_tx = NULL;
520 * Descriptors can only be freed after the tasklet
521 * has been killed (in admac_synchronize).
523 list_splice_tail_init(&adchan->submitted, &adchan->to_free);
524 list_splice_tail_init(&adchan->issued, &adchan->to_free);
525 spin_unlock_irqrestore(&adchan->lock, flags);
530 static void admac_synchronize(struct dma_chan *chan)
532 struct admac_chan *adchan = to_admac_chan(chan);
533 struct admac_tx *adtx, *_adtx;
537 spin_lock_irqsave(&adchan->lock, flags);
538 list_splice_tail_init(&adchan->to_free, &head);
539 spin_unlock_irqrestore(&adchan->lock, flags);
541 tasklet_kill(&adchan->tasklet);
543 list_for_each_entry_safe(adtx, _adtx, &head, node) {
544 list_del(&adtx->node);
545 admac_desc_free(&adtx->tx);
549 static int admac_alloc_chan_resources(struct dma_chan *chan)
551 struct admac_chan *adchan = to_admac_chan(chan);
552 struct admac_data *ad = adchan->host;
555 dma_cookie_init(&adchan->chan);
556 ret = admac_alloc_sram_carveout(ad, admac_chan_direction(adchan->no),
561 writel_relaxed(adchan->carveout,
562 ad->base + REG_CHAN_SRAM_CARVEOUT(adchan->no));
566 static void admac_free_chan_resources(struct dma_chan *chan)
568 struct admac_chan *adchan = to_admac_chan(chan);
570 admac_terminate_all(chan);
571 admac_synchronize(chan);
572 admac_free_sram_carveout(adchan->host, admac_chan_direction(adchan->no),
576 static struct dma_chan *admac_dma_of_xlate(struct of_phandle_args *dma_spec,
577 struct of_dma *ofdma)
579 struct admac_data *ad = (struct admac_data *) ofdma->of_dma_data;
582 if (dma_spec->args_count != 1)
585 index = dma_spec->args[0];
587 if (index >= ad->nchannels) {
588 dev_err(ad->dev, "channel index %u out of bounds\n", index);
592 return dma_get_slave_channel(&ad->channels[index].chan);
595 static int admac_drain_reports(struct admac_data *ad, int channo)
599 for (count = 0; count < 4; count++) {
600 u32 countval_hi, countval_lo, unk1, flags;
602 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_EMPTY)
605 countval_lo = readl_relaxed(ad->base + REG_REPORT_READ(channo));
606 countval_hi = readl_relaxed(ad->base + REG_REPORT_READ(channo));
607 unk1 = readl_relaxed(ad->base + REG_REPORT_READ(channo));
608 flags = readl_relaxed(ad->base + REG_REPORT_READ(channo));
610 dev_dbg(ad->dev, "ch%d report: countval=0x%llx unk1=0x%x flags=0x%x\n",
611 channo, ((u64) countval_hi) << 32 | countval_lo, unk1, flags);
617 static void admac_handle_status_err(struct admac_data *ad, int channo)
619 bool handled = false;
621 if (readl_relaxed(ad->base + REG_DESC_RING(channo)) & RING_ERR) {
622 writel_relaxed(RING_ERR, ad->base + REG_DESC_RING(channo));
623 dev_err_ratelimited(ad->dev, "ch%d descriptor ring error\n", channo);
627 if (readl_relaxed(ad->base + REG_REPORT_RING(channo)) & RING_ERR) {
628 writel_relaxed(RING_ERR, ad->base + REG_REPORT_RING(channo));
629 dev_err_ratelimited(ad->dev, "ch%d report ring error\n", channo);
633 if (unlikely(!handled)) {
634 dev_err(ad->dev, "ch%d unknown error, masking errors as cause of IRQs\n", channo);
635 admac_modify(ad, REG_CHAN_INTMASK(channo, ad->irq_index),
640 static void admac_handle_status_desc_done(struct admac_data *ad, int channo)
642 struct admac_chan *adchan = &ad->channels[channo];
646 writel_relaxed(STATUS_DESC_DONE,
647 ad->base + REG_CHAN_INTSTATUS(channo, ad->irq_index));
649 spin_lock_irqsave(&adchan->lock, flags);
650 nreports = admac_drain_reports(ad, channo);
652 if (adchan->current_tx) {
653 struct admac_tx *tx = adchan->current_tx;
655 adchan->nperiod_acks += nreports;
656 tx->reclaimed_pos += nreports * tx->period_len;
657 tx->reclaimed_pos %= 2 * tx->buf_len;
659 admac_cyclic_write_desc(ad, channo, tx);
660 tasklet_schedule(&adchan->tasklet);
662 spin_unlock_irqrestore(&adchan->lock, flags);
665 static void admac_handle_chan_int(struct admac_data *ad, int no)
667 u32 cause = readl_relaxed(ad->base + REG_CHAN_INTSTATUS(no, ad->irq_index));
669 if (cause & STATUS_ERR)
670 admac_handle_status_err(ad, no);
672 if (cause & STATUS_DESC_DONE)
673 admac_handle_status_desc_done(ad, no);
676 static irqreturn_t admac_interrupt(int irq, void *devid)
678 struct admac_data *ad = devid;
679 u32 rx_intstate, tx_intstate, global_intstate;
682 rx_intstate = readl_relaxed(ad->base + REG_RX_INTSTATE(ad->irq_index));
683 tx_intstate = readl_relaxed(ad->base + REG_TX_INTSTATE(ad->irq_index));
684 global_intstate = readl_relaxed(ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
686 if (!tx_intstate && !rx_intstate && !global_intstate)
689 for (i = 0; i < ad->nchannels; i += 2) {
691 admac_handle_chan_int(ad, i);
695 for (i = 1; i < ad->nchannels; i += 2) {
697 admac_handle_chan_int(ad, i);
701 if (global_intstate) {
702 dev_warn(ad->dev, "clearing unknown global interrupt flag: %x\n",
704 writel_relaxed(~(u32) 0, ad->base + REG_GLOBAL_INTSTATE(ad->irq_index));
710 static void admac_chan_tasklet(struct tasklet_struct *t)
712 struct admac_chan *adchan = from_tasklet(adchan, t, tasklet);
713 struct admac_tx *adtx;
714 struct dmaengine_desc_callback cb;
715 struct dmaengine_result tx_result;
718 spin_lock_irq(&adchan->lock);
719 adtx = adchan->current_tx;
720 nacks = adchan->nperiod_acks;
721 adchan->nperiod_acks = 0;
722 spin_unlock_irq(&adchan->lock);
727 tx_result.result = DMA_TRANS_NOERROR;
728 tx_result.residue = 0;
730 dmaengine_desc_get_callback(&adtx->tx, &cb);
732 dmaengine_desc_callback_invoke(&cb, &tx_result);
735 static int admac_device_config(struct dma_chan *chan,
736 struct dma_slave_config *config)
738 struct admac_chan *adchan = to_admac_chan(chan);
739 struct admac_data *ad = adchan->host;
740 bool is_tx = admac_chan_direction(adchan->no) == DMA_MEM_TO_DEV;
744 switch (is_tx ? config->dst_addr_width : config->src_addr_width) {
745 case DMA_SLAVE_BUSWIDTH_1_BYTE:
747 bus_width |= BUS_WIDTH_8BIT;
749 case DMA_SLAVE_BUSWIDTH_2_BYTES:
751 bus_width |= BUS_WIDTH_16BIT;
753 case DMA_SLAVE_BUSWIDTH_4_BYTES:
755 bus_width |= BUS_WIDTH_32BIT;
762 * We take port_window_size to be the number of words in a frame.
764 * The controller has some means of out-of-band signalling, to the peripheral,
765 * of words position in a frame. That's where the importance of this control
768 switch (is_tx ? config->dst_port_window_size : config->src_port_window_size) {
772 bus_width |= BUS_WIDTH_FRAME_2_WORDS;
775 bus_width |= BUS_WIDTH_FRAME_4_WORDS;
781 writel_relaxed(bus_width, ad->base + REG_BUS_WIDTH(adchan->no));
784 * By FIFOCTL_LIMIT we seem to set the maximal number of bytes allowed to be
785 * held in controller's per-channel FIFO. Transfers seem to be triggered
786 * around the time FIFO occupancy touches FIFOCTL_THRESHOLD.
788 * The numbers we set are more or less arbitrary.
790 writel_relaxed(FIELD_PREP(CHAN_FIFOCTL_LIMIT, 0x30 * wordsize)
791 | FIELD_PREP(CHAN_FIFOCTL_THRESHOLD, 0x18 * wordsize),
792 ad->base + REG_CHAN_FIFOCTL(adchan->no));
797 static int admac_probe(struct platform_device *pdev)
799 struct device_node *np = pdev->dev.of_node;
800 struct admac_data *ad;
801 struct dma_device *dma;
805 err = of_property_read_u32(np, "dma-channels", &nchannels);
806 if (err || nchannels > NCHANNELS_MAX) {
807 dev_err(&pdev->dev, "missing or invalid dma-channels property\n");
811 ad = devm_kzalloc(&pdev->dev, struct_size(ad, channels, nchannels), GFP_KERNEL);
815 platform_set_drvdata(pdev, ad);
816 ad->dev = &pdev->dev;
817 ad->nchannels = nchannels;
818 mutex_init(&ad->cache_alloc_lock);
821 * The controller has 4 IRQ outputs. Try them all until
822 * we find one we can use.
824 for (i = 0; i < IRQ_NOUTPUTS; i++) {
825 irq = platform_get_irq_optional(pdev, i);
833 return dev_err_probe(&pdev->dev, irq, "no usable interrupt\n");
836 ad->base = devm_platform_ioremap_resource(pdev, 0);
837 if (IS_ERR(ad->base))
838 return dev_err_probe(&pdev->dev, PTR_ERR(ad->base),
839 "unable to obtain MMIO resource\n");
841 ad->rstc = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
842 if (IS_ERR(ad->rstc))
843 return PTR_ERR(ad->rstc);
847 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
848 dma_cap_set(DMA_CYCLIC, dma->cap_mask);
850 dma->dev = &pdev->dev;
851 dma->device_alloc_chan_resources = admac_alloc_chan_resources;
852 dma->device_free_chan_resources = admac_free_chan_resources;
853 dma->device_tx_status = admac_tx_status;
854 dma->device_issue_pending = admac_issue_pending;
855 dma->device_terminate_all = admac_terminate_all;
856 dma->device_synchronize = admac_synchronize;
857 dma->device_prep_dma_cyclic = admac_prep_dma_cyclic;
858 dma->device_config = admac_device_config;
859 dma->device_pause = admac_pause;
860 dma->device_resume = admac_resume;
862 dma->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
863 dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
864 dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
865 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
866 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
867 dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
868 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
869 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
871 INIT_LIST_HEAD(&dma->channels);
872 for (i = 0; i < nchannels; i++) {
873 struct admac_chan *adchan = &ad->channels[i];
877 adchan->chan.device = &ad->dma;
878 spin_lock_init(&adchan->lock);
879 INIT_LIST_HEAD(&adchan->submitted);
880 INIT_LIST_HEAD(&adchan->issued);
881 INIT_LIST_HEAD(&adchan->to_free);
882 list_add_tail(&adchan->chan.device_node, &dma->channels);
883 tasklet_setup(&adchan->tasklet, admac_chan_tasklet);
886 err = reset_control_reset(ad->rstc);
888 return dev_err_probe(&pdev->dev, err,
889 "unable to trigger reset\n");
891 err = request_irq(irq, admac_interrupt, 0, dev_name(&pdev->dev), ad);
893 dev_err_probe(&pdev->dev, err,
894 "unable to register interrupt\n");
898 err = dma_async_device_register(&ad->dma);
900 dev_err_probe(&pdev->dev, err, "failed to register DMA device\n");
904 err = of_dma_controller_register(pdev->dev.of_node, admac_dma_of_xlate, ad);
906 dma_async_device_unregister(&ad->dma);
907 dev_err_probe(&pdev->dev, err, "failed to register with OF\n");
911 ad->txcache.size = readl_relaxed(ad->base + REG_TX_SRAM_SIZE);
912 ad->rxcache.size = readl_relaxed(ad->base + REG_RX_SRAM_SIZE);
914 dev_info(&pdev->dev, "Audio DMA Controller\n");
915 dev_info(&pdev->dev, "imprint %x TX cache %u RX cache %u\n",
916 readl_relaxed(ad->base + REG_IMPRINT), ad->txcache.size, ad->rxcache.size);
921 free_irq(ad->irq, ad);
923 reset_control_rearm(ad->rstc);
927 static int admac_remove(struct platform_device *pdev)
929 struct admac_data *ad = platform_get_drvdata(pdev);
931 of_dma_controller_free(pdev->dev.of_node);
932 dma_async_device_unregister(&ad->dma);
933 free_irq(ad->irq, ad);
934 reset_control_rearm(ad->rstc);
939 static const struct of_device_id admac_of_match[] = {
940 { .compatible = "apple,admac", },
943 MODULE_DEVICE_TABLE(of, admac_of_match);
945 static struct platform_driver apple_admac_driver = {
947 .name = "apple-admac",
948 .of_match_table = admac_of_match,
950 .probe = admac_probe,
951 .remove = admac_remove,
953 module_platform_driver(apple_admac_driver);
955 MODULE_AUTHOR("Martin PoviĊĦer <povik+lin@cutebit.org>");
956 MODULE_DESCRIPTION("Driver for Audio DMA Controller (ADMAC) on Apple SoCs");
957 MODULE_LICENSE("GPL");