2 * Freescale i.MX28 APBH DMA driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/list.h>
29 #include <asm/errno.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/imx-regs.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/arch/dma.h>
36 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
39 * Test is the DMA channel is valid channel
41 int mxs_dma_validate_chan(int channel)
43 struct mxs_dma_chan *pchan;
45 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
48 pchan = mxs_dma_channels + channel;
49 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
56 * Return the address of the command within a descriptor.
58 static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
60 return desc->address + offsetof(struct mxs_dma_desc, cmd);
64 * Read a DMA channel's hardware semaphore.
66 * As used by the MXS platform's DMA software, the DMA channel's hardware
67 * semaphore reflects the number of DMA commands the hardware will process, but
68 * has not yet finished. This is a volatile value read directly from hardware,
69 * so it must be be viewed as immediately stale.
71 * If the channel is not marked busy, or has finished processing all its
72 * commands, this value should be zero.
74 * See mxs_dma_append() for details on how DMA command blocks must be configured
75 * to maintain the expected behavior of the semaphore's value.
77 static int mxs_dma_read_semaphore(int channel)
79 struct mxs_apbh_regs *apbh_regs =
80 (struct mxs_apbh_regs *)MXS_APBH_BASE;
84 ret = mxs_dma_validate_chan(channel);
88 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
90 tmp &= APBH_CHn_SEMA_PHORE_MASK;
91 tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
96 #ifndef CONFIG_SYS_DCACHE_OFF
97 void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
102 addr = (uint32_t)desc;
103 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
105 flush_dcache_range(addr, addr + size);
108 inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
112 * Enable a DMA channel.
114 * If the given channel has any DMA descriptors on its active list, this
115 * function causes the DMA hardware to begin processing them.
117 * This function marks the DMA channel as "busy," whether or not there are any
118 * descriptors to process.
120 static int mxs_dma_enable(int channel)
122 struct mxs_apbh_regs *apbh_regs =
123 (struct mxs_apbh_regs *)MXS_APBH_BASE;
125 struct mxs_dma_chan *pchan;
126 struct mxs_dma_desc *pdesc;
129 ret = mxs_dma_validate_chan(channel);
133 pchan = mxs_dma_channels + channel;
135 if (pchan->pending_num == 0) {
136 pchan->flags |= MXS_DMA_FLAGS_BUSY;
140 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
144 if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
145 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
148 sem = mxs_dma_read_semaphore(channel);
153 pdesc = list_entry(pdesc->node.next,
154 struct mxs_dma_desc, node);
155 writel(mxs_dma_cmd_address(pdesc),
156 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
158 writel(pchan->pending_num,
159 &apbh_regs->ch[channel].hw_apbh_ch_sema);
160 pchan->active_num += pchan->pending_num;
161 pchan->pending_num = 0;
163 pchan->active_num += pchan->pending_num;
164 pchan->pending_num = 0;
165 writel(mxs_dma_cmd_address(pdesc),
166 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
167 writel(pchan->active_num,
168 &apbh_regs->ch[channel].hw_apbh_ch_sema);
169 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
170 &apbh_regs->hw_apbh_ctrl0_clr);
173 pchan->flags |= MXS_DMA_FLAGS_BUSY;
178 * Disable a DMA channel.
180 * This function shuts down a DMA channel and marks it as "not busy." Any
181 * descriptors on the active list are immediately moved to the head of the
182 * "done" list, whether or not they have actually been processed by the
183 * hardware. The "ready" flags of these descriptors are NOT cleared, so they
184 * still appear to be active.
186 * This function immediately shuts down a DMA channel's hardware, aborting any
187 * I/O that may be in progress, potentially leaving I/O hardware in an undefined
188 * state. It is unwise to call this function if there is ANY chance the hardware
189 * is still processing a command.
191 static int mxs_dma_disable(int channel)
193 struct mxs_dma_chan *pchan;
194 struct mxs_apbh_regs *apbh_regs =
195 (struct mxs_apbh_regs *)MXS_APBH_BASE;
198 ret = mxs_dma_validate_chan(channel);
202 pchan = mxs_dma_channels + channel;
204 if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
207 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
208 &apbh_regs->hw_apbh_ctrl0_set);
210 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
211 pchan->active_num = 0;
212 pchan->pending_num = 0;
213 list_splice_init(&pchan->active, &pchan->done);
219 * Resets the DMA channel hardware.
221 static int mxs_dma_reset(int channel)
223 struct mxs_apbh_regs *apbh_regs =
224 (struct mxs_apbh_regs *)MXS_APBH_BASE;
226 #if defined(CONFIG_MX23)
227 uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
228 uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
229 #elif defined(CONFIG_MX28)
230 uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
231 uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
234 ret = mxs_dma_validate_chan(channel);
238 writel(1 << (channel + offset), setreg);
244 * Enable or disable DMA interrupt.
246 * This function enables the given DMA channel to interrupt the CPU.
248 static int mxs_dma_enable_irq(int channel, int enable)
250 struct mxs_apbh_regs *apbh_regs =
251 (struct mxs_apbh_regs *)MXS_APBH_BASE;
254 ret = mxs_dma_validate_chan(channel);
259 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
260 &apbh_regs->hw_apbh_ctrl1_set);
262 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
263 &apbh_regs->hw_apbh_ctrl1_clr);
269 * Clear DMA interrupt.
271 * The software that is using the DMA channel must register to receive its
272 * interrupts and, when they arrive, must call this function to clear them.
274 static int mxs_dma_ack_irq(int channel)
276 struct mxs_apbh_regs *apbh_regs =
277 (struct mxs_apbh_regs *)MXS_APBH_BASE;
280 ret = mxs_dma_validate_chan(channel);
284 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
285 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
291 * Request to reserve a DMA channel
293 static int mxs_dma_request(int channel)
295 struct mxs_dma_chan *pchan;
297 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
300 pchan = mxs_dma_channels + channel;
301 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
304 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
307 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
308 pchan->active_num = 0;
309 pchan->pending_num = 0;
311 INIT_LIST_HEAD(&pchan->active);
312 INIT_LIST_HEAD(&pchan->done);
318 * Release a DMA channel.
320 * This function releases a DMA channel from its current owner.
322 * The channel will NOT be released if it's marked "busy" (see
325 int mxs_dma_release(int channel)
327 struct mxs_dma_chan *pchan;
330 ret = mxs_dma_validate_chan(channel);
334 pchan = mxs_dma_channels + channel;
336 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
340 pchan->active_num = 0;
341 pchan->pending_num = 0;
342 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
348 * Allocate DMA descriptor
350 struct mxs_dma_desc *mxs_dma_desc_alloc(void)
352 struct mxs_dma_desc *pdesc;
355 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
356 pdesc = memalign(MXS_DMA_ALIGNMENT, size);
361 memset(pdesc, 0, sizeof(*pdesc));
362 pdesc->address = (dma_addr_t)pdesc;
368 * Free DMA descriptor
370 void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
379 * Add a DMA descriptor to a channel.
381 * If the descriptor list for this channel is not empty, this function sets the
382 * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
383 * it will chain to the new descriptor's command.
385 * Then, this function marks the new descriptor as "ready," adds it to the end
386 * of the active descriptor list, and increments the count of pending
389 * The MXS platform DMA software imposes some rules on DMA commands to maintain
390 * important invariants. These rules are NOT checked, but they must be carefully
391 * applied by software that uses MXS DMA channels.
394 * The DMA channel's hardware semaphore must reflect the number of DMA
395 * commands the hardware will process, but has not yet finished.
398 * A DMA channel begins processing commands when its hardware semaphore is
399 * written with a value greater than zero, and it stops processing commands
400 * when the semaphore returns to zero.
402 * When a channel finishes a DMA command, it will decrement its semaphore if
403 * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
405 * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
406 * unless it suits the purposes of the software. For example, one could
407 * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
408 * bit set only in the last one. Then, setting the DMA channel's hardware
409 * semaphore to one would cause the entire series of five commands to be
410 * processed. However, this example would violate the invariant given above.
413 * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
414 * channel's hardware semaphore will be decremented EVERY time a command is
417 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
419 struct mxs_dma_chan *pchan;
420 struct mxs_dma_desc *last;
423 ret = mxs_dma_validate_chan(channel);
427 pchan = mxs_dma_channels + channel;
429 pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
430 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
432 if (!list_empty(&pchan->active)) {
433 last = list_entry(pchan->active.prev, struct mxs_dma_desc,
436 pdesc->flags &= ~MXS_DMA_DESC_FIRST;
437 last->flags &= ~MXS_DMA_DESC_LAST;
439 last->cmd.next = mxs_dma_cmd_address(pdesc);
440 last->cmd.data |= MXS_DMA_DESC_CHAIN;
442 mxs_dma_flush_desc(last);
444 pdesc->flags |= MXS_DMA_DESC_READY;
445 if (pdesc->flags & MXS_DMA_DESC_FIRST)
446 pchan->pending_num++;
447 list_add_tail(&pdesc->node, &pchan->active);
449 mxs_dma_flush_desc(pdesc);
455 * Clean up processed DMA descriptors.
457 * This function removes processed DMA descriptors from the "active" list. Pass
458 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
459 * to get the descriptors moved to the channel's "done" list. Descriptors on
460 * the "done" list can be retrieved with mxs_dma_get_finished().
462 * This function marks the DMA channel as "not busy" if no unprocessed
463 * descriptors remain on the "active" list.
465 static int mxs_dma_finish(int channel, struct list_head *head)
468 struct mxs_dma_chan *pchan;
469 struct list_head *p, *q;
470 struct mxs_dma_desc *pdesc;
473 ret = mxs_dma_validate_chan(channel);
477 pchan = mxs_dma_channels + channel;
479 sem = mxs_dma_read_semaphore(channel);
483 if (sem == pchan->active_num)
486 list_for_each_safe(p, q, &pchan->active) {
487 if ((pchan->active_num) <= sem)
490 pdesc = list_entry(p, struct mxs_dma_desc, node);
491 pdesc->flags &= ~MXS_DMA_DESC_READY;
494 list_move_tail(p, head);
496 list_move_tail(p, &pchan->done);
498 if (pdesc->flags & MXS_DMA_DESC_LAST)
503 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
509 * Wait for DMA channel to complete
511 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
513 struct mxs_apbh_regs *apbh_regs =
514 (struct mxs_apbh_regs *)MXS_APBH_BASE;
517 ret = mxs_dma_validate_chan(chan);
521 if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
522 1 << chan, timeout)) {
531 * Execute the DMA channel
533 int mxs_dma_go(int chan)
535 uint32_t timeout = 10000000;
538 LIST_HEAD(tmp_desc_list);
540 mxs_dma_enable_irq(chan, 1);
541 mxs_dma_enable(chan);
543 /* Wait for DMA to finish. */
544 ret = mxs_dma_wait_complete(timeout, chan);
546 /* Clear out the descriptors we just ran. */
547 mxs_dma_finish(chan, &tmp_desc_list);
549 /* Shut the DMA channel down. */
550 mxs_dma_ack_irq(chan);
552 mxs_dma_enable_irq(chan, 0);
553 mxs_dma_disable(chan);
559 * Initialize the DMA hardware
561 void mxs_dma_init(void)
563 struct mxs_apbh_regs *apbh_regs =
564 (struct mxs_apbh_regs *)MXS_APBH_BASE;
566 mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
568 #ifdef CONFIG_APBH_DMA_BURST8
569 writel(APBH_CTRL0_AHB_BURST8_EN,
570 &apbh_regs->hw_apbh_ctrl0_set);
572 writel(APBH_CTRL0_AHB_BURST8_EN,
573 &apbh_regs->hw_apbh_ctrl0_clr);
576 #ifdef CONFIG_APBH_DMA_BURST
577 writel(APBH_CTRL0_APB_BURST_EN,
578 &apbh_regs->hw_apbh_ctrl0_set);
580 writel(APBH_CTRL0_APB_BURST_EN,
581 &apbh_regs->hw_apbh_ctrl0_clr);
585 int mxs_dma_init_channel(int channel)
587 struct mxs_dma_chan *pchan;
590 pchan = mxs_dma_channels + channel;
591 pchan->flags = MXS_DMA_FLAGS_VALID;
593 ret = mxs_dma_request(channel);
596 printf("MXS DMA: Can't acquire DMA channel %i\n",
601 mxs_dma_reset(channel);
602 mxs_dma_ack_irq(channel);