drivers/dma/amba-pl08x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2006 ARM Ltd.
   4  * Copyright (c) 2010 ST-Ericsson SA
   5  * Copyirght (c) 2017 Linaro Ltd.
   6  *
   7  * Author: Peter Pearse <peter.pearse@arm.com>
   8  * Author: Linus Walleij <linus.walleij@linaro.org>
   9  *
  10  * Documentation: ARM DDI 0196G == PL080
  11  * Documentation: ARM DDI 0218E == PL081
  12  * Documentation: S3C6410 User's Manual == PL080S
  13  *
  14  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
  15  * channel.
  16  *
  17  * The PL080 has 8 channels available for simultaneous use, and the PL081
  18  * has only two channels. So on these DMA controllers the number of channels
  19  * and the number of incoming DMA signals are two totally different things.
  20  * It is usually not possible to theoretically handle all physical signals,
  21  * so a multiplexing scheme with possible denial of use is necessary.
  22  *
  23  * The PL080 has a dual bus master, PL081 has a single master.
  24  *
  25  * PL080S is a version modified by Samsung and used in S3C64xx SoCs.
  26  * It differs in following aspects:
  27  * - CH_CONFIG register at different offset,
  28  * - separate CH_CONTROL2 register for transfer size,
  29  * - bigger maximum transfer size,
  30  * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
  31  * - no support for peripheral flow control.
  32  *
  33  * Memory to peripheral transfer may be visualized as
  34  *      Get data from memory to DMAC
  35  *      Until no data left
  36  *              On burst request from peripheral
  37  *                      Destination burst from DMAC to peripheral
  38  *                      Clear burst request
  39  *      Raise terminal count interrupt
  40  *
  41  * For peripherals with a FIFO:
  42  * Source      burst size == half the depth of the peripheral FIFO
  43  * Destination burst size == the depth of the peripheral FIFO
  44  *
  45  * (Bursts are irrelevant for mem to mem transfers - there are no burst
  46  * signals, the DMA controller will simply facilitate its AHB master.)
  47  *
  48  * ASSUMES default (little) endianness for DMA transfers
  49  *
  50  * The PL08x has two flow control settings:
  51  *  - DMAC flow control: the transfer size defines the number of transfers
  52  *    which occur for the current LLI entry, and the DMAC raises TC at the
  53  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
  54  *    to both the BREQ and SREQ signals (contrary to documented),
  55  *    transferring data if either is active.  The LBREQ and LSREQ signals
  56  *    are ignored.
  57  *
  58  *  - Peripheral flow control: the transfer size is ignored (and should be
  59  *    zero).  The data is transferred from the current LLI entry, until
  60  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
  61  *    will then move to the next LLI entry. Unsupported by PL080S.
  62  */
  63 #ifndef CONFIG_SOC_STARFIVE_JH7110
  64 #include <linux/amba/bus.h>
  65 #endif
  66 #include <linux/amba/pl08x.h>
  67 #include <linux/debugfs.h>
  68 #include <linux/delay.h>
  69 #include <linux/device.h>
  70 #include <linux/dmaengine.h>
  71 #include <linux/dmapool.h>
  72 #include <linux/dma-mapping.h>
  73 #include <linux/export.h>
  74 #include <linux/init.h>
  75 #include <linux/interrupt.h>
  76 #include <linux/module.h>
  77 #include <linux/of.h>
  78 #include <linux/of_dma.h>
  79 #ifdef CONFIG_SOC_STARFIVE_JH7110
  80 #include <linux/of_device.h>
  81 #include <linux/platform_device.h>
  82 #endif
  83 #include <linux/pm_runtime.h>
  84 #include <linux/seq_file.h>
  85 #include <linux/slab.h>
  86 #include <linux/amba/pl080.h>
  87
  88 #include "dmaengine.h"
  89 #include "virt-dma.h"
  90
  91 #define DRIVER_NAME     "pl08xdmac"
  92
  93 #define PL80X_DMA_BUSWIDTHS \
  94         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  95         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  96         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  97         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  98
  99 #ifndef CONFIG_SOC_STARFIVE_JH7110
 100 static struct amba_driver pl08x_amba_driver;
 101 #endif
 102 struct pl08x_driver_data;
 103
 104 /**
 105  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
 106  * @config_offset: offset to the configuration register
 107  * @channels: the number of channels available in this variant
 108  * @signals: the number of request signals available from the hardware
 109  * @dualmaster: whether this version supports dual AHB masters or not.
 110  * @nomadik: whether this variant is a ST Microelectronics Nomadik, where the
 111  *      channels have Nomadik security extension bits that need to be checked
 112  *      for permission before use and some registers are missing
 113  * @pl080s: whether this variant is a Samsung PL080S, which has separate
 114  *      register and LLI word for transfer size.
 115  * @ftdmac020: whether this variant is a Faraday Technology FTDMAC020
 116  * @max_transfer_size: the maximum single element transfer size for this
 117  *      PL08x variant.
 118  */
 119 struct vendor_data {
 120         u8 config_offset;
 121         u8 channels;
 122         u8 signals;
 123         bool dualmaster;
 124         bool nomadik;
 125         bool pl080s;
 126         bool ftdmac020;
 127         u32 max_transfer_size;
 128 };
 129
 130 /**
 131  * struct pl08x_bus_data - information of source or destination
 132  * busses for a transfer
 133  * @addr: current address
 134  * @maxwidth: the maximum width of a transfer on this bus
 135  * @buswidth: the width of this bus in bytes: 1, 2 or 4
 136  */
 137 struct pl08x_bus_data {
 138         dma_addr_t addr;
 139         u8 maxwidth;
 140         u8 buswidth;
 141 };
 142
 143 #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
 144
 145 /**
 146  * struct pl08x_phy_chan - holder for the physical channels
 147  * @id: physical index to this channel
 148  * @base: memory base address for this physical channel
 149  * @reg_config: configuration address for this physical channel
 150  * @reg_control: control address for this physical channel
 151  * @reg_src: transfer source address register
 152  * @reg_dst: transfer destination address register
 153  * @reg_lli: transfer LLI address register
 154  * @reg_busy: if the variant has a special per-channel busy register,
 155  * this contains a pointer to it
 156  * @lock: a lock to use when altering an instance of this struct
 157  * @serving: the virtual channel currently being served by this physical
 158  * channel
 159  * @locked: channel unavailable for the system, e.g. dedicated to secure
 160  * world
 161  * @ftdmac020: channel is on a FTDMAC020
 162  * @pl080s: channel is on a PL08s
 163  */
 164 struct pl08x_phy_chan {
 165         unsigned int id;
 166         void __iomem *base;
 167         void __iomem *reg_config;
 168         void __iomem *reg_control;
 169         void __iomem *reg_src;
 170         void __iomem *reg_dst;
 171         void __iomem *reg_lli;
 172         void __iomem *reg_busy;
 173         spinlock_t lock;
 174         struct pl08x_dma_chan *serving;
 175         bool locked;
 176         bool ftdmac020;
 177         bool pl080s;
 178 };
 179
 180 /**
 181  * struct pl08x_sg - structure containing data per sg
 182  * @src_addr: src address of sg
 183  * @dst_addr: dst address of sg
 184  * @len: transfer len in bytes
 185  * @node: node for txd's dsg_list
 186  */
 187 struct pl08x_sg {
 188         dma_addr_t src_addr;
 189         dma_addr_t dst_addr;
 190         size_t len;
 191         struct list_head node;
 192 };
 193
 194 /**
 195  * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
 196  * @vd: virtual DMA descriptor
 197  * @dsg_list: list of children sg's
 198  * @llis_bus: DMA memory address (physical) start for the LLIs
 199  * @llis_va: virtual memory address start for the LLIs
 200  * @cctl: control reg values for current txd
 201  * @ccfg: config reg values for current txd
 202  * @done: this marks completed descriptors, which should not have their
 203  *   mux released.
 204  * @cyclic: indicate cyclic transfers
 205  */
 206 struct pl08x_txd {
 207         struct virt_dma_desc vd;
 208         struct list_head dsg_list;
 209         dma_addr_t llis_bus;
 210         u32 *llis_va;
 211         /* Default cctl value for LLIs */
 212         u32 cctl;
 213         /*
 214          * Settings to be put into the physical channel when we
 215          * trigger this txd.  Other registers are in llis_va[0].
 216          */
 217         u32 ccfg;
 218         bool done;
 219         bool cyclic;
 220 };
 221
 222 /**
 223  * enum pl08x_dma_chan_state - holds the PL08x specific virtual channel
 224  * states
 225  * @PL08X_CHAN_IDLE: the channel is idle
 226  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
 227  * channel and is running a transfer on it
 228  * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
 229  * channel, but the transfer is currently paused
 230  * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
 231  * channel to become available (only pertains to memcpy channels)
 232  */
 233 enum pl08x_dma_chan_state {
 234         PL08X_CHAN_IDLE,
 235         PL08X_CHAN_RUNNING,
 236         PL08X_CHAN_PAUSED,
 237         PL08X_CHAN_WAITING,
 238 };
 239
 240 /**
 241  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
 242  * @vc: wrappped virtual channel
 243  * @phychan: the physical channel utilized by this channel, if there is one
 244  * @name: name of channel
 245  * @cd: channel platform data
 246  * @cfg: slave configuration
 247  * @at: active transaction on this channel
 248  * @host: a pointer to the host (internal use)
 249  * @state: whether the channel is idle, paused, running etc
 250  * @slave: whether this channel is a device (slave) or for memcpy
 251  * @signal: the physical DMA request signal which this channel is using
 252  * @mux_use: count of descriptors using this DMA request signal setting
 253  * @waiting_at: time in jiffies when this channel moved to waiting state
 254  */
 255 struct pl08x_dma_chan {
 256         struct virt_dma_chan vc;
 257         struct pl08x_phy_chan *phychan;
 258         const char *name;
 259         struct pl08x_channel_data *cd;
 260         struct dma_slave_config cfg;
 261         struct pl08x_txd *at;
 262         struct pl08x_driver_data *host;
 263         enum pl08x_dma_chan_state state;
 264 #ifdef CONFIG_SOC_STARFIVE_JH7110
 265         int chan_id;
 266 #endif
 267         bool slave;
 268         int signal;
 269         unsigned mux_use;
 270         unsigned long waiting_at;
 271 };
 272
 273 /**
 274  * struct pl08x_driver_data - the local state holder for the PL08x
 275  * @slave: optional slave engine for this instance
 276  * @memcpy: memcpy engine for this instance
 277  * @has_slave: the PL08x has a slave engine (routed signals)
 278  * @base: virtual memory base (remapped) for the PL08x
 279  * @adev: the corresponding AMBA (PrimeCell) bus entry
 280  * @vd: vendor data for this PL08x variant
 281  * @pd: platform data passed in from the platform/machine
 282  * @phy_chans: array of data for the physical channels
 283  * @pool: a pool for the LLI descriptors
 284  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
 285  * fetches
 286  * @mem_buses: set to indicate memory transfers on AHB2.
 287  * @lli_words: how many words are used in each LLI item for this variant
 288  */
 289 struct pl08x_driver_data {
 290         struct dma_device slave;
 291         struct dma_device memcpy;
 292         bool has_slave;
 293         void __iomem *base;
 294 #ifdef CONFIG_SOC_STARFIVE_JH7110
 295         struct platform_device *adev;
 296 #else
 297         struct amba_device *adev;
 298 #endif
 299         const struct vendor_data *vd;
 300         struct pl08x_platform_data *pd;
 301         struct pl08x_phy_chan *phy_chans;
 302         struct dma_pool *pool;
 303         u8 lli_buses;
 304         u8 mem_buses;
 305         u8 lli_words;
 306 };
 307
 308 /*
 309  * PL08X specific defines
 310  */
 311
 312 /* The order of words in an LLI. */
 313 #define PL080_LLI_SRC           0
 314 #define PL080_LLI_DST           1
 315 #define PL080_LLI_LLI           2
 316 #define PL080_LLI_CCTL          3
 317 #define PL080S_LLI_CCTL2        4
 318
 319 /* Total words in an LLI. */
 320 #define PL080_LLI_WORDS         4
 321 #define PL080S_LLI_WORDS        8
 322
 323 /*
 324  * Number of LLIs in each LLI buffer allocated for one transfer
 325  * (maximum times we call dma_pool_alloc on this pool without freeing)
 326  */
 327 #define MAX_NUM_TSFR_LLIS       512
 328 #define PL08X_ALIGN             8
 329
 330 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
 331 {
 332         return container_of(chan, struct pl08x_dma_chan, vc.chan);
 333 }
 334
 335 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
 336 {
 337         return container_of(tx, struct pl08x_txd, vd.tx);
 338 }
 339
 340 /*
 341  * Mux handling.
 342  *
 343  * This gives us the DMA request input to the PL08x primecell which the
 344  * peripheral described by the channel data will be routed to, possibly
 345  * via a board/SoC specific external MUX.  One important point to note
 346  * here is that this does not depend on the physical channel.
 347  */
 348 static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
 349 {
 350         const struct pl08x_platform_data *pd = plchan->host->pd;
 351         int ret;
 352
 353         if (plchan->mux_use++ == 0 && pd->get_xfer_signal) {
 354                 ret = pd->get_xfer_signal(plchan->cd);
 355                 if (ret < 0) {
 356                         plchan->mux_use = 0;
 357                         return ret;
 358                 }
 359
 360                 plchan->signal = ret;
 361         }
 362         return 0;
 363 }
 364
 365 static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
 366 {
 367         const struct pl08x_platform_data *pd = plchan->host->pd;
 368
 369         if (plchan->signal >= 0) {
 370                 WARN_ON(plchan->mux_use == 0);
 371
 372                 if (--plchan->mux_use == 0 && pd->put_xfer_signal) {
 373                         pd->put_xfer_signal(plchan->cd, plchan->signal);
 374                         plchan->signal = -1;
 375                 }
 376         }
 377 }
 378
 379 /*
 380  * Physical channel handling
 381  */
 382
 383 /* Whether a certain channel is busy or not */
 384 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
 385 {
 386         unsigned int val;
 387
 388         /* If we have a special busy register, take a shortcut */
 389         if (ch->reg_busy) {
 390                 val = readl(ch->reg_busy);
 391                 return !!(val & BIT(ch->id));
 392         }
 393         val = readl(ch->reg_config);
 394         return val & PL080_CONFIG_ACTIVE;
 395 }
 396
 397 /*
 398  * pl08x_write_lli() - Write an LLI into the DMA controller.
 399  *
 400  * The PL08x derivatives support linked lists, but the first item of the
 401  * list containing the source, destination, control word and next LLI is
 402  * ignored. Instead the driver has to write those values directly into the
 403  * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE
 404  * register need to be set up for the first transfer.
 405  */
 406 static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
 407                 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
 408 {
 409         if (pl08x->vd->pl080s)
 410                 dev_vdbg(&pl08x->adev->dev,
 411                         "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 412                         "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",
 413                         phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
 414                         lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL],
 415                         lli[PL080S_LLI_CCTL2], ccfg);
 416         else
 417                 dev_vdbg(&pl08x->adev->dev,
 418                         "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
 419                         "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
 420                         phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
 421                         lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);
 422
 423         writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
 424         writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
 425         writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
 426
 427         /*
 428          * The FTMAC020 has a different layout in the CCTL word of the LLI
 429          * and the CCTL register which is split in CSR and SIZE registers.
 430          * Convert the LLI item CCTL into the proper values to write into
 431          * the CSR and SIZE registers.
 432          */
 433         if (phychan->ftdmac020) {
 434                 u32 llictl = lli[PL080_LLI_CCTL];
 435                 u32 val = 0;
 436
 437                 /* Write the transfer size (12 bits) to the size register */
 438                 writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK,
 439                                phychan->base + FTDMAC020_CH_SIZE);
 440                 /*
 441                  * Then write the control bits 28..16 to the control register
 442                  * by shuffleing the bits around to where they are in the
 443                  * main register. The mapping is as follows:
 444                  * Bit 28: TC_MSK - mask on all except last LLI
 445                  * Bit 27..25: SRC_WIDTH
 446                  * Bit 24..22: DST_WIDTH
 447                  * Bit 21..20: SRCAD_CTRL
 448                  * Bit 19..17: DSTAD_CTRL
 449                  * Bit 17: SRC_SEL
 450                  * Bit 16: DST_SEL
 451                  */
 452                 if (llictl & FTDMAC020_LLI_TC_MSK)
 453                         val |= FTDMAC020_CH_CSR_TC_MSK;
 454                 val |= ((llictl  & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
 455                         (FTDMAC020_LLI_SRC_WIDTH_SHIFT -
 456                          FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT));
 457                 val |= ((llictl  & FTDMAC020_LLI_DST_WIDTH_MSK) >>
 458                         (FTDMAC020_LLI_DST_WIDTH_SHIFT -
 459                          FTDMAC020_CH_CSR_DST_WIDTH_SHIFT));
 460                 val |= ((llictl  & FTDMAC020_LLI_SRCAD_CTL_MSK) >>
 461                         (FTDMAC020_LLI_SRCAD_CTL_SHIFT -
 462                          FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT));
 463                 val |= ((llictl  & FTDMAC020_LLI_DSTAD_CTL_MSK) >>
 464                         (FTDMAC020_LLI_DSTAD_CTL_SHIFT -
 465                          FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT));
 466                 if (llictl & FTDMAC020_LLI_SRC_SEL)
 467                         val |= FTDMAC020_CH_CSR_SRC_SEL;
 468                 if (llictl & FTDMAC020_LLI_DST_SEL)
 469                         val |= FTDMAC020_CH_CSR_DST_SEL;
 470
 471                 /*
 472                  * Set up the bits that exist in the CSR but are not
 473                  * part the LLI, i.e. only gets written to the control
 474                  * register right here.
 475                  *
 476                  * FIXME: do not just handle memcpy, also handle slave DMA.
 477                  */
 478                 switch (pl08x->pd->memcpy_burst_size) {
 479                 default:
 480                 case PL08X_BURST_SZ_1:
 481                         val |= PL080_BSIZE_1 <<
 482                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 483                         break;
 484                 case PL08X_BURST_SZ_4:
 485                         val |= PL080_BSIZE_4 <<
 486                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 487                         break;
 488                 case PL08X_BURST_SZ_8:
 489                         val |= PL080_BSIZE_8 <<
 490                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 491                         break;
 492                 case PL08X_BURST_SZ_16:
 493                         val |= PL080_BSIZE_16 <<
 494                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 495                         break;
 496                 case PL08X_BURST_SZ_32:
 497                         val |= PL080_BSIZE_32 <<
 498                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 499                         break;
 500                 case PL08X_BURST_SZ_64:
 501                         val |= PL080_BSIZE_64 <<
 502                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 503                         break;
 504                 case PL08X_BURST_SZ_128:
 505                         val |= PL080_BSIZE_128 <<
 506                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 507                         break;
 508                 case PL08X_BURST_SZ_256:
 509                         val |= PL080_BSIZE_256 <<
 510                                 FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
 511                         break;
 512                 }
 513
 514                 /* Protection flags */
 515                 if (pl08x->pd->memcpy_prot_buff)
 516                         val |= FTDMAC020_CH_CSR_PROT2;
 517                 if (pl08x->pd->memcpy_prot_cache)
 518                         val |= FTDMAC020_CH_CSR_PROT3;
 519                 /* We are the kernel, so we are in privileged mode */
 520                 val |= FTDMAC020_CH_CSR_PROT1;
 521
 522                 writel_relaxed(val, phychan->reg_control);
 523         } else {
 524                 /* Bits are just identical */
 525                 writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
 526         }
 527
 528         /* Second control word on the PL080s */
 529         if (pl08x->vd->pl080s)
 530                 writel_relaxed(lli[PL080S_LLI_CCTL2],
 531                                 phychan->base + PL080S_CH_CONTROL2);
 532
 533         writel(ccfg, phychan->reg_config);
 534 }
 535
 536 /*
 537  * Set the initial DMA register values i.e. those for the first LLI
 538  * The next LLI pointer and the configuration interrupt bit have
 539  * been set when the LLIs were constructed.  Poke them into the hardware
 540  * and start the transfer.
 541  */
 542 static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 543 {
 544         struct pl08x_driver_data *pl08x = plchan->host;
 545         struct pl08x_phy_chan *phychan = plchan->phychan;
 546         struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc);
 547         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
 548         u32 val;
 549
 550         list_del(&txd->vd.node);
 551
 552         plchan->at = txd;
 553
 554         /* Wait for channel inactive */
 555         while (pl08x_phy_channel_busy(phychan))
 556                 cpu_relax();
 557
 558         pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);
 559
 560         /* Enable the DMA channel */
 561         /* Do not access config register until channel shows as disabled */
 562         while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
 563                 cpu_relax();
 564
 565         /* Do not access config register until channel shows as inactive */
 566         if (phychan->ftdmac020) {
 567                 val = readl(phychan->reg_config);
 568                 while (val & FTDMAC020_CH_CFG_BUSY)
 569                         val = readl(phychan->reg_config);
 570
 571                 val = readl(phychan->reg_control);
 572                 while (val & FTDMAC020_CH_CSR_EN)
 573                         val = readl(phychan->reg_control);
 574
 575                 writel(val | FTDMAC020_CH_CSR_EN,
 576                        phychan->reg_control);
 577         } else {
 578                 val = readl(phychan->reg_config);
 579                 while ((val & PL080_CONFIG_ACTIVE) ||
 580                        (val & PL080_CONFIG_ENABLE))
 581                         val = readl(phychan->reg_config);
 582
 583                 writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
 584         }
 585 }
 586
 587 /*
 588  * Pause the channel by setting the HALT bit.
 589  *
 590  * For M->P transfers, pause the DMAC first and then stop the peripheral -
 591  * the FIFO can only drain if the peripheral is still requesting data.
 592  * (note: this can still timeout if the DMAC FIFO never drains of data.)
 593  *
 594  * For P->M transfers, disable the peripheral first to stop it filling
 595  * the DMAC FIFO, and then pause the DMAC.
 596  */
 597 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
 598 {
 599         u32 val;
 600         int timeout;
 601
 602         if (ch->ftdmac020) {
 603                 /* Use the enable bit on the FTDMAC020 */
 604                 val = readl(ch->reg_control);
 605                 val &= ~FTDMAC020_CH_CSR_EN;
 606                 writel(val, ch->reg_control);
 607                 return;
 608         }
 609
 610         /* Set the HALT bit and wait for the FIFO to drain */
 611         val = readl(ch->reg_config);
 612         val |= PL080_CONFIG_HALT;
 613         writel(val, ch->reg_config);
 614
 615         /* Wait for channel inactive */
 616         for (timeout = 1000; timeout; timeout--) {
 617                 if (!pl08x_phy_channel_busy(ch))
 618                         break;
 619                 udelay(1);
 620         }
 621         if (pl08x_phy_channel_busy(ch))
 622                 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
 623 }
 624
 625 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
 626 {
 627         u32 val;
 628
 629         /* Use the enable bit on the FTDMAC020 */
 630         if (ch->ftdmac020) {
 631                 val = readl(ch->reg_control);
 632                 val |= FTDMAC020_CH_CSR_EN;
 633                 writel(val, ch->reg_control);
 634                 return;
 635         }
 636
 637         /* Clear the HALT bit */
 638         val = readl(ch->reg_config);
 639         val &= ~PL080_CONFIG_HALT;
 640         writel(val, ch->reg_config);
 641 }
 642
 643 /*
 644  * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
 645  * clears any pending interrupt status.  This should not be used for
 646  * an on-going transfer, but as a method of shutting down a channel
 647  * (eg, when it's no longer used) or terminating a transfer.
 648  */
 649 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 650         struct pl08x_phy_chan *ch)
 651 {
 652         u32 val;
 653
 654         /* The layout for the FTDMAC020 is different */
 655         if (ch->ftdmac020) {
 656                 /* Disable all interrupts */
 657                 val = readl(ch->reg_config);
 658                 val |= (FTDMAC020_CH_CFG_INT_ABT_MASK |
 659                         FTDMAC020_CH_CFG_INT_ERR_MASK |
 660                         FTDMAC020_CH_CFG_INT_TC_MASK);
 661                 writel(val, ch->reg_config);
 662
 663                 /* Abort and disable channel */
 664                 val = readl(ch->reg_control);
 665                 val &= ~FTDMAC020_CH_CSR_EN;
 666                 val |= FTDMAC020_CH_CSR_ABT;
 667                 writel(val, ch->reg_control);
 668
 669                 /* Clear ABT and ERR interrupt flags */
 670                 writel(BIT(ch->id) | BIT(ch->id + 16),
 671                        pl08x->base + PL080_ERR_CLEAR);
 672                 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
 673
 674                 return;
 675         }
 676
 677         val = readl(ch->reg_config);
 678         val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
 679                  PL080_CONFIG_TC_IRQ_MASK);
 680         writel(val, ch->reg_config);
 681
 682         writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
 683         writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
 684 }
 685
 686 static u32 get_bytes_in_phy_channel(struct pl08x_phy_chan *ch)
 687 {
 688         u32 val;
 689         u32 bytes;
 690
 691         if (ch->ftdmac020) {
 692                 bytes = readl(ch->base + FTDMAC020_CH_SIZE);
 693
 694                 val = readl(ch->reg_control);
 695                 val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK;
 696                 val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT;
 697         } else if (ch->pl080s) {
 698                 val = readl(ch->base + PL080S_CH_CONTROL2);
 699                 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 700
 701                 val = readl(ch->reg_control);
 702                 val &= PL080_CONTROL_SWIDTH_MASK;
 703                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 704         } else {
 705                 /* Plain PL08x */
 706                 val = readl(ch->reg_control);
 707                 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
 708
 709                 val &= PL080_CONTROL_SWIDTH_MASK;
 710                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 711         }
 712
 713         switch (val) {
 714         case PL080_WIDTH_8BIT:
 715                 break;
 716         case PL080_WIDTH_16BIT:
 717                 bytes *= 2;
 718                 break;
 719         case PL080_WIDTH_32BIT:
 720                 bytes *= 4;
 721                 break;
 722         }
 723         return bytes;
 724 }
 725
 726 static u32 get_bytes_in_lli(struct pl08x_phy_chan *ch, const u32 *llis_va)
 727 {
 728         u32 val;
 729         u32 bytes;
 730
 731         if (ch->ftdmac020) {
 732                 val = llis_va[PL080_LLI_CCTL];
 733                 bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK;
 734
 735                 val = llis_va[PL080_LLI_CCTL];
 736                 val &= FTDMAC020_LLI_SRC_WIDTH_MSK;
 737                 val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT;
 738         } else if (ch->pl080s) {
 739                 val = llis_va[PL080S_LLI_CCTL2];
 740                 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
 741
 742                 val = llis_va[PL080_LLI_CCTL];
 743                 val &= PL080_CONTROL_SWIDTH_MASK;
 744                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 745         } else {
 746                 /* Plain PL08x */
 747                 val = llis_va[PL080_LLI_CCTL];
 748                 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
 749
 750                 val &= PL080_CONTROL_SWIDTH_MASK;
 751                 val >>= PL080_CONTROL_SWIDTH_SHIFT;
 752         }
 753
 754         switch (val) {
 755         case PL080_WIDTH_8BIT:
 756                 break;
 757         case PL080_WIDTH_16BIT:
 758                 bytes *= 2;
 759                 break;
 760         case PL080_WIDTH_32BIT:
 761                 bytes *= 4;
 762                 break;
 763         }
 764         return bytes;
 765 }
 766
 767 /* The channel should be paused when calling this */
 768 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
 769 {
 770         struct pl08x_driver_data *pl08x = plchan->host;
 771         const u32 *llis_va, *llis_va_limit;
 772         struct pl08x_phy_chan *ch;
 773         dma_addr_t llis_bus;
 774         struct pl08x_txd *txd;
 775         u32 llis_max_words;
 776         size_t bytes;
 777         u32 clli;
 778
 779         ch = plchan->phychan;
 780         txd = plchan->at;
 781
 782         if (!ch || !txd)
 783                 return 0;
 784
 785         /*
 786          * Follow the LLIs to get the number of remaining
 787          * bytes in the currently active transaction.
 788          */
 789         clli = readl(ch->reg_lli) & ~PL080_LLI_LM_AHB2;
 790
 791         /* First get the remaining bytes in the active transfer */
 792         bytes = get_bytes_in_phy_channel(ch);
 793
 794         if (!clli)
 795                 return bytes;
 796
 797         llis_va = txd->llis_va;
 798         llis_bus = txd->llis_bus;
 799
 800         llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS;
 801         BUG_ON(clli < llis_bus || clli >= llis_bus +
 802                                                 sizeof(u32) * llis_max_words);
 803
 804         /*
 805          * Locate the next LLI - as this is an array,
 806          * it's simple maths to find.
 807          */
 808         llis_va += (clli - llis_bus) / sizeof(u32);
 809
 810         llis_va_limit = llis_va + llis_max_words;
 811
 812         for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) {
 813                 bytes += get_bytes_in_lli(ch, llis_va);
 814
 815                 /*
 816                  * A LLI pointer going backward terminates the LLI list
 817                  */
 818                 if (llis_va[PL080_LLI_LLI] <= clli)
 819                         break;
 820         }
 821
 822         return bytes;
 823 }
 824
 825 /*
 826  * Allocate a physical channel for a virtual channel
 827  *
 828  * Try to locate a physical channel to be used for this transfer. If all
 829  * are taken return NULL and the requester will have to cope by using
 830  * some fallback PIO mode or retrying later.
 831  */
 832 static struct pl08x_phy_chan *
 833 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
 834                       struct pl08x_dma_chan *virt_chan)
 835 {
 836         struct pl08x_phy_chan *ch = NULL;
 837         unsigned long flags;
 838         int i;
 839
 840 #ifdef CONFIG_SOC_STARFIVE_JH7110
 841         ch = &pl08x->phy_chans[virt_chan->chan_id];
 842
 843         spin_lock_irqsave(&ch->lock, flags);
 844
 845         if (!ch->locked && !ch->serving) {
 846                 ch->serving = virt_chan;
 847                 spin_unlock_irqrestore(&ch->lock, flags);
 848                 return ch;
 849         }
 850
 851         spin_unlock_irqrestore(&ch->lock, flags);
 852 #endif
 853         for (i = 0; i < pl08x->vd->channels; i++) {
 854                 ch = &pl08x->phy_chans[i];
 855
 856                 spin_lock_irqsave(&ch->lock, flags);
 857
 858                 if (!ch->locked && !ch->serving) {
 859                         ch->serving = virt_chan;
 860                         spin_unlock_irqrestore(&ch->lock, flags);
 861                         break;
 862                 }
 863
 864                 spin_unlock_irqrestore(&ch->lock, flags);
 865         }
 866
 867         if (i == pl08x->vd->channels) {
 868                 /* No physical channel available, cope with it */
 869                 return NULL;
 870         }
 871
 872         return ch;
 873 }
 874
 875 /* Mark the physical channel as free.  Note, this write is atomic. */
 876 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
 877                                          struct pl08x_phy_chan *ch)
 878 {
 879         ch->serving = NULL;
 880 }
 881
 882 /*
 883  * Try to allocate a physical channel.  When successful, assign it to
 884  * this virtual channel, and initiate the next descriptor.  The
 885  * virtual channel lock must be held at this point.
 886  */
 887 static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan)
 888 {
 889         struct pl08x_driver_data *pl08x = plchan->host;
 890         struct pl08x_phy_chan *ch;
 891
 892         ch = pl08x_get_phy_channel(pl08x, plchan);
 893         if (!ch) {
 894                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
 895                 plchan->state = PL08X_CHAN_WAITING;
 896                 plchan->waiting_at = jiffies;
 897                 return;
 898         }
 899
 900         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
 901                 ch->id, plchan->name);
 902
 903         plchan->phychan = ch;
 904         plchan->state = PL08X_CHAN_RUNNING;
 905         pl08x_start_next_txd(plchan);
 906 }
 907
 908 static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
 909         struct pl08x_dma_chan *plchan)
 910 {
 911         struct pl08x_driver_data *pl08x = plchan->host;
 912
 913         dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
 914                 ch->id, plchan->name);
 915
 916         /*
 917          * We do this without taking the lock; we're really only concerned
 918          * about whether this pointer is NULL or not, and we're guaranteed
 919          * that this will only be called when it _already_ is non-NULL.
 920          */
 921         ch->serving = plchan;
 922         plchan->phychan = ch;
 923         plchan->state = PL08X_CHAN_RUNNING;
 924         pl08x_start_next_txd(plchan);
 925 }
 926
 927 /*
 928  * Free a physical DMA channel, potentially reallocating it to another
 929  * virtual channel if we have any pending.
 930  */
 931 static void pl08x_phy_free(struct pl08x_dma_chan *plchan)
 932 {
 933         struct pl08x_driver_data *pl08x = plchan->host;
 934         struct pl08x_dma_chan *p, *next;
 935         unsigned long waiting_at;
 936  retry:
 937         next = NULL;
 938         waiting_at = jiffies;
 939
 940         /*
 941          * Find a waiting virtual channel for the next transfer.
 942          * To be fair, time when each channel reached waiting state is compared
 943          * to select channel that is waiting for the longest time.
 944          */
 945         list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
 946                 if (p->state == PL08X_CHAN_WAITING &&
 947                     p->waiting_at <= waiting_at) {
 948                         next = p;
 949                         waiting_at = p->waiting_at;
 950                 }
 951
 952         if (!next && pl08x->has_slave) {
 953                 list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
 954                         if (p->state == PL08X_CHAN_WAITING &&
 955                             p->waiting_at <= waiting_at) {
 956                                 next = p;
 957                                 waiting_at = p->waiting_at;
 958                         }
 959         }
 960
 961         /* Ensure that the physical channel is stopped */
 962         pl08x_terminate_phy_chan(pl08x, plchan->phychan);
 963
 964         if (next) {
 965                 bool success;
 966
 967                 /*
 968                  * Eww.  We know this isn't going to deadlock
 969                  * but lockdep probably doesn't.
 970                  */
 971                 spin_lock(&next->vc.lock);
 972                 /* Re-check the state now that we have the lock */
 973                 success = next->state == PL08X_CHAN_WAITING;
 974                 if (success)
 975                         pl08x_phy_reassign_start(plchan->phychan, next);
 976                 spin_unlock(&next->vc.lock);
 977
 978                 /* If the state changed, try to find another channel */
 979                 if (!success)
 980                         goto retry;
 981         } else {
 982                 /* No more jobs, so free up the physical channel */
 983                 pl08x_put_phy_channel(pl08x, plchan->phychan);
 984         }
 985
 986         plchan->phychan = NULL;
 987         plchan->state = PL08X_CHAN_IDLE;
 988 }
 989
 990 /*
 991  * LLI handling
 992  */
 993
 994 static inline unsigned int
 995 pl08x_get_bytes_for_lli(struct pl08x_driver_data *pl08x,
 996                         u32 cctl,
 997                         bool source)
 998 {
 999         u32 val;
1000
1001         if (pl08x->vd->ftdmac020) {
1002                 if (source)
1003                         val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
1004                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1005                 else
1006                         val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
1007                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1008         } else {
1009                 if (source)
1010                         val = (cctl & PL080_CONTROL_SWIDTH_MASK) >>
1011                                 PL080_CONTROL_SWIDTH_SHIFT;
1012                 else
1013                         val = (cctl & PL080_CONTROL_DWIDTH_MASK) >>
1014                                 PL080_CONTROL_DWIDTH_SHIFT;
1015         }
1016
1017         switch (val) {
1018         case PL080_WIDTH_8BIT:
1019                 return 1;
1020         case PL080_WIDTH_16BIT:
1021                 return 2;
1022         case PL080_WIDTH_32BIT:
1023                 return 4;
1024         default:
1025                 break;
1026         }
1027         BUG();
1028         return 0;
1029 }
1030
1031 static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x,
1032                                          u32 cctl,
1033                                          u8 srcwidth, u8 dstwidth,
1034                                          size_t tsize)
1035 {
1036         u32 retbits = cctl;
1037
1038         /*
1039          * Remove all src, dst and transfer size bits, then set the
1040          * width and size according to the parameters. The bit offsets
1041          * are different in the FTDMAC020 so we need to accound for this.
1042          */
1043         if (pl08x->vd->ftdmac020) {
1044                 retbits &= ~FTDMAC020_LLI_DST_WIDTH_MSK;
1045                 retbits &= ~FTDMAC020_LLI_SRC_WIDTH_MSK;
1046                 retbits &= ~FTDMAC020_LLI_TRANSFER_SIZE_MASK;
1047
1048                 switch (srcwidth) {
1049                 case 1:
1050                         retbits |= PL080_WIDTH_8BIT <<
1051                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1052                         break;
1053                 case 2:
1054                         retbits |= PL080_WIDTH_16BIT <<
1055                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1056                         break;
1057                 case 4:
1058                         retbits |= PL080_WIDTH_32BIT <<
1059                                 FTDMAC020_LLI_SRC_WIDTH_SHIFT;
1060                         break;
1061                 default:
1062                         BUG();
1063                         break;
1064                 }
1065
1066                 switch (dstwidth) {
1067                 case 1:
1068                         retbits |= PL080_WIDTH_8BIT <<
1069                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1070                         break;
1071                 case 2:
1072                         retbits |= PL080_WIDTH_16BIT <<
1073                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1074                         break;
1075                 case 4:
1076                         retbits |= PL080_WIDTH_32BIT <<
1077                                 FTDMAC020_LLI_DST_WIDTH_SHIFT;
1078                         break;
1079                 default:
1080                         BUG();
1081                         break;
1082                 }
1083
1084                 tsize &= FTDMAC020_LLI_TRANSFER_SIZE_MASK;
1085                 retbits |= tsize << FTDMAC020_LLI_TRANSFER_SIZE_SHIFT;
1086         } else {
1087                 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
1088                 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
1089                 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
1090
1091                 switch (srcwidth) {
1092                 case 1:
1093                         retbits |= PL080_WIDTH_8BIT <<
1094                                 PL080_CONTROL_SWIDTH_SHIFT;
1095                         break;
1096                 case 2:
1097                         retbits |= PL080_WIDTH_16BIT <<
1098                                 PL080_CONTROL_SWIDTH_SHIFT;
1099                         break;
1100                 case 4:
1101                         retbits |= PL080_WIDTH_32BIT <<
1102                                 PL080_CONTROL_SWIDTH_SHIFT;
1103                         break;
1104                 default:
1105                         BUG();
1106                         break;
1107                 }
1108
1109                 switch (dstwidth) {
1110                 case 1:
1111                         retbits |= PL080_WIDTH_8BIT <<
1112                                 PL080_CONTROL_DWIDTH_SHIFT;
1113                         break;
1114                 case 2:
1115                         retbits |= PL080_WIDTH_16BIT <<
1116                                 PL080_CONTROL_DWIDTH_SHIFT;
1117                         break;
1118                 case 4:
1119                         retbits |= PL080_WIDTH_32BIT <<
1120                                 PL080_CONTROL_DWIDTH_SHIFT;
1121                         break;
1122                 default:
1123                         BUG();
1124                         break;
1125                 }
1126
1127                 tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK;
1128                 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
1129         }
1130
1131         return retbits;
1132 }
1133
1134 struct pl08x_lli_build_data {
1135         struct pl08x_txd *txd;
1136         struct pl08x_bus_data srcbus;
1137         struct pl08x_bus_data dstbus;
1138         size_t remainder;
1139         u32 lli_bus;
1140 };
1141
1142 /*
1143  * Autoselect a master bus to use for the transfer. Slave will be the chosen as
1144  * victim in case src & dest are not similarly aligned. i.e. If after aligning
1145  * masters address with width requirements of transfer (by sending few byte by
1146  * byte data), slave is still not aligned, then its width will be reduced to
1147  * BYTE.
1148  * - prefers the destination bus if both available
1149  * - prefers bus with fixed address (i.e. peripheral)
1150  */
1151 static void pl08x_choose_master_bus(struct pl08x_driver_data *pl08x,
1152                                     struct pl08x_lli_build_data *bd,
1153                                     struct pl08x_bus_data **mbus,
1154                                     struct pl08x_bus_data **sbus,
1155                                     u32 cctl)
1156 {
1157         bool dst_incr;
1158         bool src_incr;
1159
1160         /*
1161          * The FTDMAC020 only supports memory-to-memory transfer, so
1162          * source and destination always increase.
1163          */
1164         if (pl08x->vd->ftdmac020) {
1165                 dst_incr = true;
1166                 src_incr = true;
1167         } else {
1168                 dst_incr = !!(cctl & PL080_CONTROL_DST_INCR);
1169                 src_incr = !!(cctl & PL080_CONTROL_SRC_INCR);
1170         }
1171
1172         /*
1173          * If either bus is not advancing, i.e. it is a peripheral, that
1174          * one becomes master
1175          */
1176         if (!dst_incr) {
1177                 *mbus = &bd->dstbus;
1178                 *sbus = &bd->srcbus;
1179         } else if (!src_incr) {
1180                 *mbus = &bd->srcbus;
1181                 *sbus = &bd->dstbus;
1182         } else {
1183                 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
1184                         *mbus = &bd->dstbus;
1185                         *sbus = &bd->srcbus;
1186                 } else {
1187                         *mbus = &bd->srcbus;
1188                         *sbus = &bd->dstbus;
1189                 }
1190         }
1191 }
1192
1193 /*
1194  * Fills in one LLI for a certain transfer descriptor and advance the counter
1195  */
1196 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
1197                                     struct pl08x_lli_build_data *bd,
1198                                     int num_llis, int len, u32 cctl, u32 cctl2)
1199 {
1200         u32 offset = num_llis * pl08x->lli_words;
1201         u32 *llis_va = bd->txd->llis_va + offset;
1202         dma_addr_t llis_bus = bd->txd->llis_bus;
1203
1204         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
1205
1206         /* Advance the offset to next LLI. */
1207         offset += pl08x->lli_words;
1208
1209         llis_va[PL080_LLI_SRC] = bd->srcbus.addr;
1210         llis_va[PL080_LLI_DST] = bd->dstbus.addr;
1211         llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset);
1212         llis_va[PL080_LLI_LLI] |= bd->lli_bus;
1213         llis_va[PL080_LLI_CCTL] = cctl;
1214         if (pl08x->vd->pl080s)
1215                 llis_va[PL080S_LLI_CCTL2] = cctl2;
1216
1217         if (pl08x->vd->ftdmac020) {
1218                 /* FIXME: only memcpy so far so both increase */
1219                 bd->srcbus.addr += len;
1220                 bd->dstbus.addr += len;
1221         } else {
1222                 if (cctl & PL080_CONTROL_SRC_INCR)
1223                         bd->srcbus.addr += len;
1224                 if (cctl & PL080_CONTROL_DST_INCR)
1225                         bd->dstbus.addr += len;
1226         }
1227
1228         BUG_ON(bd->remainder < len);
1229
1230         bd->remainder -= len;
1231 }
1232
1233 static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
1234                         struct pl08x_lli_build_data *bd, u32 *cctl, u32 len,
1235                         int num_llis, size_t *total_bytes)
1236 {
1237         *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len);
1238         pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len);
1239         (*total_bytes) += len;
1240 }
1241
1242 #if 1
1243 static void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1244                            const u32 *llis_va, int num_llis)
1245 {
1246         int i;
1247
1248         if (pl08x->vd->pl080s) {
1249                 dev_vdbg(&pl08x->adev->dev,
1250                         "%-3s %-9s  %-10s %-10s %-10s %-10s %s\n",
1251                         "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
1252                 for (i = 0; i < num_llis; i++) {
1253                         dev_vdbg(&pl08x->adev->dev,
1254                                 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1255                                 i, llis_va, llis_va[PL080_LLI_SRC],
1256                                 llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
1257                                 llis_va[PL080_LLI_CCTL],
1258                                 llis_va[PL080S_LLI_CCTL2]);
1259                         llis_va += pl08x->lli_words;
1260                 }
1261         } else {
1262                 dev_vdbg(&pl08x->adev->dev,
1263                         "%-3s %-9s  %-10s %-10s %-10s %s\n",
1264                         "lli", "", "csrc", "cdst", "clli", "cctl");
1265                 for (i = 0; i < num_llis; i++) {
1266                         dev_vdbg(&pl08x->adev->dev,
1267                                 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1268                                 i, llis_va, llis_va[PL080_LLI_SRC],
1269                                 llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
1270                                 llis_va[PL080_LLI_CCTL]);
1271                         llis_va += pl08x->lli_words;
1272                 }
1273         }
1274 }
1275 #else
1276 static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1277                                   const u32 *llis_va, int num_llis) {}
1278 #endif
1279
1280 /*
1281  * This fills in the table of LLIs for the transfer descriptor
1282  * Note that we assume we never have to change the burst sizes
1283  * Return 0 for error
1284  */
1285 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
1286                               struct pl08x_txd *txd)
1287 {
1288         struct pl08x_bus_data *mbus, *sbus;
1289         struct pl08x_lli_build_data bd;
1290         int num_llis = 0;
1291         u32 cctl, early_bytes = 0;
1292         size_t max_bytes_per_lli, total_bytes;
1293         u32 *llis_va, *last_lli;
1294         struct pl08x_sg *dsg;
1295
1296         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
1297         if (!txd->llis_va) {
1298                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
1299                 return 0;
1300         }
1301
1302         bd.txd = txd;
1303         bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
1304         cctl = txd->cctl;
1305
1306         /* Find maximum width of the source bus */
1307         bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true);
1308
1309         /* Find maximum width of the destination bus */
1310         bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false);
1311
1312         list_for_each_entry(dsg, &txd->dsg_list, node) {
1313                 total_bytes = 0;
1314                 cctl = txd->cctl;
1315
1316                 bd.srcbus.addr = dsg->src_addr;
1317                 bd.dstbus.addr = dsg->dst_addr;
1318                 bd.remainder = dsg->len;
1319                 bd.srcbus.buswidth = bd.srcbus.maxwidth;
1320                 bd.dstbus.buswidth = bd.dstbus.maxwidth;
1321
1322                 pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl);
1323
1324                 dev_vdbg(&pl08x->adev->dev,
1325                         "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
1326                         (u64)bd.srcbus.addr,
1327                         cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
1328                         bd.srcbus.buswidth,
1329                         (u64)bd.dstbus.addr,
1330                         cctl & PL080_CONTROL_DST_INCR ? "+" : "",
1331                         bd.dstbus.buswidth,
1332                         bd.remainder);
1333                 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
1334                         mbus == &bd.srcbus ? "src" : "dst",
1335                         sbus == &bd.srcbus ? "src" : "dst");
1336
1337                 /*
1338                  * Zero length is only allowed if all these requirements are
1339                  * met:
1340                  * - flow controller is peripheral.
1341                  * - src.addr is aligned to src.width
1342                  * - dst.addr is aligned to dst.width
1343                  *
1344                  * sg_len == 1 should be true, as there can be two cases here:
1345                  *
1346                  * - Memory addresses are contiguous and are not scattered.
1347                  *   Here, Only one sg will be passed by user driver, with
1348                  *   memory address and zero length. We pass this to controller
1349                  *   and after the transfer it will receive the last burst
1350                  *   request from peripheral and so transfer finishes.
1351                  *
1352                  * - Memory addresses are scattered and are not contiguous.
1353                  *   Here, Obviously as DMA controller doesn't know when a lli's
1354                  *   transfer gets over, it can't load next lli. So in this
1355                  *   case, there has to be an assumption that only one lli is
1356                  *   supported. Thus, we can't have scattered addresses.
1357                  */
1358                 if (!bd.remainder) {
1359                         u32 fc;
1360
1361                         /* FTDMAC020 only does memory-to-memory */
1362                         if (pl08x->vd->ftdmac020)
1363                                 fc = PL080_FLOW_MEM2MEM;
1364                         else
1365                                 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
1366                                         PL080_CONFIG_FLOW_CONTROL_SHIFT;
1367                         if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
1368                                         (fc <= PL080_FLOW_SRC2DST_SRC))) {
1369                                 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
1370                                         __func__);
1371                                 return 0;
1372                         }
1373
1374                         if (!IS_BUS_ALIGNED(&bd.srcbus) ||
1375                                 !IS_BUS_ALIGNED(&bd.dstbus)) {
1376                                 dev_err(&pl08x->adev->dev,
1377                                         "%s src & dst address must be aligned to src"
1378                                         " & dst width if peripheral is flow controller",
1379                                         __func__);
1380                                 return 0;
1381                         }
1382
1383                         cctl = pl08x_lli_control_bits(pl08x, cctl,
1384                                         bd.srcbus.buswidth, bd.dstbus.buswidth,
1385                                         0);
1386                         pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1387                                         0, cctl, 0);
1388                         break;
1389                 }
1390
1391                 /*
1392                  * Send byte by byte for following cases
1393                  * - Less than a bus width available
1394                  * - until master bus is aligned
1395                  */
1396                 if (bd.remainder < mbus->buswidth)
1397                         early_bytes = bd.remainder;
1398                 else if (!IS_BUS_ALIGNED(mbus)) {
1399                         early_bytes = mbus->buswidth -
1400                                 (mbus->addr & (mbus->buswidth - 1));
1401                         if ((bd.remainder - early_bytes) < mbus->buswidth)
1402                                 early_bytes = bd.remainder;
1403                 }
1404
1405                 if (early_bytes) {
1406                         dev_vdbg(&pl08x->adev->dev,
1407                                 "%s byte width LLIs (remain 0x%08zx)\n",
1408                                 __func__, bd.remainder);
1409                         prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes,
1410                                 num_llis++, &total_bytes);
1411                 }
1412
1413                 if (bd.remainder) {
1414                         /*
1415                          * Master now aligned
1416                          * - if slave is not then we must set its width down
1417                          */
1418                         if (!IS_BUS_ALIGNED(sbus)) {
1419                                 dev_dbg(&pl08x->adev->dev,
1420                                         "%s set down bus width to one byte\n",
1421                                         __func__);
1422
1423                                 sbus->buswidth = 1;
1424                         }
1425
1426                         /*
1427                          * Bytes transferred = tsize * src width, not
1428                          * MIN(buswidths)
1429                          */
1430                         max_bytes_per_lli = bd.srcbus.buswidth *
1431                                                 pl08x->vd->max_transfer_size;
1432                         dev_vdbg(&pl08x->adev->dev,
1433                                 "%s max bytes per lli = %zu\n",
1434                                 __func__, max_bytes_per_lli);
1435
1436                         /*
1437                          * Make largest possible LLIs until less than one bus
1438                          * width left
1439                          */
1440                         while (bd.remainder > (mbus->buswidth - 1)) {
1441                                 size_t lli_len, tsize, width;
1442
1443                                 /*
1444                                  * If enough left try to send max possible,
1445                                  * otherwise try to send the remainder
1446                                  */
1447                                 lli_len = min(bd.remainder, max_bytes_per_lli);
1448
1449                                 /*
1450                                  * Check against maximum bus alignment:
1451                                  * Calculate actual transfer size in relation to
1452                                  * bus width an get a maximum remainder of the
1453                                  * highest bus width - 1
1454                                  */
1455                                 width = max(mbus->buswidth, sbus->buswidth);
1456                                 lli_len = (lli_len / width) * width;
1457                                 tsize = lli_len / bd.srcbus.buswidth;
1458
1459                                 dev_vdbg(&pl08x->adev->dev,
1460                                         "%s fill lli with single lli chunk of "
1461                                         "size 0x%08zx (remainder 0x%08zx)\n",
1462                                         __func__, lli_len, bd.remainder);
1463
1464                                 cctl = pl08x_lli_control_bits(pl08x, cctl,
1465                                         bd.srcbus.buswidth, bd.dstbus.buswidth,
1466                                         tsize);
1467                                 pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1468                                                 lli_len, cctl, tsize);
1469                                 total_bytes += lli_len;
1470                         }
1471
1472                         /*
1473                          * Send any odd bytes
1474                          */
1475                         if (bd.remainder) {
1476                                 dev_vdbg(&pl08x->adev->dev,
1477                                         "%s align with boundary, send odd bytes (remain %zu)\n",
1478                                         __func__, bd.remainder);
1479                                 prep_byte_width_lli(pl08x, &bd, &cctl,
1480                                         bd.remainder, num_llis++, &total_bytes);
1481                         }
1482                 }
1483
1484                 if (total_bytes != dsg->len) {
1485                         dev_err(&pl08x->adev->dev,
1486                                 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
1487                                 __func__, total_bytes, dsg->len);
1488                         return 0;
1489                 }
1490
1491                 if (num_llis >= MAX_NUM_TSFR_LLIS) {
1492                         dev_err(&pl08x->adev->dev,
1493                                 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
1494                                 __func__, MAX_NUM_TSFR_LLIS);
1495                         return 0;
1496                 }
1497         }
1498
1499         llis_va = txd->llis_va;
1500         last_lli = llis_va + (num_llis - 1) * pl08x->lli_words;
1501
1502         if (txd->cyclic) {
1503                 /* Link back to the first LLI. */
1504                 last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus;
1505         } else {
1506                 /* The final LLI terminates the LLI. */
1507                 last_lli[PL080_LLI_LLI] = 0;
1508                 /* The final LLI element shall also fire an interrupt. */
1509                 if (pl08x->vd->ftdmac020)
1510                         last_lli[PL080_LLI_CCTL] &= ~FTDMAC020_LLI_TC_MSK;
1511                 else
1512                         last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN;
1513         }
1514
1515         pl08x_dump_lli(pl08x, llis_va, num_llis);
1516
1517         return num_llis;
1518 }
1519
1520 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
1521                            struct pl08x_txd *txd)
1522 {
1523         struct pl08x_sg *dsg, *_dsg;
1524
1525         if (txd->llis_va)
1526                 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
1527
1528         list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
1529                 list_del(&dsg->node);
1530                 kfree(dsg);
1531         }
1532
1533         kfree(txd);
1534 }
1535
1536 static void pl08x_desc_free(struct virt_dma_desc *vd)
1537 {
1538         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1539         struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
1540
1541         dma_descriptor_unmap(&vd->tx);
1542         if (!txd->done)
1543                 pl08x_release_mux(plchan);
1544
1545         pl08x_free_txd(plchan->host, txd);
1546 }
1547
1548 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1549                                 struct pl08x_dma_chan *plchan)
1550 {
1551         LIST_HEAD(head);
1552
1553         vchan_get_all_descriptors(&plchan->vc, &head);
1554         vchan_dma_desc_free_list(&plchan->vc, &head);
1555 }
1556
1557 /*
1558  * The DMA ENGINE API
1559  */
1560 static void pl08x_free_chan_resources(struct dma_chan *chan)
1561 {
1562         /* Ensure all queued descriptors are freed */
1563         vchan_free_chan_resources(to_virt_chan(chan));
1564 }
1565
1566 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1567                 struct dma_chan *chan, unsigned long flags)
1568 {
1569         struct dma_async_tx_descriptor *retval = NULL;
1570
1571         return retval;
1572 }
1573
1574 /*
1575  * Code accessing dma_async_is_complete() in a tight loop may give problems.
1576  * If slaves are relying on interrupts to signal completion this function
1577  * must not be called with interrupts disabled.
1578  */
1579 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
1580                 dma_cookie_t cookie, struct dma_tx_state *txstate)
1581 {
1582         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1583         struct virt_dma_desc *vd;
1584         unsigned long flags;
1585         enum dma_status ret;
1586         size_t bytes = 0;
1587
1588         ret = dma_cookie_status(chan, cookie, txstate);
1589         if (ret == DMA_COMPLETE)
1590                 return ret;
1591
1592         /*
1593          * There's no point calculating the residue if there's
1594          * no txstate to store the value.
1595          */
1596         if (!txstate) {
1597                 if (plchan->state == PL08X_CHAN_PAUSED)
1598                         ret = DMA_PAUSED;
1599                 return ret;
1600         }
1601
1602         spin_lock_irqsave(&plchan->vc.lock, flags);
1603         ret = dma_cookie_status(chan, cookie, txstate);
1604         if (ret != DMA_COMPLETE) {
1605                 vd = vchan_find_desc(&plchan->vc, cookie);
1606                 if (vd) {
1607                         /* On the issued list, so hasn't been processed yet */
1608                         struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
1609                         struct pl08x_sg *dsg;
1610
1611                         list_for_each_entry(dsg, &txd->dsg_list, node)
1612                                 bytes += dsg->len;
1613                 } else {
1614                         bytes = pl08x_getbytes_chan(plchan);
1615                 }
1616         }
1617         spin_unlock_irqrestore(&plchan->vc.lock, flags);
1618
1619         /*
1620          * This cookie not complete yet
1621          * Get number of bytes left in the active transactions and queue
1622          */
1623         dma_set_residue(txstate, bytes);
1624
1625         if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
1626                 ret = DMA_PAUSED;
1627
1628         /* Whether waiting or running, we're in progress */
1629         return ret;
1630 }
1631
1632 /* PrimeCell DMA extension */
1633 struct burst_table {
1634         u32 burstwords;
1635         u32 reg;
1636 };
1637
1638 static const struct burst_table burst_sizes[] = {
1639         {
1640                 .burstwords = 256,
1641                 .reg = PL080_BSIZE_256,
1642         },
1643         {
1644                 .burstwords = 128,
1645                 .reg = PL080_BSIZE_128,
1646         },
1647         {
1648                 .burstwords = 64,
1649                 .reg = PL080_BSIZE_64,
1650         },
1651         {
1652                 .burstwords = 32,
1653                 .reg = PL080_BSIZE_32,
1654         },
1655         {
1656                 .burstwords = 16,
1657                 .reg = PL080_BSIZE_16,
1658         },
1659         {
1660                 .burstwords = 8,
1661                 .reg = PL080_BSIZE_8,
1662         },
1663         {
1664                 .burstwords = 4,
1665                 .reg = PL080_BSIZE_4,
1666         },
1667         {
1668                 .burstwords = 0,
1669                 .reg = PL080_BSIZE_1,
1670         },
1671 };
1672
1673 /*
1674  * Given the source and destination available bus masks, select which
1675  * will be routed to each port.  We try to have source and destination
1676  * on separate ports, but always respect the allowable settings.
1677  */
1678 static u32 pl08x_select_bus(bool ftdmac020, u8 src, u8 dst)
1679 {
1680         u32 cctl = 0;
1681         u32 dst_ahb2;
1682         u32 src_ahb2;
1683
1684         /* The FTDMAC020 use different bits to indicate src/dst bus */
1685         if (ftdmac020) {
1686                 dst_ahb2 = FTDMAC020_LLI_DST_SEL;
1687                 src_ahb2 = FTDMAC020_LLI_SRC_SEL;
1688         } else {
1689                 dst_ahb2 = PL080_CONTROL_DST_AHB2;
1690                 src_ahb2 = PL080_CONTROL_SRC_AHB2;
1691         }
1692
1693         if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1694                 cctl |= dst_ahb2;
1695         if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1696                 cctl |= src_ahb2;
1697
1698         return cctl;
1699 }
1700
1701 static u32 pl08x_cctl(u32 cctl)
1702 {
1703         cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1704                   PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1705                   PL080_CONTROL_PROT_MASK);
1706
1707         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1708         return cctl | PL080_CONTROL_PROT_SYS;
1709 }
1710
1711 static u32 pl08x_width(enum dma_slave_buswidth width)
1712 {
1713         switch (width) {
1714         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1715                 return PL080_WIDTH_8BIT;
1716         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1717                 return PL080_WIDTH_16BIT;
1718         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1719                 return PL080_WIDTH_32BIT;
1720         default:
1721                 return ~0;
1722         }
1723 }
1724
1725 static u32 pl08x_burst(u32 maxburst)
1726 {
1727         int i;
1728
1729         for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1730                 if (burst_sizes[i].burstwords <= maxburst)
1731                         break;
1732
1733         return burst_sizes[i].reg;
1734 }
1735
1736 static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
1737         enum dma_slave_buswidth addr_width, u32 maxburst)
1738 {
1739         u32 width, burst, cctl = 0;
1740
1741         width = pl08x_width(addr_width);
1742         if (width == ~0)
1743                 return ~0;
1744
1745         cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1746         cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1747
1748         /*
1749          * If this channel will only request single transfers, set this
1750          * down to ONE element.  Also select one element if no maxburst
1751          * is specified.
1752          */
1753         if (plchan->cd->single)
1754                 maxburst = 1;
1755
1756         burst = pl08x_burst(maxburst);
1757         cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1758         cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1759
1760         return pl08x_cctl(cctl);
1761 }
1762
1763 /*
1764  * Slave transactions callback to the slave device to allow
1765  * synchronization of slave DMA signals with the DMAC enable
1766  */
1767 static void pl08x_issue_pending(struct dma_chan *chan)
1768 {
1769         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1770         unsigned long flags;
1771
1772 #ifdef CONFIG_SOC_STARFIVE_JH7110
1773         plchan->chan_id = chan->chan_id;
1774 #endif
1775         spin_lock_irqsave(&plchan->vc.lock, flags);
1776         if (vchan_issue_pending(&plchan->vc)) {
1777                 if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
1778                         pl08x_phy_alloc_and_start(plchan);
1779         }
1780         spin_unlock_irqrestore(&plchan->vc.lock, flags);
1781 }
1782
1783 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1784 {
1785         struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1786
1787         if (txd)
1788                 INIT_LIST_HEAD(&txd->dsg_list);
1789         return txd;
1790 }
1791
1792 static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x)
1793 {
1794         u32 cctl = 0;
1795
1796         /* Conjure cctl */
1797         switch (pl08x->pd->memcpy_burst_size) {
1798         default:
1799                 dev_err(&pl08x->adev->dev,
1800                         "illegal burst size for memcpy, set to 1\n");
1801                 fallthrough;
1802         case PL08X_BURST_SZ_1:
1803                 cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
1804                         PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;
1805                 break;
1806         case PL08X_BURST_SZ_4:
1807                 cctl |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
1808                         PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT;
1809                 break;
1810         case PL08X_BURST_SZ_8:
1811                 cctl |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT |
1812                         PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT;
1813                 break;
1814         case PL08X_BURST_SZ_16:
1815                 cctl |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT |
1816                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT;
1817                 break;
1818         case PL08X_BURST_SZ_32:
1819                 cctl |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT |
1820                         PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT;
1821                 break;
1822         case PL08X_BURST_SZ_64:
1823                 cctl |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT |
1824                         PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT;
1825                 break;
1826         case PL08X_BURST_SZ_128:
1827                 cctl |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT |
1828                         PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT;
1829                 break;
1830         case PL08X_BURST_SZ_256:
1831                 cctl |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |
1832                         PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT;
1833                 break;
1834         }
1835
1836         switch (pl08x->pd->memcpy_bus_width) {
1837         default:
1838                 dev_err(&pl08x->adev->dev,
1839                         "illegal bus width for memcpy, set to 8 bits\n");
1840                 fallthrough;
1841         case PL08X_BUS_WIDTH_8_BITS:
1842                 cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
1843                         PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
1844                 break;
1845         case PL08X_BUS_WIDTH_16_BITS:
1846                 cctl |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT |
1847                         PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
1848                 break;
1849         case PL08X_BUS_WIDTH_32_BITS:
1850                 cctl |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
1851                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
1852                 break;
1853         }
1854
1855         /* Protection flags */
1856         if (pl08x->pd->memcpy_prot_buff)
1857                 cctl |= PL080_CONTROL_PROT_BUFF;
1858         if (pl08x->pd->memcpy_prot_cache)
1859                 cctl |= PL080_CONTROL_PROT_CACHE;
1860
1861         /* We are the kernel, so we are in privileged mode */
1862         cctl |= PL080_CONTROL_PROT_SYS;
1863
1864         /* Both to be incremented or the code will break */
1865         cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1866
1867         if (pl08x->vd->dualmaster)
1868                 cctl |= pl08x_select_bus(false,
1869                                          pl08x->mem_buses,
1870                                          pl08x->mem_buses);
1871
1872         return cctl;
1873 }
1874
1875 static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x)
1876 {
1877         u32 cctl = 0;
1878
1879         /* Conjure cctl */
1880         switch (pl08x->pd->memcpy_bus_width) {
1881         default:
1882                 dev_err(&pl08x->adev->dev,
1883                         "illegal bus width for memcpy, set to 8 bits\n");
1884                 fallthrough;
1885         case PL08X_BUS_WIDTH_8_BITS:
1886                 cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1887                         PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1888                 break;
1889         case PL08X_BUS_WIDTH_16_BITS:
1890                 cctl |= PL080_WIDTH_16BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1891                         PL080_WIDTH_16BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1892                 break;
1893         case PL08X_BUS_WIDTH_32_BITS:
1894                 cctl |= PL080_WIDTH_32BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1895                         PL080_WIDTH_32BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
1896                 break;
1897         }
1898
1899         /*
1900          * By default mask the TC IRQ on all LLIs, it will be unmasked on
1901          * the last LLI item by other code.
1902          */
1903         cctl |= FTDMAC020_LLI_TC_MSK;
1904
1905         /*
1906          * Both to be incremented so leave bits FTDMAC020_LLI_SRCAD_CTL
1907          * and FTDMAC020_LLI_DSTAD_CTL as zero
1908          */
1909         if (pl08x->vd->dualmaster)
1910                 cctl |= pl08x_select_bus(true,
1911                                          pl08x->mem_buses,
1912                                          pl08x->mem_buses);
1913
1914         return cctl;
1915 }
1916
1917 /*
1918  * Initialize a descriptor to be used by memcpy submit
1919  */
1920 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1921                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1922                 size_t len, unsigned long flags)
1923 {
1924         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1925         struct pl08x_driver_data *pl08x = plchan->host;
1926         struct pl08x_txd *txd;
1927         struct pl08x_sg *dsg;
1928         int ret;
1929
1930         txd = pl08x_get_txd(plchan);
1931         if (!txd) {
1932                 dev_err(&pl08x->adev->dev,
1933                         "%s no memory for descriptor\n", __func__);
1934                 return NULL;
1935         }
1936
1937         dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
1938         if (!dsg) {
1939                 pl08x_free_txd(pl08x, txd);
1940                 dev_err(&pl08x->adev->dev,
1941                         "%s no memory for kzalloc\n", __func__);
1942                 return NULL;
1943         }
1944         list_add_tail(&dsg->node, &txd->dsg_list);
1945
1946         dsg->src_addr = src;
1947         dsg->dst_addr = dest;
1948         dsg->len = len;
1949         if (pl08x->vd->ftdmac020) {
1950                 /* Writing CCFG zero ENABLES all interrupts */
1951                 txd->ccfg = 0;
1952                 txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x);
1953         } else {
1954                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1955                         PL080_CONFIG_TC_IRQ_MASK |
1956                         PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1957                 txd->cctl = pl08x_memcpy_cctl(pl08x);
1958         }
1959
1960         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
1961         if (!ret) {
1962                 pl08x_free_txd(pl08x, txd);
1963                 dev_err(&pl08x->adev->dev,
1964                         "%s pl08x_fill_llis_for_desc error\n", __func__);
1965                 return NULL;
1966         }
1967
1968         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
1969 }
1970
1971 static struct pl08x_txd *pl08x_init_txd(
1972                 struct dma_chan *chan,
1973                 enum dma_transfer_direction direction,
1974                 dma_addr_t *slave_addr)
1975 {
1976         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1977         struct pl08x_driver_data *pl08x = plchan->host;
1978         struct pl08x_txd *txd;
1979         enum dma_slave_buswidth addr_width;
1980         int ret, tmp;
1981         u8 src_buses, dst_buses;
1982         u32 maxburst, cctl;
1983
1984         txd = pl08x_get_txd(plchan);
1985         if (!txd) {
1986                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1987                 return NULL;
1988         }
1989
1990         /*
1991          * Set up addresses, the PrimeCell configured address
1992          * will take precedence since this may configure the
1993          * channel target address dynamically at runtime.
1994          */
1995         if (direction == DMA_MEM_TO_DEV) {
1996                 cctl = PL080_CONTROL_SRC_INCR;
1997                 *slave_addr = plchan->cfg.dst_addr;
1998                 addr_width = plchan->cfg.dst_addr_width;
1999                 maxburst = plchan->cfg.dst_maxburst;
2000                 src_buses = pl08x->mem_buses;
2001                 dst_buses = plchan->cd->periph_buses;
2002         } else if (direction == DMA_DEV_TO_MEM) {
2003                 cctl = PL080_CONTROL_DST_INCR;
2004                 *slave_addr = plchan->cfg.src_addr;
2005                 addr_width = plchan->cfg.src_addr_width;
2006                 maxburst = plchan->cfg.src_maxburst;
2007                 src_buses = plchan->cd->periph_buses;
2008                 dst_buses = pl08x->mem_buses;
2009         } else {
2010                 pl08x_free_txd(pl08x, txd);
2011                 dev_err(&pl08x->adev->dev,
2012                         "%s direction unsupported\n", __func__);
2013                 return NULL;
2014         }
2015
2016         cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
2017         if (cctl == ~0) {
2018                 pl08x_free_txd(pl08x, txd);
2019                 dev_err(&pl08x->adev->dev,
2020                         "DMA slave configuration botched?\n");
2021                 return NULL;
2022         }
2023
2024         txd->cctl = cctl | pl08x_select_bus(false, src_buses, dst_buses);
2025
2026         if (plchan->cfg.device_fc)
2027                 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
2028                         PL080_FLOW_PER2MEM_PER;
2029         else
2030                 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
2031                         PL080_FLOW_PER2MEM;
2032
2033         txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
2034                 PL080_CONFIG_TC_IRQ_MASK |
2035                 tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
2036
2037         ret = pl08x_request_mux(plchan);
2038         if (ret < 0) {
2039                 pl08x_free_txd(pl08x, txd);
2040                 dev_dbg(&pl08x->adev->dev,
2041                         "unable to mux for transfer on %s due to platform restrictions\n",
2042                         plchan->name);
2043                 return NULL;
2044         }
2045
2046         dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
2047                  plchan->signal, plchan->name);
2048
2049         /* Assign the flow control signal to this channel */
2050         if (direction == DMA_MEM_TO_DEV)
2051                 txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT;
2052         else
2053                 txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
2054
2055         return txd;
2056 }
2057
2058 static int pl08x_tx_add_sg(struct pl08x_txd *txd,
2059                            enum dma_transfer_direction direction,
2060                            dma_addr_t slave_addr,
2061                            dma_addr_t buf_addr,
2062                            unsigned int len)
2063 {
2064         struct pl08x_sg *dsg;
2065
2066         dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
2067         if (!dsg)
2068                 return -ENOMEM;
2069
2070         list_add_tail(&dsg->node, &txd->dsg_list);
2071
2072         dsg->len = len;
2073         if (direction == DMA_MEM_TO_DEV) {
2074                 dsg->src_addr = buf_addr;
2075                 dsg->dst_addr = slave_addr;
2076         } else {
2077                 dsg->src_addr = slave_addr;
2078                 dsg->dst_addr = buf_addr;
2079         }
2080
2081         return 0;
2082 }
2083
2084 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
2085                 struct dma_chan *chan, struct scatterlist *sgl,
2086                 unsigned int sg_len, enum dma_transfer_direction direction,
2087                 unsigned long flags, void *context)
2088 {
2089         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2090         struct pl08x_driver_data *pl08x = plchan->host;
2091         struct pl08x_txd *txd;
2092         struct scatterlist *sg;
2093         int ret, tmp;
2094         dma_addr_t slave_addr;
2095
2096         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
2097                         __func__, sg_dma_len(sgl), plchan->name);
2098
2099         txd = pl08x_init_txd(chan, direction, &slave_addr);
2100         if (!txd)
2101                 return NULL;
2102
2103         for_each_sg(sgl, sg, sg_len, tmp) {
2104                 ret = pl08x_tx_add_sg(txd, direction, slave_addr,
2105                                       sg_dma_address(sg),
2106                                       sg_dma_len(sg));
2107                 if (ret) {
2108                         pl08x_release_mux(plchan);
2109                         pl08x_free_txd(pl08x, txd);
2110                         dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
2111                                         __func__);
2112                         return NULL;
2113                 }
2114         }
2115
2116         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
2117         if (!ret) {
2118                 pl08x_release_mux(plchan);
2119                 pl08x_free_txd(pl08x, txd);
2120                 return NULL;
2121         }
2122
2123         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
2124 }
2125
2126 static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
2127                 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
2128                 size_t period_len, enum dma_transfer_direction direction,
2129                 unsigned long flags)
2130 {
2131         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2132         struct pl08x_driver_data *pl08x = plchan->host;
2133         struct pl08x_txd *txd;
2134         int ret, tmp;
2135         dma_addr_t slave_addr;
2136
2137         dev_dbg(&pl08x->adev->dev,
2138                 "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n",
2139                 __func__, period_len, buf_len,
2140                 direction == DMA_MEM_TO_DEV ? "to" : "from",
2141                 plchan->name);
2142
2143         txd = pl08x_init_txd(chan, direction, &slave_addr);
2144         if (!txd)
2145                 return NULL;
2146
2147         txd->cyclic = true;
2148         txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
2149         for (tmp = 0; tmp < buf_len; tmp += period_len) {
2150                 ret = pl08x_tx_add_sg(txd, direction, slave_addr,
2151                                       buf_addr + tmp, period_len);
2152                 if (ret) {
2153                         pl08x_release_mux(plchan);
2154                         pl08x_free_txd(pl08x, txd);
2155                         return NULL;
2156                 }
2157         }
2158
2159         ret = pl08x_fill_llis_for_desc(plchan->host, txd);
2160         if (!ret) {
2161                 pl08x_release_mux(plchan);
2162                 pl08x_free_txd(pl08x, txd);
2163                 return NULL;
2164         }
2165
2166         return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
2167 }
2168
2169 static int pl08x_config(struct dma_chan *chan,
2170                         struct dma_slave_config *config)
2171 {
2172         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2173         struct pl08x_driver_data *pl08x = plchan->host;
2174
2175         if (!plchan->slave)
2176                 return -EINVAL;
2177
2178         /* Reject definitely invalid configurations */
2179         if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
2180             config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
2181                 return -EINVAL;
2182
2183         if (config->device_fc && pl08x->vd->pl080s) {
2184                 dev_err(&pl08x->adev->dev,
2185                         "%s: PL080S does not support peripheral flow control\n",
2186                         __func__);
2187                 return -EINVAL;
2188         }
2189
2190         plchan->cfg = *config;
2191
2192         return 0;
2193 }
2194
2195 static int pl08x_terminate_all(struct dma_chan *chan)
2196 {
2197         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2198         struct pl08x_driver_data *pl08x = plchan->host;
2199         unsigned long flags;
2200
2201         spin_lock_irqsave(&plchan->vc.lock, flags);
2202         if (!plchan->phychan && !plchan->at) {
2203                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2204                 return 0;
2205         }
2206
2207         plchan->state = PL08X_CHAN_IDLE;
2208
2209         if (plchan->phychan) {
2210                 /*
2211                  * Mark physical channel as free and free any slave
2212                  * signal
2213                  */
2214                 pl08x_phy_free(plchan);
2215         }
2216         /* Dequeue jobs and free LLIs */
2217         if (plchan->at) {
2218                 vchan_terminate_vdesc(&plchan->at->vd);
2219                 plchan->at = NULL;
2220         }
2221         /* Dequeue jobs not yet fired as well */
2222         pl08x_free_txd_list(pl08x, plchan);
2223
2224         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2225
2226         return 0;
2227 }
2228
2229 static void pl08x_synchronize(struct dma_chan *chan)
2230 {
2231         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2232
2233         vchan_synchronize(&plchan->vc);
2234 }
2235
2236 static int pl08x_pause(struct dma_chan *chan)
2237 {
2238         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2239         unsigned long flags;
2240
2241         /*
2242          * Anything succeeds on channels with no physical allocation and
2243          * no queued transfers.
2244          */
2245         spin_lock_irqsave(&plchan->vc.lock, flags);
2246         if (!plchan->phychan && !plchan->at) {
2247                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2248                 return 0;
2249         }
2250
2251         pl08x_pause_phy_chan(plchan->phychan);
2252         plchan->state = PL08X_CHAN_PAUSED;
2253
2254         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2255
2256         return 0;
2257 }
2258
2259 static int pl08x_resume(struct dma_chan *chan)
2260 {
2261         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2262         unsigned long flags;
2263
2264         /*
2265          * Anything succeeds on channels with no physical allocation and
2266          * no queued transfers.
2267          */
2268         spin_lock_irqsave(&plchan->vc.lock, flags);
2269         if (!plchan->phychan && !plchan->at) {
2270                 spin_unlock_irqrestore(&plchan->vc.lock, flags);
2271                 return 0;
2272         }
2273
2274         pl08x_resume_phy_chan(plchan->phychan);
2275         plchan->state = PL08X_CHAN_RUNNING;
2276
2277         spin_unlock_irqrestore(&plchan->vc.lock, flags);
2278
2279         return 0;
2280 }
2281
2282 #ifndef CONFIG_SOC_STARFIVE_JH7110
2283 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
2284 {
2285         struct pl08x_dma_chan *plchan;
2286         char *name = chan_id;
2287
2288         /* Reject channels for devices not bound to this driver */
2289         if (chan->device->dev->driver != &pl08x_amba_driver.drv)
2290                 return false;
2291
2292         plchan = to_pl08x_chan(chan);
2293
2294         /* Check that the channel is not taken! */
2295         if (!strcmp(plchan->name, name))
2296                 return true;
2297
2298         return false;
2299 }
2300 EXPORT_SYMBOL_GPL(pl08x_filter_id);
2301 #endif
2302
2303 static bool pl08x_filter_fn(struct dma_chan *chan, void *chan_id)
2304 {
2305         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
2306
2307         return plchan->cd == chan_id;
2308 }
2309
2310 /*
2311  * Just check that the device is there and active
2312  * TODO: turn this bit on/off depending on the number of physical channels
2313  * actually used, if it is zero... well shut it off. That will save some
2314  * power. Cut the clock at the same time.
2315  */
2316 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
2317 {
2318         /* The Nomadik variant does not have the config register */
2319         if (pl08x->vd->nomadik)
2320                 return;
2321         /* The FTDMAC020 variant does this in another register */
2322         if (pl08x->vd->ftdmac020) {
2323                 writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
2324                 return;
2325         }
2326         writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
2327 }
2328
2329 static irqreturn_t pl08x_irq(int irq, void *dev)
2330 {
2331         struct pl08x_driver_data *pl08x = dev;
2332         u32 mask = 0, err, tc, i;
2333
2334         /* check & clear - ERR & TC interrupts */
2335         err = readl(pl08x->base + PL080_ERR_STATUS);
2336         if (err) {
2337                 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
2338                         __func__, err);
2339                 writel(err, pl08x->base + PL080_ERR_CLEAR);
2340         }
2341         tc = readl(pl08x->base + PL080_TC_STATUS);
2342         if (tc)
2343                 writel(tc, pl08x->base + PL080_TC_CLEAR);
2344
2345         if (!err && !tc)
2346                 return IRQ_NONE;
2347
2348         for (i = 0; i < pl08x->vd->channels; i++) {
2349                 if ((BIT(i) & err) || (BIT(i) & tc)) {
2350                         /* Locate physical channel */
2351                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
2352                         struct pl08x_dma_chan *plchan = phychan->serving;
2353                         struct pl08x_txd *tx;
2354
2355                         if (!plchan) {
2356                                 dev_err(&pl08x->adev->dev,
2357                                         "%s Error TC interrupt on unused channel: 0x%08x\n",
2358                                         __func__, i);
2359                                 continue;
2360                         }
2361
2362                         spin_lock(&plchan->vc.lock);
2363                         tx = plchan->at;
2364                         if (tx && tx->cyclic) {
2365                                 vchan_cyclic_callback(&tx->vd);
2366                         } else if (tx) {
2367                                 plchan->at = NULL;
2368                                 /*
2369                                  * This descriptor is done, release its mux
2370                                  * reservation.
2371                                  */
2372                                 pl08x_release_mux(plchan);
2373                                 tx->done = true;
2374                                 vchan_cookie_complete(&tx->vd);
2375
2376                                 /*
2377                                  * And start the next descriptor (if any),
2378                                  * otherwise free this channel.
2379                                  */
2380                                 if (vchan_next_desc(&plchan->vc))
2381                                         pl08x_start_next_txd(plchan);
2382                                 else
2383                                         pl08x_phy_free(plchan);
2384                         }
2385                         spin_unlock(&plchan->vc.lock);
2386
2387                         mask |= BIT(i);
2388                 }
2389         }
2390
2391         return mask ? IRQ_HANDLED : IRQ_NONE;
2392 }
2393
2394 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
2395 {
2396         chan->slave = true;
2397         chan->name = chan->cd->bus_id;
2398         chan->cfg.src_addr = chan->cd->addr;
2399         chan->cfg.dst_addr = chan->cd->addr;
2400 }
2401
2402 /*
2403  * Initialise the DMAC memcpy/slave channels.
2404  * Make a local wrapper to hold required data
2405  */
2406 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
2407                 struct dma_device *dmadev, unsigned int channels, bool slave)
2408 {
2409         struct pl08x_dma_chan *chan;
2410         int i;
2411
2412         INIT_LIST_HEAD(&dmadev->channels);
2413
2414         /*
2415          * Register as many many memcpy as we have physical channels,
2416          * we won't always be able to use all but the code will have
2417          * to cope with that situation.
2418          */
2419         for (i = 0; i < channels; i++) {
2420                 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
2421                 if (!chan)
2422                         return -ENOMEM;
2423
2424                 chan->host = pl08x;
2425                 chan->state = PL08X_CHAN_IDLE;
2426                 chan->signal = -1;
2427
2428                 if (slave) {
2429                         chan->cd = &pl08x->pd->slave_channels[i];
2430                         /*
2431                          * Some implementations have muxed signals, whereas some
2432                          * use a mux in front of the signals and need dynamic
2433                          * assignment of signals.
2434                          */
2435                         chan->signal = i;
2436                         pl08x_dma_slave_init(chan);
2437                 } else {
2438                         chan->cd = kzalloc(sizeof(*chan->cd), GFP_KERNEL);
2439                         if (!chan->cd) {
2440                                 kfree(chan);
2441                                 return -ENOMEM;
2442                         }
2443                         chan->cd->bus_id = "memcpy";
2444                         chan->cd->periph_buses = pl08x->pd->mem_buses;
2445                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
2446                         if (!chan->name) {
2447                                 kfree(chan->cd);
2448                                 kfree(chan);
2449                                 return -ENOMEM;
2450                         }
2451                 }
2452                 dev_dbg(&pl08x->adev->dev,
2453                          "initialize virtual channel \"%s\"\n",
2454                          chan->name);
2455
2456                 chan->vc.desc_free = pl08x_desc_free;
2457                 vchan_init(&chan->vc, dmadev);
2458         }
2459         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
2460                  i, slave ? "slave" : "memcpy");
2461         return i;
2462 }
2463
2464 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
2465 {
2466         struct pl08x_dma_chan *chan = NULL;
2467         struct pl08x_dma_chan *next;
2468
2469         list_for_each_entry_safe(chan,
2470                                  next, &dmadev->channels, vc.chan.device_node) {
2471                 list_del(&chan->vc.chan.device_node);
2472                 kfree(chan);
2473         }
2474 }
2475
2476 #ifdef CONFIG_DEBUG_FS
2477 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
2478 {
2479         switch (state) {
2480         case PL08X_CHAN_IDLE:
2481                 return "idle";
2482         case PL08X_CHAN_RUNNING:
2483                 return "running";
2484         case PL08X_CHAN_PAUSED:
2485                 return "paused";
2486         case PL08X_CHAN_WAITING:
2487                 return "waiting";
2488         default:
2489                 break;
2490         }
2491         return "UNKNOWN STATE";
2492 }
2493
2494 static int pl08x_debugfs_show(struct seq_file *s, void *data)
2495 {
2496         struct pl08x_driver_data *pl08x = s->private;
2497         struct pl08x_dma_chan *chan;
2498         struct pl08x_phy_chan *ch;
2499         unsigned long flags;
2500         int i;
2501
2502         seq_printf(s, "PL08x physical channels:\n");
2503         seq_printf(s, "CHANNEL:\tUSER:\n");
2504         seq_printf(s, "--------\t-----\n");
2505         for (i = 0; i < pl08x->vd->channels; i++) {
2506                 struct pl08x_dma_chan *virt_chan;
2507
2508                 ch = &pl08x->phy_chans[i];
2509
2510                 spin_lock_irqsave(&ch->lock, flags);
2511                 virt_chan = ch->serving;
2512
2513                 seq_printf(s, "%d\t\t%s%s\n",
2514                            ch->id,
2515                            virt_chan ? virt_chan->name : "(none)",
2516                            ch->locked ? " LOCKED" : "");
2517
2518                 spin_unlock_irqrestore(&ch->lock, flags);
2519         }
2520
2521         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
2522         seq_printf(s, "CHANNEL:\tSTATE:\n");
2523         seq_printf(s, "--------\t------\n");
2524         list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
2525                 seq_printf(s, "%s\t\t%s\n", chan->name,
2526                            pl08x_state_str(chan->state));
2527         }
2528
2529         if (pl08x->has_slave) {
2530                 seq_printf(s, "\nPL08x virtual slave channels:\n");
2531                 seq_printf(s, "CHANNEL:\tSTATE:\n");
2532                 seq_printf(s, "--------\t------\n");
2533                 list_for_each_entry(chan, &pl08x->slave.channels,
2534                                     vc.chan.device_node) {
2535                         seq_printf(s, "%s\t\t%s\n", chan->name,
2536                                    pl08x_state_str(chan->state));
2537                 }
2538         }
2539
2540         return 0;
2541 }
2542
2543 DEFINE_SHOW_ATTRIBUTE(pl08x_debugfs);
2544
2545 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2546 {
2547         /* Expose a simple debugfs interface to view all clocks */
2548         debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
2549                             NULL, pl08x, &pl08x_debugfs_fops);
2550 }
2551
2552 #else
2553 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2554 {
2555 }
2556 #endif
2557
2558 #ifdef CONFIG_OF
2559 static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x,
2560                                          u32 id)
2561 {
2562         struct pl08x_dma_chan *chan;
2563
2564         /* Trying to get a slave channel from something with no slave support */
2565         if (!pl08x->has_slave)
2566                 return NULL;
2567
2568         list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
2569                 if (chan->signal == id)
2570                         return &chan->vc.chan;
2571         }
2572
2573         return NULL;
2574 }
2575
2576 static struct dma_chan *pl08x_of_xlate(struct of_phandle_args *dma_spec,
2577                                        struct of_dma *ofdma)
2578 {
2579         struct pl08x_driver_data *pl08x = ofdma->of_dma_data;
2580         struct dma_chan *dma_chan;
2581         struct pl08x_dma_chan *plchan;
2582
2583         if (!pl08x)
2584                 return NULL;
2585
2586         if (dma_spec->args_count != 2) {
2587                 dev_err(&pl08x->adev->dev,
2588                         "DMA channel translation requires two cells\n");
2589                 return NULL;
2590         }
2591
2592         dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);
2593         if (!dma_chan) {
2594                 dev_err(&pl08x->adev->dev,
2595                         "DMA slave channel not found\n");
2596                 return NULL;
2597         }
2598
2599         plchan = to_pl08x_chan(dma_chan);
2600         dev_dbg(&pl08x->adev->dev,
2601                 "translated channel for signal %d\n",
2602                 dma_spec->args[0]);
2603
2604         /* Augment channel data for applicable AHB buses */
2605         plchan->cd->periph_buses = dma_spec->args[1];
2606         return dma_get_slave_channel(dma_chan);
2607 }
2608
2609 #ifdef CONFIG_SOC_STARFIVE_JH7110
2610 static int pl08x_of_probe(struct platform_device *adev,
2611 #else
2612 static int pl08x_of_probe(struct amba_device *adev,
2613 #endif
2614                           struct pl08x_driver_data *pl08x,
2615                           struct device_node *np)
2616 {
2617         struct pl08x_platform_data *pd;
2618         struct pl08x_channel_data *chanp = NULL;
2619         u32 val;
2620         int ret;
2621         int i;
2622
2623         pd = devm_kzalloc(&adev->dev, sizeof(*pd), GFP_KERNEL);
2624         if (!pd)
2625                 return -ENOMEM;
2626
2627         /* Eligible bus masters for fetching LLIs */
2628         if (of_property_read_bool(np, "lli-bus-interface-ahb1"))
2629                 pd->lli_buses |= PL08X_AHB1;
2630         if (of_property_read_bool(np, "lli-bus-interface-ahb2"))
2631                 pd->lli_buses |= PL08X_AHB2;
2632         if (!pd->lli_buses) {
2633                 dev_info(&adev->dev, "no bus masters for LLIs stated, assume all\n");
2634                 pd->lli_buses |= PL08X_AHB1 | PL08X_AHB2;
2635         }
2636
2637         /* Eligible bus masters for memory access */
2638         if (of_property_read_bool(np, "mem-bus-interface-ahb1"))
2639                 pd->mem_buses |= PL08X_AHB1;
2640         if (of_property_read_bool(np, "mem-bus-interface-ahb2"))
2641                 pd->mem_buses |= PL08X_AHB2;
2642         if (!pd->mem_buses) {
2643                 dev_info(&adev->dev, "no bus masters for memory stated, assume all\n");
2644                 pd->mem_buses |= PL08X_AHB1 | PL08X_AHB2;
2645         }
2646
2647         /* Parse the memcpy channel properties */
2648         ret = of_property_read_u32(np, "memcpy-burst-size", &val);
2649         if (ret) {
2650                 dev_info(&adev->dev, "no memcpy burst size specified, using 1 byte\n");
2651                 val = 1;
2652         }
2653         switch (val) {
2654         default:
2655                 dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");
2656                 fallthrough;
2657         case 1:
2658                 pd->memcpy_burst_size = PL08X_BURST_SZ_1;
2659                 break;
2660         case 4:
2661                 pd->memcpy_burst_size = PL08X_BURST_SZ_4;
2662                 break;
2663         case 8:
2664                 pd->memcpy_burst_size = PL08X_BURST_SZ_8;
2665                 break;
2666         case 16:
2667                 pd->memcpy_burst_size = PL08X_BURST_SZ_16;
2668                 break;
2669         case 32:
2670                 pd->memcpy_burst_size = PL08X_BURST_SZ_32;
2671                 break;
2672         case 64:
2673                 pd->memcpy_burst_size = PL08X_BURST_SZ_64;
2674                 break;
2675         case 128:
2676                 pd->memcpy_burst_size = PL08X_BURST_SZ_128;
2677                 break;
2678         case 256:
2679                 pd->memcpy_burst_size = PL08X_BURST_SZ_256;
2680                 break;
2681         }
2682
2683         ret = of_property_read_u32(np, "memcpy-bus-width", &val);
2684         if (ret) {
2685                 dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n");
2686                 val = 8;
2687         }
2688         switch (val) {
2689         default:
2690                 dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");
2691                 fallthrough;
2692         case 8:
2693                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS;
2694                 break;
2695         case 16:
2696                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_16_BITS;
2697                 break;
2698         case 32:
2699                 pd->memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS;
2700                 break;
2701         }
2702
2703         /*
2704          * Allocate channel data for all possible slave channels (one
2705          * for each possible signal), channels will then be allocated
2706          * for a device and have it's AHB interfaces set up at
2707          * translation time.
2708          */
2709         if (pl08x->vd->signals) {
2710                 chanp = devm_kcalloc(&adev->dev,
2711                                      pl08x->vd->signals,
2712                                      sizeof(struct pl08x_channel_data),
2713                                      GFP_KERNEL);
2714                 if (!chanp)
2715                         return -ENOMEM;
2716
2717                 pd->slave_channels = chanp;
2718                 for (i = 0; i < pl08x->vd->signals; i++) {
2719                         /*
2720                          * chanp->periph_buses will be assigned at translation
2721                          */
2722                         chanp->bus_id = kasprintf(GFP_KERNEL, "slave%d", i);
2723                         chanp++;
2724                 }
2725                 pd->num_slave_channels = pl08x->vd->signals;
2726         }
2727
2728         pl08x->pd = pd;
2729
2730         return of_dma_controller_register(adev->dev.of_node, pl08x_of_xlate,
2731                                           pl08x);
2732 }
2733 #else
2734 #ifdef CONFIG_SOC_STARFIVE_JH7110
2735 static inline int pl08x_of_probe(struct platform_device *adev,
2736 #else
2737 static inline int pl08x_of_probe(struct amba_device *adev,
2738 #endif
2739                                  struct pl08x_driver_data *pl08x,
2740                                  struct device_node *np)
2741 {
2742         return -EINVAL;
2743 }
2744 #endif
2745
2746 #ifdef CONFIG_SOC_STARFIVE_JH7110
2747 static int pl08x_probe(struct platform_device *adev) //, const struct amba_id *id)
2748 #else
2749 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
2750 #endif
2751 {
2752         struct pl08x_driver_data *pl08x;
2753         struct device_node *np = adev->dev.of_node;
2754         u32 tsfr_size;
2755 #ifdef CONFIG_SOC_STARFIVE_JH7110
2756         struct vendor_data *vd;
2757         struct resource *res;
2758         int irq, ret = 0;
2759 #else
2760         struct vendor_data *vd = id->data;
2761         int ret = 0;
2762 #endif
2763         int i;
2764
2765 #ifndef CONFIG_SOC_STARFIVE_JH7110
2766         ret = amba_request_regions(adev, NULL);
2767         if (ret)
2768                 return ret;
2769
2770 #endif
2771         /* Ensure that we can do DMA */
2772         ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2773 #ifdef CONFIG_SOC_STARFIVE_JH7110
2774         if (ret)
2775                 return ret;
2776 #else
2777         if (ret)
2778                 goto out_no_pl08x;
2779 #endif
2780
2781         /* Create the driver state holder */
2782         pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
2783         if (!pl08x) {
2784                 ret = -ENOMEM;
2785 #ifdef CONFIG_SOC_STARFIVE_JH7110
2786                 return ret;
2787 #else
2788                 goto out_no_pl08x;
2789 #endif
2790         }
2791
2792         /* Assign useful pointers to the driver state */
2793         pl08x->adev = adev;
2794 #ifdef CONFIG_SOC_STARFIVE_JH7110
2795         vd = (struct vendor_data *)of_device_get_match_data(&adev->dev);
2796         if(!vd)
2797                 return -ENODEV;
2798 #endif
2799         pl08x->vd = vd;
2800
2801 #ifdef CONFIG_SOC_STARFIVE_JH7110
2802         res = platform_get_resource_byname(adev, IORESOURCE_MEM, "sec_dma");
2803         pl08x->base = devm_ioremap_resource(&adev->dev, res);
2804 #else
2805         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2806 #endif
2807         if (!pl08x->base) {
2808                 ret = -ENOMEM;
2809                 goto out_no_ioremap;
2810         }
2811
2812         if (vd->ftdmac020) {
2813                 u32 val;
2814
2815                 val = readl(pl08x->base + FTDMAC020_REVISION);
2816                 dev_info(&pl08x->adev->dev, "FTDMAC020 %d.%d rel %d\n",
2817                          (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
2818                 val = readl(pl08x->base + FTDMAC020_FEATURE);
2819                 dev_info(&pl08x->adev->dev, "FTDMAC020 %d channels, "
2820                          "%s built-in bridge, %s, %s linked lists\n",
2821                          (val >> 12) & 0x0f,
2822                          (val & BIT(10)) ? "no" : "has",
2823                          (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0",
2824                          (val & BIT(8)) ? "supports" : "does not support");
2825
2826                 /* Vendor data from feature register */
2827                 if (!(val & BIT(8)))
2828                         dev_warn(&pl08x->adev->dev,
2829                                  "linked lists not supported, required\n");
2830                 vd->channels = (val >> 12) & 0x0f;
2831                 vd->dualmaster = !!(val & BIT(9));
2832         }
2833
2834         /* Initialize memcpy engine */
2835         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
2836         pl08x->memcpy.dev = &adev->dev;
2837         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
2838         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
2839         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
2840         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
2841         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
2842         pl08x->memcpy.device_config = pl08x_config;
2843         pl08x->memcpy.device_pause = pl08x_pause;
2844         pl08x->memcpy.device_resume = pl08x_resume;
2845         pl08x->memcpy.device_terminate_all = pl08x_terminate_all;
2846         pl08x->memcpy.device_synchronize = pl08x_synchronize;
2847         pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2848         pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2849         pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM);
2850         pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2851         if (vd->ftdmac020)
2852                 pl08x->memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2853
2854
2855         /*
2856          * Initialize slave engine, if the block has no signals, that means
2857          * we have no slave support.
2858          */
2859         if (vd->signals) {
2860                 pl08x->has_slave = true;
2861                 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
2862                 dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
2863                 pl08x->slave.dev = &adev->dev;
2864                 pl08x->slave.device_free_chan_resources =
2865                         pl08x_free_chan_resources;
2866                 pl08x->slave.device_prep_dma_interrupt =
2867                         pl08x_prep_dma_interrupt;
2868                 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
2869                 pl08x->slave.device_issue_pending = pl08x_issue_pending;
2870                 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
2871                 pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
2872                 pl08x->slave.device_config = pl08x_config;
2873                 pl08x->slave.device_pause = pl08x_pause;
2874                 pl08x->slave.device_resume = pl08x_resume;
2875                 pl08x->slave.device_terminate_all = pl08x_terminate_all;
2876                 pl08x->slave.device_synchronize = pl08x_synchronize;
2877                 pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2878                 pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2879                 pl08x->slave.directions =
2880                         BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2881                 pl08x->slave.residue_granularity =
2882                         DMA_RESIDUE_GRANULARITY_SEGMENT;
2883         }
2884
2885         /* Get the platform data */
2886         pl08x->pd = dev_get_platdata(&adev->dev);
2887         if (!pl08x->pd) {
2888                 if (np) {
2889                         ret = pl08x_of_probe(adev, pl08x, np);
2890                         if (ret)
2891                                 goto out_no_platdata;
2892                 } else {
2893                         dev_err(&adev->dev, "no platform data supplied\n");
2894                         ret = -EINVAL;
2895                         goto out_no_platdata;
2896                 }
2897         } else {
2898                 pl08x->slave.filter.map = pl08x->pd->slave_map;
2899                 pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len;
2900                 pl08x->slave.filter.fn = pl08x_filter_fn;
2901         }
2902
2903         /* By default, AHB1 only.  If dualmaster, from platform */
2904         pl08x->lli_buses = PL08X_AHB1;
2905         pl08x->mem_buses = PL08X_AHB1;
2906         if (pl08x->vd->dualmaster) {
2907                 pl08x->lli_buses = pl08x->pd->lli_buses;
2908                 pl08x->mem_buses = pl08x->pd->mem_buses;
2909         }
2910
2911         if (vd->pl080s)
2912                 pl08x->lli_words = PL080S_LLI_WORDS;
2913         else
2914                 pl08x->lli_words = PL080_LLI_WORDS;
2915         tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32);
2916
2917         /* A DMA memory pool for LLIs, align on 1-byte boundary */
2918         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
2919                                                 tsfr_size, PL08X_ALIGN, 0);
2920         if (!pl08x->pool) {
2921                 ret = -ENOMEM;
2922                 goto out_no_lli_pool;
2923         }
2924
2925         /* Turn on the PL08x */
2926         pl08x_ensure_on(pl08x);
2927
2928         /* Clear any pending interrupts */
2929         if (vd->ftdmac020)
2930                 /* This variant has error IRQs in bits 16-19 */
2931                 writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
2932         else
2933                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2934         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2935
2936         /* Attach the interrupt handler */
2937 #ifdef CONFIG_SOC_STARFIVE_JH7110
2938         irq = platform_get_irq(adev, 0);
2939         if (irq < 0) {
2940                 dev_err(&adev->dev, "Cannot get IRQ resource\n");
2941                 return irq;
2942         }
2943
2944         ret = request_irq(irq, pl08x_irq, 0, DRIVER_NAME, pl08x);
2945 #else
2946         ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);
2947 #endif
2948         if (ret) {
2949                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2950 #ifdef CONFIG_SOC_STARFIVE_JH7110
2951                         __func__, irq);
2952 #else
2953                         __func__, adev->irq[0]);
2954 #endif
2955                 goto out_no_irq;
2956         }
2957
2958         /* Initialize physical channels */
2959         pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2960                         GFP_KERNEL);
2961         if (!pl08x->phy_chans) {
2962                 ret = -ENOMEM;
2963                 goto out_no_phychans;
2964         }
2965
2966         for (i = 0; i < vd->channels; i++) {
2967                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2968
2969                 ch->id = i;
2970                 ch->base = pl08x->base + PL080_Cx_BASE(i);
2971                 if (vd->ftdmac020) {
2972                         /* FTDMA020 has a special channel busy register */
2973                         ch->reg_busy = ch->base + FTDMAC020_CH_BUSY;
2974                         ch->reg_config = ch->base + FTDMAC020_CH_CFG;
2975                         ch->reg_control = ch->base + FTDMAC020_CH_CSR;
2976                         ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR;
2977                         ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR;
2978                         ch->reg_lli = ch->base + FTDMAC020_CH_LLP;
2979                         ch->ftdmac020 = true;
2980                 } else {
2981                         ch->reg_config = ch->base + vd->config_offset;
2982                         ch->reg_control = ch->base + PL080_CH_CONTROL;
2983                         ch->reg_src = ch->base + PL080_CH_SRC_ADDR;
2984                         ch->reg_dst = ch->base + PL080_CH_DST_ADDR;
2985                         ch->reg_lli = ch->base + PL080_CH_LLI;
2986                 }
2987                 if (vd->pl080s)
2988                         ch->pl080s = true;
2989
2990                 spin_lock_init(&ch->lock);
2991
2992                 /*
2993                  * Nomadik variants can have channels that are locked
2994                  * down for the secure world only. Lock up these channels
2995                  * by perpetually serving a dummy virtual channel.
2996                  */
2997                 if (vd->nomadik) {
2998                         u32 val;
2999
3000                         val = readl(ch->reg_config);
3001                         if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
3002                                 dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
3003                                 ch->locked = true;
3004                         }
3005                 }
3006
3007                 dev_dbg(&adev->dev, "physical channel %d is %s\n",
3008                         i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
3009         }
3010
3011         /* Register as many memcpy channels as there are physical channels */
3012         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
3013                                               pl08x->vd->channels, false);
3014         if (ret <= 0) {
3015                 dev_warn(&pl08x->adev->dev,
3016                          "%s failed to enumerate memcpy channels - %d\n",
3017                          __func__, ret);
3018                 goto out_no_memcpy;
3019         }
3020
3021         /* Register slave channels */
3022         if (pl08x->has_slave) {
3023                 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
3024                                         pl08x->pd->num_slave_channels, true);
3025                 if (ret < 0) {
3026                         dev_warn(&pl08x->adev->dev,
3027                                  "%s failed to enumerate slave channels - %d\n",
3028                                  __func__, ret);
3029                         goto out_no_slave;
3030                 }
3031         }
3032
3033         ret = dma_async_device_register(&pl08x->memcpy);
3034         if (ret) {
3035                 dev_warn(&pl08x->adev->dev,
3036                         "%s failed to register memcpy as an async device - %d\n",
3037                         __func__, ret);
3038                 goto out_no_memcpy_reg;
3039         }
3040
3041         if (pl08x->has_slave) {
3042                 ret = dma_async_device_register(&pl08x->slave);
3043                 if (ret) {
3044                         dev_warn(&pl08x->adev->dev,
3045                         "%s failed to register slave as an async device - %d\n",
3046                         __func__, ret);
3047                         goto out_no_slave_reg;
3048                 }
3049         }
3050
3051 #ifdef CONFIG_SOC_STARFIVE_JH7110
3052         platform_set_drvdata(adev, pl08x);
3053 #else
3054         amba_set_drvdata(adev, pl08x);
3055 #endif
3056         init_pl08x_debugfs(pl08x);
3057 #ifdef CONFIG_SOC_STARFIVE_JH7110
3058         dev_dbg(&pl08x->adev->dev, "DMA: PL080  at 0x%08llx irq %d\n",
3059                  (unsigned long long)res->start, irq);
3060 #else
3061         dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n",
3062                  amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev),
3063                  (unsigned long long)adev->res.start, adev->irq[0]);
3064 #endif
3065
3066         return 0;
3067
3068 out_no_slave_reg:
3069         dma_async_device_unregister(&pl08x->memcpy);
3070 out_no_memcpy_reg:
3071         if (pl08x->has_slave)
3072                 pl08x_free_virtual_channels(&pl08x->slave);
3073 out_no_slave:
3074         pl08x_free_virtual_channels(&pl08x->memcpy);
3075 out_no_memcpy:
3076         kfree(pl08x->phy_chans);
3077 out_no_phychans:
3078 #ifdef CONFIG_SOC_STARFIVE_JH7110
3079         free_irq(irq, pl08x);
3080 #else
3081         free_irq(adev->irq[0], pl08x);
3082 #endif
3083 out_no_irq:
3084         dma_pool_destroy(pl08x->pool);
3085 out_no_lli_pool:
3086 out_no_platdata:
3087         iounmap(pl08x->base);
3088 out_no_ioremap:
3089         kfree(pl08x);
3090
3091 #ifndef CONFIG_SOC_STARFIVE_JH7110
3092 out_no_pl08x:
3093         amba_release_regions(adev);
3094 #endif
3095         return ret;
3096 }
3097
3098 /* PL080 has 8 channels and the PL080 have just 2 */
3099 static struct vendor_data vendor_pl080 = {
3100         .config_offset = PL080_CH_CONFIG,
3101         .channels = 8,
3102         .signals = 16,
3103         .dualmaster = true,
3104         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3105 };
3106 #ifdef CONFIG_SOC_STARFIVE_JH7110
3107 static const struct of_device_id jh7110_dma_ids[] = {
3108         { .compatible = "starfive,jh7110-pl080", .data = &vendor_pl080},
3109         {},
3110 };
3111 MODULE_DEVICE_TABLE(of, jh7110_dma_ids);
3112
3113 static struct platform_driver jh7110_pl08x_driver = {
3114         .probe  = pl08x_probe,
3115         .driver = {
3116                 .name           = DRIVER_NAME,
3117                 .of_match_table = jh7110_dma_ids,
3118         },
3119 };
3120
3121 module_platform_driver(jh7110_pl08x_driver);
3122
3123 MODULE_LICENSE("GPL");
3124 MODULE_AUTHOR("Huan Feng <huan.feng@starfivetech.com>");
3125 #else
3126 static struct vendor_data vendor_nomadik = {
3127         .config_offset = PL080_CH_CONFIG,
3128         .channels = 8,
3129         .signals = 32,
3130         .dualmaster = true,
3131         .nomadik = true,
3132         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3133 };
3134
3135 static struct vendor_data vendor_pl080s = {
3136         .config_offset = PL080S_CH_CONFIG,
3137         .channels = 8,
3138         .signals = 32,
3139         .pl080s = true,
3140         .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
3141 };
3142
3143 static struct vendor_data vendor_pl081 = {
3144         .config_offset = PL080_CH_CONFIG,
3145         .channels = 2,
3146         .signals = 16,
3147         .dualmaster = false,
3148         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3149 };
3150
3151 static struct vendor_data vendor_ftdmac020 = {
3152         .config_offset = PL080_CH_CONFIG,
3153         .ftdmac020 = true,
3154         .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
3155 };
3156
3157 static const struct amba_id pl08x_ids[] = {
3158         /* Samsung PL080S variant */
3159         {
3160                 .id     = 0x0a141080,
3161                 .mask   = 0xffffffff,
3162                 .data   = &vendor_pl080s,
3163         },
3164         /* PL080 */
3165         {
3166                 .id     = 0x00041080,
3167                 .mask   = 0x000fffff,
3168                 .data   = &vendor_pl080,
3169         },
3170         /* PL081 */
3171         {
3172                 .id     = 0x00041081,
3173                 .mask   = 0x000fffff,
3174                 .data   = &vendor_pl081,
3175         },
3176         /* Nomadik 8815 PL080 variant */
3177         {
3178                 .id     = 0x00280080,
3179                 .mask   = 0x00ffffff,
3180                 .data   = &vendor_nomadik,
3181         },
3182         /* Faraday Technology FTDMAC020 */
3183         {
3184                 .id     = 0x0003b080,
3185                 .mask   = 0x000fffff,
3186                 .data   = &vendor_ftdmac020,
3187         },
3188         { 0, 0 },
3189 };
3190
3191 MODULE_DEVICE_TABLE(amba, pl08x_ids);
3192
3193 static struct amba_driver pl08x_amba_driver = {
3194         .drv.name       = DRIVER_NAME,
3195         .id_table       = pl08x_ids,
3196         .probe          = pl08x_probe,
3197 };
3198
3199 static int __init pl08x_init(void)
3200 {
3201         int retval;
3202         retval = amba_driver_register(&pl08x_amba_driver);
3203         if (retval)
3204                 printk(KERN_WARNING DRIVER_NAME
3205                        "failed to register as an AMBA device (%d)\n",
3206                        retval);
3207         return retval;
3208 }
3209 subsys_initcall(pl08x_init);
3210 #endif