1 /* drivers/devfreq/exynos4210_memorybus.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 * MyungJoo Ham <myungjoo.ham@samsung.com>
7 * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework
8 * This version supports EXYNOS4210 only. This changes bus frequencies
9 * and vddint voltages. Exynos4412/4212 should be able to be supported
10 * with minor modifications.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/suspend.h>
22 #include <linux/opp.h>
23 #include <linux/devfreq.h>
24 #include <linux/platform_device.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/module.h>
28 /* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */
29 #ifdef CONFIG_EXYNOS_ASV
30 extern unsigned int exynos_result_of_asv;
33 #include <mach/regs-clock.h>
35 #include <plat/map-s5p.h>
37 #define MAX_SAFEVOLT 1200000 /* 1.2V */
39 enum exynos4_busf_type {
44 /* Assume that the bus is saturated if the utilization is 40% */
45 #define BUS_SATURATION_RATIO 40
55 void __iomem *hw_base;
58 unsigned int count[PPMU_PMNCNT_MAX];
60 bool count_overflow[PPMU_PMNCNT_MAX];
63 enum busclk_level_idx {
71 #define EX4210_LV_MAX LV_2
72 #define EX4x12_LV_MAX LV_4
73 #define EX4210_LV_NUM (LV_2 + 1)
74 #define EX4x12_LV_NUM (LV_4 + 1)
77 enum exynos4_busf_type type;
79 struct devfreq *devfreq;
81 struct regulator *vdd_int;
82 struct regulator *vdd_mif; /* Exynos4412/4212 only */
84 struct exynos4_ppmu dmc[2];
86 struct notifier_block pm_notifier;
89 /* Dividers calculated at boot/probe-time */
90 unsigned int dmc_divtable[_LV_END]; /* DMC0 */
91 unsigned int top_divtable[_LV_END];
94 struct bus_opp_table {
100 /* 4210 controls clock of mif and voltage of int */
101 static struct bus_opp_table exynos4210_busclk_table[] = {
102 {LV_0, 400000, 1150000},
103 {LV_1, 267000, 1050000},
104 {LV_2, 133000, 1025000},
109 * MIF is the main control knob clock for exynox4x12 MIF/INT
110 * clock and voltage of both mif/int are controlled.
112 static struct bus_opp_table exynos4x12_mifclk_table[] = {
113 {LV_0, 400000, 1100000},
114 {LV_1, 267000, 1000000},
115 {LV_2, 160000, 950000},
116 {LV_3, 133000, 950000},
117 {LV_4, 100000, 950000},
122 * INT is not the control knob of 4x12. LV_x is not meant to represent
123 * the current performance. (MIF does)
125 static struct bus_opp_table exynos4x12_intclk_table[] = {
126 {LV_0, 200000, 1000000},
127 {LV_1, 160000, 950000},
128 {LV_2, 133000, 925000},
129 {LV_3, 100000, 900000},
133 /* TODO: asv volt definitions are "__initdata"? */
134 /* Some chips have different operating voltages */
135 static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = {
136 {1150000, 1050000, 1050000},
137 {1125000, 1025000, 1025000},
138 {1100000, 1000000, 1000000},
139 {1075000, 975000, 975000},
140 {1050000, 950000, 950000},
143 static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = {
144 /* 400 267 160 133 100 */
145 {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */
146 {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */
147 {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */
148 {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */
149 {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */
150 {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */
151 {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */
152 {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */
153 {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */
156 static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = {
157 /* 200 160 133 100 */
158 {1000000, 950000, 925000, 900000}, /* ASV0 */
159 {975000, 925000, 925000, 900000}, /* ASV1 */
160 {950000, 925000, 900000, 875000}, /* ASV2 */
161 {950000, 900000, 900000, 875000}, /* ASV3 */
162 {925000, 875000, 875000, 875000}, /* ASV4 */
163 {900000, 850000, 850000, 850000}, /* ASV5 */
164 {900000, 850000, 850000, 850000}, /* ASV6 */
165 {900000, 850000, 850000, 850000}, /* ASV7 */
166 {900000, 850000, 850000, 850000}, /* ASV8 */
169 /*** Clock Divider Data for Exynos4210 ***/
170 static unsigned int exynos4210_clkdiv_dmc0[][8] = {
172 * Clock divider value for following
173 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
174 * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
178 { 3, 1, 1, 1, 1, 1, 3, 1 },
179 /* DMC L1: 266.7MHz */
180 { 4, 1, 1, 2, 1, 1, 3, 1 },
182 { 5, 1, 1, 5, 1, 1, 3, 1 },
184 static unsigned int exynos4210_clkdiv_top[][5] = {
186 * Clock divider value for following
187 * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
189 /* ACLK200 L0: 200MHz */
191 /* ACLK200 L1: 160MHz */
193 /* ACLK200 L2: 133MHz */
196 static unsigned int exynos4210_clkdiv_lr_bus[][2] = {
198 * Clock divider value for following
199 * { DIVGDL/R, DIVGPL/R }
201 /* ACLK_GDL/R L1: 200MHz */
203 /* ACLK_GDL/R L2: 160MHz */
205 /* ACLK_GDL/R L3: 133MHz */
209 /*** Clock Divider Data for Exynos4212/4412 ***/
210 static unsigned int exynos4x12_clkdiv_dmc0[][6] = {
212 * Clock divider value for following
213 * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
219 /* DMC L1: 266.7MHz */
228 static unsigned int exynos4x12_clkdiv_dmc1[][6] = {
230 * Clock divider value for following
231 * { G2DACP, DIVC2C, DIVC2C_ACLK }
236 /* DMC L1: 266.7MHz */
245 static unsigned int exynos4x12_clkdiv_top[][5] = {
247 * Clock divider value for following
248 * { DIVACLK266_GPS, DIVACLK100, DIVACLK160,
249 DIVACLK133, DIVONENAND }
252 /* ACLK_GDL/R L0: 200MHz */
254 /* ACLK_GDL/R L1: 200MHz */
256 /* ACLK_GDL/R L2: 160MHz */
258 /* ACLK_GDL/R L3: 133MHz */
260 /* ACLK_GDL/R L4: 100MHz */
263 static unsigned int exynos4x12_clkdiv_lr_bus[][2] = {
265 * Clock divider value for following
266 * { DIVGDL/R, DIVGPL/R }
269 /* ACLK_GDL/R L0: 200MHz */
271 /* ACLK_GDL/R L1: 200MHz */
273 /* ACLK_GDL/R L2: 160MHz */
275 /* ACLK_GDL/R L3: 133MHz */
277 /* ACLK_GDL/R L4: 100MHz */
280 static unsigned int exynos4x12_clkdiv_sclkip[][3] = {
282 * Clock divider value for following
283 * { DIVMFC, DIVJPEG, DIVFIMC0~3}
286 /* SCLK_MFC: 200MHz */
288 /* SCLK_MFC: 200MHz */
290 /* SCLK_MFC: 160MHz */
292 /* SCLK_MFC: 133MHz */
294 /* SCLK_MFC: 100MHz */
299 static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp)
304 for (index = LV_0; index < EX4210_LV_NUM; index++)
305 if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk)
308 if (index == EX4210_LV_NUM)
311 /* Change Divider - DMC0 */
312 tmp = data->dmc_divtable[index];
314 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
317 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
318 } while (tmp & 0x11111111);
320 /* Change Divider - TOP */
321 tmp = data->top_divtable[index];
323 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
326 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
327 } while (tmp & 0x11111);
329 /* Change Divider - LEFTBUS */
330 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
332 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
334 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
335 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
336 (exynos4210_clkdiv_lr_bus[index][1] <<
337 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
339 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
342 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
343 } while (tmp & 0x11);
345 /* Change Divider - RIGHTBUS */
346 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
348 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
350 tmp |= ((exynos4210_clkdiv_lr_bus[index][0] <<
351 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
352 (exynos4210_clkdiv_lr_bus[index][1] <<
353 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
355 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
358 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
359 } while (tmp & 0x11);
364 static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp)
369 for (index = LV_0; index < EX4x12_LV_NUM; index++)
370 if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk)
373 if (index == EX4x12_LV_NUM)
376 /* Change Divider - DMC0 */
377 tmp = data->dmc_divtable[index];
379 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0);
382 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0);
383 } while (tmp & 0x11111111);
385 /* Change Divider - DMC1 */
386 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1);
388 tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK |
389 EXYNOS4_CLKDIV_DMC1_C2C_MASK |
390 EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK);
392 tmp |= ((exynos4x12_clkdiv_dmc1[index][0] <<
393 EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) |
394 (exynos4x12_clkdiv_dmc1[index][1] <<
395 EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) |
396 (exynos4x12_clkdiv_dmc1[index][2] <<
397 EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT));
399 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1);
402 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1);
403 } while (tmp & 0x111111);
405 /* Change Divider - TOP */
406 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
408 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK |
409 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
410 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
411 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
412 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
414 tmp |= ((exynos4x12_clkdiv_top[index][0] <<
415 EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) |
416 (exynos4x12_clkdiv_top[index][1] <<
417 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
418 (exynos4x12_clkdiv_top[index][2] <<
419 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
420 (exynos4x12_clkdiv_top[index][3] <<
421 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
422 (exynos4x12_clkdiv_top[index][4] <<
423 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
425 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP);
428 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP);
429 } while (tmp & 0x11111);
431 /* Change Divider - LEFTBUS */
432 tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS);
434 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
436 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
437 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
438 (exynos4x12_clkdiv_lr_bus[index][1] <<
439 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
441 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS);
444 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS);
445 } while (tmp & 0x11);
447 /* Change Divider - RIGHTBUS */
448 tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS);
450 tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK);
452 tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] <<
453 EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) |
454 (exynos4x12_clkdiv_lr_bus[index][1] <<
455 EXYNOS4_CLKDIV_BUS_GPLR_SHIFT));
457 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS);
460 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS);
461 } while (tmp & 0x11);
463 /* Change Divider - MFC */
464 tmp = __raw_readl(EXYNOS4_CLKDIV_MFC);
466 tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK);
468 tmp |= ((exynos4x12_clkdiv_sclkip[index][0] <<
469 EXYNOS4_CLKDIV_MFC_SHIFT));
471 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC);
474 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC);
477 /* Change Divider - JPEG */
478 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1);
480 tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK);
482 tmp |= ((exynos4x12_clkdiv_sclkip[index][1] <<
483 EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT));
485 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1);
488 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
491 /* Change Divider - FIMC0~3 */
492 tmp = __raw_readl(EXYNOS4_CLKDIV_CAM);
494 tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK |
495 EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK);
497 tmp |= ((exynos4x12_clkdiv_sclkip[index][2] <<
498 EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) |
499 (exynos4x12_clkdiv_sclkip[index][2] <<
500 EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) |
501 (exynos4x12_clkdiv_sclkip[index][2] <<
502 EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) |
503 (exynos4x12_clkdiv_sclkip[index][2] <<
504 EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT));
506 __raw_writel(tmp, EXYNOS4_CLKDIV_CAM);
509 tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1);
510 } while (tmp & 0x1111);
516 static void busfreq_mon_reset(struct busfreq_data *data)
520 for (i = 0; i < 2; i++) {
521 void __iomem *ppmu_base = data->dmc[i].hw_base;
524 __raw_writel(0x8000000f, ppmu_base + 0xf010);
525 __raw_writel(0x8000000f, ppmu_base + 0xf050);
526 __raw_writel(0x6, ppmu_base + 0xf000);
527 __raw_writel(0x0, ppmu_base + 0xf100);
530 data->dmc[i].event = 0x6;
531 __raw_writel(((data->dmc[i].event << 12) | 0x1),
535 __raw_writel(0x1, ppmu_base + 0xf000);
539 static void exynos4_read_ppmu(struct busfreq_data *data)
543 for (i = 0; i < 2; i++) {
544 void __iomem *ppmu_base = data->dmc[i].hw_base;
548 __raw_writel(0x0, ppmu_base + 0xf000);
550 /* Update local data from PPMU */
551 overflow = __raw_readl(ppmu_base + 0xf050);
553 data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100);
554 data->dmc[i].ccnt_overflow = overflow & (1 << 31);
556 for (j = 0; j < PPMU_PMNCNT_MAX; j++) {
557 data->dmc[i].count[j] = __raw_readl(
558 ppmu_base + (0xf110 + (0x10 * j)));
559 data->dmc[i].count_overflow[j] = overflow & (1 << j);
563 busfreq_mon_reset(data);
566 static int exynos4x12_get_intspec(unsigned long mifclk)
570 while (exynos4x12_intclk_table[i].clk) {
571 if (exynos4x12_intclk_table[i].clk <= mifclk)
579 static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp,
583 unsigned long volt = opp_get_voltage(opp);
585 switch (data->type) {
586 case TYPE_BUSF_EXYNOS4210:
587 /* OPP represents DMC clock + INT voltage */
588 err = regulator_set_voltage(data->vdd_int, volt,
591 case TYPE_BUSF_EXYNOS4x12:
592 /* OPP represents MIF clock + MIF voltage */
593 err = regulator_set_voltage(data->vdd_mif, volt,
598 tmp = exynos4x12_get_intspec(opp_get_freq(opp));
601 regulator_set_voltage(data->vdd_mif,
602 opp_get_voltage(oldopp),
606 err = regulator_set_voltage(data->vdd_int,
607 exynos4x12_intclk_table[tmp].volt,
611 regulator_set_voltage(data->vdd_mif,
612 opp_get_voltage(oldopp),
622 static int exynos4_bus_target(struct device *dev, unsigned long *_freq,
626 struct platform_device *pdev = container_of(dev, struct platform_device,
628 struct busfreq_data *data = platform_get_drvdata(pdev);
629 struct opp *opp = devfreq_recommended_opp(dev, _freq, flags);
630 unsigned long freq = opp_get_freq(opp);
631 unsigned long old_freq = opp_get_freq(data->curr_opp);
636 if (old_freq == freq)
639 dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp));
641 mutex_lock(&data->lock);
647 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
651 if (old_freq != freq) {
652 switch (data->type) {
653 case TYPE_BUSF_EXYNOS4210:
654 err = exynos4210_set_busclk(data, opp);
656 case TYPE_BUSF_EXYNOS4x12:
657 err = exynos4x12_set_busclk(data, opp);
667 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
671 data->curr_opp = opp;
673 mutex_unlock(&data->lock);
677 static int exynos4_get_busier_dmc(struct busfreq_data *data)
679 u64 p0 = data->dmc[0].count[0];
680 u64 p1 = data->dmc[1].count[0];
682 p0 *= data->dmc[1].ccnt;
683 p1 *= data->dmc[0].ccnt;
685 if (data->dmc[1].ccnt == 0)
693 static int exynos4_bus_get_dev_status(struct device *dev,
694 struct devfreq_dev_status *stat)
696 struct busfreq_data *data = dev_get_drvdata(dev);
698 int cycles_x2 = 2; /* 2 x cycles */
703 exynos4_read_ppmu(data);
704 busier_dmc = exynos4_get_busier_dmc(data);
705 stat->current_frequency = opp_get_freq(data->curr_opp);
712 memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */
713 timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */
715 switch ((memctrl >> 8) & 0xf) {
717 cycles_x2 = ((timing >> 16) & 0xf) * 2;
719 case 0x5: /* LPDDR2 */
721 cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf);
724 pr_err("%s: Unknown Memory Type(%d).\n", __func__,
725 (memctrl >> 8) & 0xf);
729 /* Number of cycles spent on memory access */
730 stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2);
731 stat->busy_time *= 100 / BUS_SATURATION_RATIO;
732 stat->total_time = data->dmc[busier_dmc].ccnt;
734 /* If the counters have overflown, retry */
735 if (data->dmc[busier_dmc].ccnt_overflow ||
736 data->dmc[busier_dmc].count_overflow[0])
742 static void exynos4_bus_exit(struct device *dev)
744 struct busfreq_data *data = dev_get_drvdata(dev);
746 devfreq_unregister_opp_notifier(dev, data->devfreq);
749 static struct devfreq_dev_profile exynos4_devfreq_profile = {
750 .initial_freq = 400000,
752 .target = exynos4_bus_target,
753 .get_dev_status = exynos4_bus_get_dev_status,
754 .exit = exynos4_bus_exit,
757 static int exynos4210_init_tables(struct busfreq_data *data)
763 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
764 for (i = LV_0; i < EX4210_LV_NUM; i++) {
765 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
766 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
767 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
768 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
769 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
770 EXYNOS4_CLKDIV_DMC0_DMCP_MASK |
771 EXYNOS4_CLKDIV_DMC0_COPY2_MASK |
772 EXYNOS4_CLKDIV_DMC0_CORETI_MASK);
774 tmp |= ((exynos4210_clkdiv_dmc0[i][0] <<
775 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
776 (exynos4210_clkdiv_dmc0[i][1] <<
777 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
778 (exynos4210_clkdiv_dmc0[i][2] <<
779 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
780 (exynos4210_clkdiv_dmc0[i][3] <<
781 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
782 (exynos4210_clkdiv_dmc0[i][4] <<
783 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
784 (exynos4210_clkdiv_dmc0[i][5] <<
785 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) |
786 (exynos4210_clkdiv_dmc0[i][6] <<
787 EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) |
788 (exynos4210_clkdiv_dmc0[i][7] <<
789 EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT));
791 data->dmc_divtable[i] = tmp;
794 tmp = __raw_readl(EXYNOS4_CLKDIV_TOP);
795 for (i = LV_0; i < EX4210_LV_NUM; i++) {
796 tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK |
797 EXYNOS4_CLKDIV_TOP_ACLK100_MASK |
798 EXYNOS4_CLKDIV_TOP_ACLK160_MASK |
799 EXYNOS4_CLKDIV_TOP_ACLK133_MASK |
800 EXYNOS4_CLKDIV_TOP_ONENAND_MASK);
802 tmp |= ((exynos4210_clkdiv_top[i][0] <<
803 EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) |
804 (exynos4210_clkdiv_top[i][1] <<
805 EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) |
806 (exynos4210_clkdiv_top[i][2] <<
807 EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) |
808 (exynos4210_clkdiv_top[i][3] <<
809 EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) |
810 (exynos4210_clkdiv_top[i][4] <<
811 EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT));
813 data->top_divtable[i] = tmp;
816 #ifdef CONFIG_EXYNOS_ASV
817 tmp = exynos4_result_of_asv;
819 tmp = 0; /* Max voltages for the reliability of the unknown */
822 pr_debug("ASV Group of Exynos4 is %d\n", tmp);
823 /* Use merged grouping for voltage */
844 pr_warn("Unknown ASV Group. Use max voltage.\n");
848 for (i = LV_0; i < EX4210_LV_NUM; i++)
849 exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i];
851 for (i = LV_0; i < EX4210_LV_NUM; i++) {
852 err = opp_add(data->dev, exynos4210_busclk_table[i].clk,
853 exynos4210_busclk_table[i].volt);
855 dev_err(data->dev, "Cannot add opp entries.\n");
864 static int exynos4x12_init_tables(struct busfreq_data *data)
870 /* Enable pause function for DREX2 DVFS */
871 tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL);
872 tmp |= EXYNOS4_DMC_PAUSE_ENABLE;
873 __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL);
875 tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0);
877 for (i = 0; i < EX4x12_LV_NUM; i++) {
878 tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK |
879 EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK |
880 EXYNOS4_CLKDIV_DMC0_DPHY_MASK |
881 EXYNOS4_CLKDIV_DMC0_DMC_MASK |
882 EXYNOS4_CLKDIV_DMC0_DMCD_MASK |
883 EXYNOS4_CLKDIV_DMC0_DMCP_MASK);
885 tmp |= ((exynos4x12_clkdiv_dmc0[i][0] <<
886 EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
887 (exynos4x12_clkdiv_dmc0[i][1] <<
888 EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) |
889 (exynos4x12_clkdiv_dmc0[i][2] <<
890 EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) |
891 (exynos4x12_clkdiv_dmc0[i][3] <<
892 EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) |
893 (exynos4x12_clkdiv_dmc0[i][4] <<
894 EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) |
895 (exynos4x12_clkdiv_dmc0[i][5] <<
896 EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT));
898 data->dmc_divtable[i] = tmp;
901 #ifdef CONFIG_EXYNOS_ASV
902 tmp = exynos4_result_of_asv;
904 tmp = 0; /* Max voltages for the reliability of the unknown */
909 pr_debug("ASV Group of Exynos4x12 is %d\n", tmp);
911 for (i = 0; i < EX4x12_LV_NUM; i++) {
912 exynos4x12_mifclk_table[i].volt =
913 exynos4x12_mif_step_50[tmp][i];
914 exynos4x12_intclk_table[i].volt =
915 exynos4x12_int_volt[tmp][i];
918 for (i = 0; i < EX4x12_LV_NUM; i++) {
919 ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk,
920 exynos4x12_mifclk_table[i].volt);
922 dev_err(data->dev, "Fail to add opp entries.\n");
930 static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this,
931 unsigned long event, void *ptr)
933 struct busfreq_data *data = container_of(this, struct busfreq_data,
936 unsigned long maxfreq = ULONG_MAX;
940 case PM_SUSPEND_PREPARE:
941 /* Set Fastest and Deactivate DVFS */
942 mutex_lock(&data->lock);
944 data->disabled = true;
946 opp = opp_find_freq_floor(data->dev, &maxfreq);
948 err = exynos4_bus_setvolt(data, opp, data->curr_opp);
952 switch (data->type) {
953 case TYPE_BUSF_EXYNOS4210:
954 err = exynos4210_set_busclk(data, opp);
956 case TYPE_BUSF_EXYNOS4x12:
957 err = exynos4x12_set_busclk(data, opp);
965 data->curr_opp = opp;
967 mutex_unlock(&data->lock);
971 case PM_POST_RESTORE:
972 case PM_POST_SUSPEND:
974 mutex_lock(&data->lock);
975 data->disabled = false;
976 mutex_unlock(&data->lock);
983 static __devinit int exynos4_busfreq_probe(struct platform_device *pdev)
985 struct busfreq_data *data;
987 struct device *dev = &pdev->dev;
990 data = kzalloc(sizeof(struct busfreq_data), GFP_KERNEL);
992 dev_err(dev, "Cannot allocate memory.\n");
996 data->type = pdev->id_entry->driver_data;
997 data->dmc[0].hw_base = S5P_VA_DMC0;
998 data->dmc[1].hw_base = S5P_VA_DMC1;
999 data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event;
1001 mutex_init(&data->lock);
1003 switch (data->type) {
1004 case TYPE_BUSF_EXYNOS4210:
1005 err = exynos4210_init_tables(data);
1007 case TYPE_BUSF_EXYNOS4x12:
1008 err = exynos4x12_init_tables(data);
1011 dev_err(dev, "Cannot determine the device id %d\n", data->type);
1017 data->vdd_int = regulator_get(dev, "vdd_int");
1018 if (IS_ERR(data->vdd_int)) {
1019 dev_err(dev, "Cannot get the regulator \"vdd_int\"\n");
1020 err = PTR_ERR(data->vdd_int);
1023 if (data->type == TYPE_BUSF_EXYNOS4x12) {
1024 data->vdd_mif = regulator_get(dev, "vdd_mif");
1025 if (IS_ERR(data->vdd_mif)) {
1026 dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n");
1027 err = PTR_ERR(data->vdd_mif);
1028 regulator_put(data->vdd_int);
1034 opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq);
1036 dev_err(dev, "Invalid initial frequency %lu kHz.\n",
1037 exynos4_devfreq_profile.initial_freq);
1041 data->curr_opp = opp;
1043 platform_set_drvdata(pdev, data);
1045 busfreq_mon_reset(data);
1047 data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile,
1048 &devfreq_simple_ondemand, NULL);
1049 if (IS_ERR(data->devfreq)) {
1050 err = PTR_ERR(data->devfreq);
1054 devfreq_register_opp_notifier(dev, data->devfreq);
1056 err = register_pm_notifier(&data->pm_notifier);
1058 dev_err(dev, "Failed to setup pm notifier\n");
1059 goto err_devfreq_add;
1064 devfreq_remove_device(data->devfreq);
1067 regulator_put(data->vdd_mif);
1068 regulator_put(data->vdd_int);
1074 static __devexit int exynos4_busfreq_remove(struct platform_device *pdev)
1076 struct busfreq_data *data = platform_get_drvdata(pdev);
1078 unregister_pm_notifier(&data->pm_notifier);
1079 devfreq_remove_device(data->devfreq);
1080 regulator_put(data->vdd_int);
1082 regulator_put(data->vdd_mif);
1088 static int exynos4_busfreq_resume(struct device *dev)
1090 struct busfreq_data *data = dev_get_drvdata(dev);
1092 busfreq_mon_reset(data);
1096 static const struct dev_pm_ops exynos4_busfreq_pm = {
1097 .resume = exynos4_busfreq_resume,
1100 static const struct platform_device_id exynos4_busfreq_id[] = {
1101 { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 },
1102 { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 },
1103 { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 },
1107 static struct platform_driver exynos4_busfreq_driver = {
1108 .probe = exynos4_busfreq_probe,
1109 .remove = __devexit_p(exynos4_busfreq_remove),
1110 .id_table = exynos4_busfreq_id,
1112 .name = "exynos4-busfreq",
1113 .owner = THIS_MODULE,
1114 .pm = &exynos4_busfreq_pm,
1118 static int __init exynos4_busfreq_init(void)
1120 return platform_driver_register(&exynos4_busfreq_driver);
1122 late_initcall(exynos4_busfreq_init);
1124 static void __exit exynos4_busfreq_exit(void)
1126 platform_driver_unregister(&exynos4_busfreq_driver);
1128 module_exit(exynos4_busfreq_exit);
1130 MODULE_LICENSE("GPL");
1131 MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework");
1132 MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>");