drivers/ddr/marvell/a38x/ddr3_training.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include "ddr3_init.h"
   7 #include "mv_ddr_common.h"
   8 #include "mv_ddr_training_db.h"
   9 #include "mv_ddr_regs.h"
  10
  11 #define GET_CS_FROM_MASK(mask)  (cs_mask2_num[mask])
  12 #define CS_CBE_VALUE(cs_num)    (cs_cbe_reg[cs_num])
  13
  14 u32 window_mem_addr = 0;
  15 u32 phy_reg0_val = 0;
  16 u32 phy_reg1_val = 8;
  17 u32 phy_reg2_val = 0;
  18 u32 phy_reg3_val = PARAM_UNDEFINED;
  19 enum mv_ddr_freq low_freq = MV_DDR_FREQ_LOW_FREQ;
  20 enum mv_ddr_freq medium_freq;
  21 u32 debug_dunit = 0;
  22 u32 odt_additional = 1;
  23 u32 *dq_map_table = NULL;
  24
  25 /* in case of ddr4 do not run ddr3_tip_write_additional_odt_setting function - mc odt always 'on'
  26  * in ddr4 case the terminations are rttWR and rttPARK and the odt must be always 'on' 0x1498 = 0xf
  27  */
  28 #if defined(CONFIG_DDR4)
  29 u32 odt_config = 0;
  30 #else
  31 u32 odt_config = 1;
  32 #endif
  33
  34 u32 nominal_avs;
  35 u32 extension_avs;
  36
  37 u32 is_pll_before_init = 0, is_adll_calib_before_init = 1, is_dfs_in_init = 0;
  38 u32 dfs_low_freq;
  39
  40 u32 g_rtt_nom_cs0, g_rtt_nom_cs1;
  41 u8 calibration_update_control;  /* 2 external only, 1 is internal only */
  42
  43 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
  44 enum auto_tune_stage training_stage = INIT_CONTROLLER;
  45 u32 finger_test = 0, p_finger_start = 11, p_finger_end = 64,
  46         n_finger_start = 11, n_finger_end = 64,
  47         p_finger_step = 3, n_finger_step = 3;
  48 u32 clamp_tbl[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
  49
  50 /* Initiate to 0xff, this variable is define by user in debug mode */
  51 u32 mode_2t = 0xff;
  52 u32 xsb_validate_type = 0;
  53 u32 xsb_validation_base_address = 0xf000;
  54 u32 first_active_if = 0;
  55 u32 dfs_low_phy1 = 0x1f;
  56 u32 multicast_id = 0;
  57 int use_broadcast = 0;
  58 struct hws_tip_freq_config_info *freq_info_table = NULL;
  59 u8 is_cbe_required = 0;
  60 u32 debug_mode = 0;
  61 u32 delay_enable = 0;
  62 int rl_mid_freq_wa = 0;
  63
  64 u32 effective_cs = 0;
  65
  66 u32 vref_init_val = 0x4;
  67 u32 ck_delay = PARAM_UNDEFINED;
  68
  69 /* Design guidelines parameters */
  70 u32 g_zpri_data = PARAM_UNDEFINED; /* controller data - P drive strength */
  71 u32 g_znri_data = PARAM_UNDEFINED; /* controller data - N drive strength */
  72 u32 g_zpri_ctrl = PARAM_UNDEFINED; /* controller C/A - P drive strength */
  73 u32 g_znri_ctrl = PARAM_UNDEFINED; /* controller C/A - N drive strength */
  74
  75 u32 g_zpodt_data = PARAM_UNDEFINED; /* controller data - P ODT */
  76 u32 g_znodt_data = PARAM_UNDEFINED; /* controller data - N ODT */
  77 u32 g_zpodt_ctrl = PARAM_UNDEFINED; /* controller data - P ODT */
  78 u32 g_znodt_ctrl = PARAM_UNDEFINED; /* controller data - N ODT */
  79
  80 u32 g_odt_config = PARAM_UNDEFINED;
  81 u32 g_rtt_nom = PARAM_UNDEFINED;
  82 u32 g_rtt_wr = PARAM_UNDEFINED;
  83 u32 g_dic = PARAM_UNDEFINED;
  84 u32 g_rtt_park = PARAM_UNDEFINED;
  85
  86 u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
  87                       WRITE_LEVELING_MASK_BIT |
  88                       LOAD_PATTERN_2_MASK_BIT |
  89                       READ_LEVELING_MASK_BIT |
  90                       SET_TARGET_FREQ_MASK_BIT |
  91                       WRITE_LEVELING_TF_MASK_BIT |
  92 #if defined(CONFIG_DDR4)
  93                       SW_READ_LEVELING_MASK_BIT |
  94 #else /* CONFIG_DDR4 */
  95                       READ_LEVELING_TF_MASK_BIT |
  96 #endif /* CONFIG_DDR4 */
  97                       CENTRALIZATION_RX_MASK_BIT |
  98                       CENTRALIZATION_TX_MASK_BIT);
  99
 100 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
 101 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
 102                               u32 if_id, u32 cl_value, u32 cwl_value);
 103 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
 104
 105 #ifdef ODT_TEST_SUPPORT
 106 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
 107 #endif
 108
 109 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
 110                      u32 if_id, enum mv_ddr_freq frequency);
 111 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
 112                                u32 if_id, enum mv_ddr_freq frequency);
 113 #if defined(CONFIG_DDR4)
 114 static int ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
 115                                u32 if_id, enum mv_ddr_freq frequency);
 116 #endif /* CONFIG_DDR4 */
 117
 118 static u8 mem_size_config[MV_DDR_DIE_CAP_LAST] = {
 119         0x2,                    /* 512Mbit  */
 120         0x3,                    /* 1Gbit    */
 121         0x0,                    /* 2Gbit    */
 122         0x4,                    /* 4Gbit    */
 123         0x5,                    /* 8Gbit    */
 124         0x0, /* TODO: placeholder for 16-Mbit die capacity */
 125         0x0, /* TODO: placeholder for 32-Mbit die capacity */
 126         0x0, /* TODO: placeholder for 12-Mbit die capacity */
 127         0x0  /* TODO: placeholder for 24-Mbit die capacity */
 128 };
 129
 130 static u8 cs_mask2_num[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
 131
 132 static struct reg_data odpg_default_value[] = {
 133         {0x1034, 0x38000, MASK_ALL_BITS},
 134         {0x1038, 0x0, MASK_ALL_BITS},
 135         {0x10b0, 0x0, MASK_ALL_BITS},
 136         {0x10b8, 0x0, MASK_ALL_BITS},
 137         {0x10c0, 0x0, MASK_ALL_BITS},
 138         {0x10f0, 0x0, MASK_ALL_BITS},
 139         {0x10f4, 0x0, MASK_ALL_BITS},
 140         {0x10f8, 0xff, MASK_ALL_BITS},
 141         {0x10fc, 0xffff, MASK_ALL_BITS},
 142         {0x1130, 0x0, MASK_ALL_BITS},
 143         {0x1830, 0x2000000, MASK_ALL_BITS},
 144         {0x14d0, 0x0, MASK_ALL_BITS},
 145         {0x14d4, 0x0, MASK_ALL_BITS},
 146         {0x14d8, 0x0, MASK_ALL_BITS},
 147         {0x14dc, 0x0, MASK_ALL_BITS},
 148         {0x1454, 0x0, MASK_ALL_BITS},
 149         {0x1594, 0x0, MASK_ALL_BITS},
 150         {0x1598, 0x0, MASK_ALL_BITS},
 151         {0x159c, 0x0, MASK_ALL_BITS},
 152         {0x15a0, 0x0, MASK_ALL_BITS},
 153         {0x15a4, 0x0, MASK_ALL_BITS},
 154         {0x15a8, 0x0, MASK_ALL_BITS},
 155         {0x15ac, 0x0, MASK_ALL_BITS},
 156         {0x1600, 0x0, MASK_ALL_BITS},
 157         {0x1604, 0x0, MASK_ALL_BITS},
 158         {0x1608, 0x0, MASK_ALL_BITS},
 159         {0x160c, 0x0, MASK_ALL_BITS},
 160         {0x1610, 0x0, MASK_ALL_BITS},
 161         {0x1614, 0x0, MASK_ALL_BITS},
 162         {0x1618, 0x0, MASK_ALL_BITS},
 163         {0x1624, 0x0, MASK_ALL_BITS},
 164         {0x1690, 0x0, MASK_ALL_BITS},
 165         {0x1694, 0x0, MASK_ALL_BITS},
 166         {0x1698, 0x0, MASK_ALL_BITS},
 167         {0x169c, 0x0, MASK_ALL_BITS},
 168         {0x14b8, 0x6f67, MASK_ALL_BITS},
 169         {0x1630, 0x0, MASK_ALL_BITS},
 170         {0x1634, 0x0, MASK_ALL_BITS},
 171         {0x1638, 0x0, MASK_ALL_BITS},
 172         {0x163c, 0x0, MASK_ALL_BITS},
 173         {0x16b0, 0x0, MASK_ALL_BITS},
 174         {0x16b4, 0x0, MASK_ALL_BITS},
 175         {0x16b8, 0x0, MASK_ALL_BITS},
 176         {0x16bc, 0x0, MASK_ALL_BITS},
 177         {0x16c0, 0x0, MASK_ALL_BITS},
 178         {0x16c4, 0x0, MASK_ALL_BITS},
 179         {0x16c8, 0x0, MASK_ALL_BITS},
 180         {0x16cc, 0x1, MASK_ALL_BITS},
 181         {0x16f0, 0x1, MASK_ALL_BITS},
 182         {0x16f4, 0x0, MASK_ALL_BITS},
 183         {0x16f8, 0x0, MASK_ALL_BITS},
 184         {0x16fc, 0x0, MASK_ALL_BITS}
 185 };
 186
 187 /* MR cmd and addr definitions */
 188 #if defined(CONFIG_DDR4)
 189 struct mv_ddr_mr_data mr_data[] = {
 190         {MRS0_CMD, DDR4_MR0_REG},
 191         {MRS1_CMD, DDR4_MR1_REG},
 192         {MRS2_CMD, DDR4_MR2_REG},
 193         {MRS3_CMD, DDR4_MR3_REG},
 194         {MRS4_CMD, DDR4_MR4_REG},
 195         {MRS5_CMD, DDR4_MR5_REG},
 196         {MRS6_CMD, DDR4_MR6_REG}
 197 };
 198 #else
 199 struct mv_ddr_mr_data mr_data[] = {
 200         {MRS0_CMD, MR0_REG},
 201         {MRS1_CMD, MR1_REG},
 202         {MRS2_CMD, MR2_REG},
 203         {MRS3_CMD, MR3_REG}
 204 };
 205 #endif
 206
 207 /* inverse pads */
 208 static int ddr3_tip_pad_inv(void)
 209 {
 210         u32 sphy, data;
 211         u32 sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
 212         u32 ck_swap_ctrl_sphy;
 213         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 214
 215         for (sphy = 0; sphy < sphy_max; sphy++) {
 216                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
 217                 if (tm->interface_params[0].
 218                     as_bus_params[sphy].is_dqs_swap == 1) {
 219                         data = (INVERT_PAD << INV_PAD4_OFFS |
 220                                 INVERT_PAD << INV_PAD5_OFFS);
 221                         /* dqs swap */
 222                         ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
 223                                                        0, sphy,
 224                                                        DDR_PHY_DATA,
 225                                                        PHY_CTRL_PHY_REG,
 226                                                        data, data);
 227                 }
 228
 229                 if (tm->interface_params[0].as_bus_params[sphy].
 230                     is_ck_swap == 1 && sphy == 0) {
 231 /* TODO: move this code to per platform one */
 232                         /* clock swap for both cs0 and cs1 */
 233                         data = (INVERT_PAD << INV_PAD2_OFFS |
 234                                 INVERT_PAD << INV_PAD6_OFFS |
 235                                 INVERT_PAD << INV_PAD4_OFFS |
 236                                 INVERT_PAD << INV_PAD5_OFFS);
 237                         ck_swap_ctrl_sphy = CK_SWAP_CTRL_PHY_NUM;
 238                         ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
 239                                                        0, ck_swap_ctrl_sphy,
 240                                                        DDR_PHY_CONTROL,
 241                                                        PHY_CTRL_PHY_REG,
 242                                                        data, data);
 243                 }
 244         }
 245
 246         return MV_OK;
 247 }
 248
 249 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
 250
 251 /*
 252  * Update global training parameters by data from user
 253  */
 254 int ddr3_tip_tune_training_params(u32 dev_num,
 255                                   struct tune_train_params *params)
 256 {
 257         if (params->ck_delay != PARAM_UNDEFINED)
 258                 ck_delay = params->ck_delay;
 259         if (params->phy_reg3_val != PARAM_UNDEFINED)
 260                 phy_reg3_val = params->phy_reg3_val;
 261         if (params->g_rtt_nom != PARAM_UNDEFINED)
 262                 g_rtt_nom = params->g_rtt_nom;
 263         if (params->g_rtt_wr != PARAM_UNDEFINED)
 264                 g_rtt_wr = params->g_rtt_wr;
 265         if (params->g_dic != PARAM_UNDEFINED)
 266                 g_dic = params->g_dic;
 267         if (params->g_odt_config != PARAM_UNDEFINED)
 268                 g_odt_config = params->g_odt_config;
 269         if (params->g_zpri_data != PARAM_UNDEFINED)
 270                 g_zpri_data = params->g_zpri_data;
 271         if (params->g_znri_data != PARAM_UNDEFINED)
 272                 g_znri_data = params->g_znri_data;
 273         if (params->g_zpri_ctrl != PARAM_UNDEFINED)
 274                 g_zpri_ctrl = params->g_zpri_ctrl;
 275         if (params->g_znri_ctrl != PARAM_UNDEFINED)
 276                 g_znri_ctrl = params->g_znri_ctrl;
 277         if (params->g_zpodt_data != PARAM_UNDEFINED)
 278                 g_zpodt_data = params->g_zpodt_data;
 279         if (params->g_znodt_data != PARAM_UNDEFINED)
 280                 g_znodt_data = params->g_znodt_data;
 281         if (params->g_zpodt_ctrl != PARAM_UNDEFINED)
 282                 g_zpodt_ctrl = params->g_zpodt_ctrl;
 283         if (params->g_znodt_ctrl != PARAM_UNDEFINED)
 284                 g_znodt_ctrl = params->g_znodt_ctrl;
 285         if (params->g_rtt_park != PARAM_UNDEFINED)
 286                 g_rtt_park = params->g_rtt_park;
 287
 288
 289         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 290                           ("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
 291                            g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
 292                            g_zpodt_ctrl, g_znodt_ctrl, g_rtt_nom, g_dic, g_odt_config, g_rtt_wr));
 293
 294         return MV_OK;
 295 }
 296
 297 /*
 298  * Configure CS
 299  */
 300 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
 301 {
 302         u32 data, addr_hi, data_high;
 303         u32 mem_index;
 304         u32 clk_enable;
 305         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 306
 307         if (tm->clk_enable & (1 << cs_num))
 308                 clk_enable = 1;
 309         else
 310                 clk_enable = enable;
 311
 312         if (enable == 1) {
 313                 data = (tm->interface_params[if_id].bus_width ==
 314                         MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
 315                 CHECK_STATUS(ddr3_tip_if_write
 316                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 317                               SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)),
 318                               0x3 << (cs_num * 4)));
 319                 mem_index = tm->interface_params[if_id].memory_size;
 320
 321                 addr_hi = mem_size_config[mem_index] & 0x3;
 322                 CHECK_STATUS(ddr3_tip_if_write
 323                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 324                               SDRAM_ADDR_CTRL_REG,
 325                               (addr_hi << (2 + cs_num * 4)),
 326                               0x3 << (2 + cs_num * 4)));
 327
 328                 data_high = (mem_size_config[mem_index] & 0x4) >> 2;
 329                 CHECK_STATUS(ddr3_tip_if_write
 330                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 331                               SDRAM_ADDR_CTRL_REG,
 332                               data_high << (20 + cs_num), 1 << (20 + cs_num)));
 333
 334                 /* Enable Address Select Mode */
 335                 CHECK_STATUS(ddr3_tip_if_write
 336                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 337                               SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num),
 338                               1 << (16 + cs_num)));
 339         }
 340         switch (cs_num) {
 341         case 0:
 342         case 1:
 343         case 2:
 344                 CHECK_STATUS(ddr3_tip_if_write
 345                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 346                               DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)),
 347                               1 << (cs_num + 11)));
 348                 break;
 349         case 3:
 350                 CHECK_STATUS(ddr3_tip_if_write
 351                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
 352                               DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15));
 353                 break;
 354         }
 355
 356         return MV_OK;
 357 }
 358
 359 /*
 360  * Init Controller Flow
 361  */
 362 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
 363 {
 364         u32 if_id;
 365         u32 cs_num;
 366         u32 t_ckclk = 0, t_wr = 0, t2t = 0;
 367         u32 data_value = 0, cs_cnt = 0,
 368                 mem_mask = 0, bus_index = 0;
 369         enum mv_ddr_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
 370         u32 cs_mask = 0;
 371         u32 cl_value = 0, cwl_val = 0;
 372         u32 bus_cnt = 0, adll_tap = 0;
 373         enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
 374         u32 data_read[MAX_INTERFACE_NUM];
 375         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 376         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 377         enum mv_ddr_timing timing;
 378         enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
 379
 380         DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 381                           ("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
 382                            init_cntr_prm->do_mrs_phy,
 383                            init_cntr_prm->is_ctrl64_bit));
 384
 385         if (init_cntr_prm->init_phy == 1) {
 386                 CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
 387         }
 388
 389         if (generic_init_controller == 1) {
 390                 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
 391                         VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 392                         DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 393                                           ("active IF %d\n", if_id));
 394                         mem_mask = 0;
 395                         for (bus_index = 0;
 396                              bus_index < octets_per_if_num;
 397                              bus_index++) {
 398                                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
 399                                 mem_mask |=
 400                                         tm->interface_params[if_id].
 401                                         as_bus_params[bus_index].mirror_enable_bitmask;
 402                         }
 403
 404                         if (mem_mask != 0) {
 405                                 CHECK_STATUS(ddr3_tip_if_write
 406                                              (dev_num, ACCESS_TYPE_MULTICAST,
 407                                               if_id, DUAL_DUNIT_CFG_REG, 0,
 408                                               0x8));
 409                         }
 410
 411                         speed_bin_index =
 412                                 tm->interface_params[if_id].
 413                                 speed_bin_index;
 414
 415                         /* t_ckclk is external clock */
 416                         t_ckclk = (MEGA / mv_ddr_freq_get(freq));
 417
 418                         if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
 419                                 data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26);
 420                         else
 421                                 data_value = (0x4000 | 0x8000 | 0x1000000) & ~(1 << 26);
 422
 423                         /* Interface Bus Width */
 424                         /* SRMode */
 425                         CHECK_STATUS(ddr3_tip_if_write
 426                                      (dev_num, access_type, if_id,
 427                                       SDRAM_CFG_REG, data_value,
 428                                       0x100c000));
 429
 430                         /* Interleave first command pre-charge enable (TBD) */
 431                         CHECK_STATUS(ddr3_tip_if_write
 432                                      (dev_num, access_type, if_id,
 433                                       SDRAM_OPEN_PAGES_CTRL_REG, (1 << 10),
 434                                       (1 << 10)));
 435
 436                         /* Reset divider_b assert -> de-assert */
 437                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
 438                                                        SDRAM_CFG_REG,
 439                                                        0x0 << PUP_RST_DIVIDER_OFFS,
 440                                                        PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
 441
 442                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
 443                                                        SDRAM_CFG_REG,
 444                                                        0x1 << PUP_RST_DIVIDER_OFFS,
 445                                                        PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
 446
 447                         /* PHY configuration */
 448                         /*
 449                          * Postamble Length = 1.5cc, Addresscntl to clk skew
 450                          * \BD, Preamble length normal, parralal ADLL enable
 451                          */
 452                         CHECK_STATUS(ddr3_tip_if_write
 453                                      (dev_num, access_type, if_id,
 454                                       DRAM_PHY_CFG_REG, 0x28, 0x3e));
 455                         if (init_cntr_prm->is_ctrl64_bit) {
 456                                 /* positive edge */
 457                                 CHECK_STATUS(ddr3_tip_if_write
 458                                              (dev_num, access_type, if_id,
 459                                               DRAM_PHY_CFG_REG, 0x0,
 460                                               0xff80));
 461                         }
 462
 463                         /* calibration block disable */
 464                         /* Xbar Read buffer select (for Internal access) */
 465                         CHECK_STATUS(ddr3_tip_if_write
 466                                      (dev_num, access_type, if_id,
 467                                       MAIN_PADS_CAL_MACH_CTRL_REG, 0x1200c,
 468                                       0x7dffe01c));
 469                         CHECK_STATUS(ddr3_tip_if_write
 470                                      (dev_num, access_type, if_id,
 471                                       MAIN_PADS_CAL_MACH_CTRL_REG,
 472                                       calibration_update_control << 3, 0x3 << 3));
 473
 474                         /* Pad calibration control - enable */
 475                         CHECK_STATUS(ddr3_tip_if_write
 476                                      (dev_num, access_type, if_id,
 477                                       MAIN_PADS_CAL_MACH_CTRL_REG, 0x1, 0x1));
 478                         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
 479                                 /* DDR3 rank ctrl \96 part of the generic code */
 480                                 /* CS1 mirroring enable + w/a for JIRA DUNIT-14581 */
 481                                 CHECK_STATUS(ddr3_tip_if_write
 482                                              (dev_num, access_type, if_id,
 483                                               DDR3_RANK_CTRL_REG, 0x27, MASK_ALL_BITS));
 484                         }
 485
 486                         cs_mask = 0;
 487                         data_value = 0x7;
 488                         /*
 489                          * Address ctrl \96 Part of the Generic code
 490                          * The next configuration is done:
 491                          * 1)  Memory Size
 492                          * 2) Bus_width
 493                          * 3) CS#
 494                          * 4) Page Number
 495                          * Per Dunit get from the Map_topology the parameters:
 496                          * Bus_width
 497                          */
 498
 499                         data_value =
 500                                 (tm->interface_params[if_id].
 501                                  bus_width == MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
 502
 503                         /* create merge cs mask for all cs available in dunit */
 504                         for (bus_cnt = 0;
 505                              bus_cnt < octets_per_if_num;
 506                              bus_cnt++) {
 507                                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
 508                                 cs_mask |=
 509                                         tm->interface_params[if_id].
 510                                         as_bus_params[bus_cnt].cs_bitmask;
 511                         }
 512                         DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 513                                           ("Init_controller IF %d cs_mask %d\n",
 514                                            if_id, cs_mask));
 515                         /*
 516                          * Configure the next upon the Map Topology \96 If the
 517                          * Dunit is CS0 Configure CS0 if it is multi CS
 518                          * configure them both:  The Bust_width it\92s the
 519                          * Memory Bus width \96 x8 or x16
 520                          */
 521                         for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) {
 522                                 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
 523                                                       ((cs_mask & (1 << cs_cnt)) ? 1
 524                                                        : 0));
 525                         }
 526
 527                         if (init_cntr_prm->do_mrs_phy) {
 528                                 /*
 529                                  * MR0 \96 Part of the Generic code
 530                                  * The next configuration is done:
 531                                  * 1) Burst Length
 532                                  * 2) CAS Latency
 533                                  * get for each dunit what is it Speed_bin &
 534                                  * Target Frequency. From those both parameters
 535                                  * get the appropriate Cas_l from the CL table
 536                                  */
 537                                 cl_value =
 538                                         tm->interface_params[if_id].
 539                                         cas_l;
 540                                 cwl_val =
 541                                         tm->interface_params[if_id].
 542                                         cas_wl;
 543                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
 544                                                   ("cl_value 0x%x cwl_val 0x%x\n",
 545                                                    cl_value, cwl_val));
 546
 547                                 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
 548                                                            (speed_bin_index,
 549                                                             SPEED_BIN_TWR), t_ckclk);
 550
 551                                 data_value =
 552                                         ((cl_mask_table[cl_value] & 0x1) << 2) |
 553                                         ((cl_mask_table[cl_value] & 0xe) << 3);
 554                                 CHECK_STATUS(ddr3_tip_if_write
 555                                              (dev_num, access_type, if_id,
 556                                               MR0_REG, data_value,
 557                                               (0x7 << 4) | (1 << 2)));
 558                                 CHECK_STATUS(ddr3_tip_if_write
 559                                              (dev_num, access_type, if_id,
 560                                               MR0_REG, twr_mask_table[t_wr] << 9,
 561                                               0x7 << 9));
 562
 563                                 /*
 564                                  * MR1: Set RTT and DIC Design GL values
 565                                  * configured by user
 566                                  */
 567                                 CHECK_STATUS(ddr3_tip_if_write
 568                                              (dev_num, ACCESS_TYPE_MULTICAST,
 569                                               PARAM_NOT_CARE, MR1_REG,
 570                                               g_dic | g_rtt_nom, 0x266));
 571
 572                                 /* MR2 - Part of the Generic code */
 573                                 /*
 574                                  * The next configuration is done:
 575                                  * 1)  SRT
 576                                  * 2) CAS Write Latency
 577                                  */
 578                                 data_value = (cwl_mask_table[cwl_val] << 3);
 579                                 data_value |=
 580                                         ((tm->interface_params[if_id].
 581                                           interface_temp ==
 582                                           MV_DDR_TEMP_HIGH) ? (1 << 7) : 0);
 583                                 data_value |= g_rtt_wr;
 584                                 CHECK_STATUS(ddr3_tip_if_write
 585                                              (dev_num, access_type, if_id,
 586                                               MR2_REG, data_value,
 587                                               (0x7 << 3) | (0x1 << 7) | (0x3 <<
 588                                                                          9)));
 589                         }
 590
 591                         ddr3_tip_write_odt(dev_num, access_type, if_id,
 592                                            cl_value, cwl_val);
 593                         ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
 594
 595                         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
 596                                 CHECK_STATUS(ddr3_tip_if_write
 597                                              (dev_num, access_type, if_id,
 598                                               DUNIT_CTRL_HIGH_REG, 0x1000119,
 599                                               0x100017F));
 600                         } else {
 601                                 CHECK_STATUS(ddr3_tip_if_write
 602                                              (dev_num, access_type, if_id,
 603                                               DUNIT_CTRL_HIGH_REG, 0x600177 |
 604                                               (init_cntr_prm->is_ctrl64_bit ?
 605                                               CPU_INTERJECTION_ENA_SPLIT_ENA << CPU_INTERJECTION_ENA_OFFS :
 606                                               CPU_INTERJECTION_ENA_SPLIT_DIS << CPU_INTERJECTION_ENA_OFFS),
 607                                               0x1600177 | CPU_INTERJECTION_ENA_MASK <<
 608                                               CPU_INTERJECTION_ENA_OFFS));
 609                         }
 610
 611                         /* reset bit 7 */
 612                         CHECK_STATUS(ddr3_tip_if_write
 613                                      (dev_num, access_type, if_id,
 614                                       DUNIT_CTRL_HIGH_REG,
 615                                       (init_cntr_prm->msys_init << 7), (1 << 7)));
 616
 617                         timing = tm->interface_params[if_id].timing;
 618
 619                         if (mode_2t != 0xff) {
 620                                 t2t = mode_2t;
 621                         } else if (timing != MV_DDR_TIM_DEFAULT) {
 622                                 t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
 623                         } else {
 624                                 /* calculate number of CS (per interface) */
 625                                 cs_num = mv_ddr_cs_num_get();
 626                                 t2t = (cs_num == 1) ? 0 : 1;
 627                         }
 628
 629                         CHECK_STATUS(ddr3_tip_if_write
 630                                      (dev_num, access_type, if_id,
 631                                       DUNIT_CTRL_LOW_REG, t2t << 3,
 632                                       0x3 << 3));
 633                         CHECK_STATUS(ddr3_tip_if_write
 634                                      (dev_num, access_type, if_id,
 635                                       DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
 636                         CHECK_STATUS(ddr3_tip_if_write
 637                                      (dev_num, access_type, if_id,
 638                                       DDR_TIMING_REG, 0xa << 21, 0xff << 21));
 639
 640                         /* move the block to ddr3_tip_set_timing - end */
 641                         /* AUTO_ZQC_TIMING */
 642                         CHECK_STATUS(ddr3_tip_if_write
 643                                      (dev_num, access_type, if_id,
 644                                       ZQC_CFG_REG, (AUTO_ZQC_TIMING | (2 << 20)),
 645                                       0x3fffff));
 646                         CHECK_STATUS(ddr3_tip_if_read
 647                                      (dev_num, access_type, if_id,
 648                                       DRAM_PHY_CFG_REG, data_read, 0x30));
 649                         data_value =
 650                                 (data_read[if_id] == 0) ? (1 << 11) : 0;
 651                         CHECK_STATUS(ddr3_tip_if_write
 652                                      (dev_num, access_type, if_id,
 653                                       DUNIT_CTRL_HIGH_REG, data_value,
 654                                       (1 << 11)));
 655
 656                         /* Set Active control for ODT write transactions */
 657                         CHECK_STATUS(ddr3_tip_if_write
 658                                      (dev_num, ACCESS_TYPE_MULTICAST,
 659                                       PARAM_NOT_CARE, 0x1494, g_odt_config,
 660                                       MASK_ALL_BITS));
 661
 662                         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) {
 663                                 CHECK_STATUS(ddr3_tip_if_write
 664                                              (dev_num, access_type, if_id,
 665                                               0x14a8, 0x900, 0x900));
 666                                 /* wa: controls control sub-phy outputs floating during self-refresh */
 667                                 CHECK_STATUS(ddr3_tip_if_write
 668                                              (dev_num, access_type, if_id,
 669                                               0x16d0, 0, 0x8000));
 670                         }
 671                 }
 672         }
 673
 674         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
 675                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
 676                 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
 677
 678                 if (init_cntr_prm->do_mrs_phy)
 679                         ddr3_tip_pad_inv();
 680
 681                 /* Pad calibration control - disable */
 682                 CHECK_STATUS(ddr3_tip_if_write
 683                              (dev_num, access_type, if_id,
 684                               MAIN_PADS_CAL_MACH_CTRL_REG, 0x0, 0x1));
 685                 CHECK_STATUS(ddr3_tip_if_write
 686                              (dev_num, access_type, if_id,
 687                               MAIN_PADS_CAL_MACH_CTRL_REG,
 688                               calibration_update_control << 3, 0x3 << 3));
 689         }
 690
 691 #if defined(CONFIG_DDR4)
 692         /* dev_num, vref_en, pod_only */
 693         CHECK_STATUS(mv_ddr4_mode_regs_init(dev_num));
 694         CHECK_STATUS(mv_ddr4_sdram_config(dev_num));
 695 #endif /* CONFIG_DDR4 */
 696
 697         if (delay_enable != 0) {
 698                 adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
 699                 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
 700         }
 701
 702         return MV_OK;
 703 }
 704
 705 /*
 706  * Rank Control Flow
 707  */
 708 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id)
 709 {
 710         u32 data_value = 0,  bus_cnt = 0;
 711         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 712         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 713
 714         for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
 715                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
 716                 data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt].
 717                               cs_bitmask;
 718
 719                 if (tm->interface_params[if_id].as_bus_params[bus_cnt].
 720                     mirror_enable_bitmask == 1) {
 721                         /*
 722                          * Check mirror_enable_bitmask
 723                          * If it is enabled, CS + 4 bit in a word to be '1'
 724                          */
 725                         if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
 726                              cs_bitmask & 0x1) != 0) {
 727                                 data_value |= tm->interface_params[if_id].
 728                                               as_bus_params[bus_cnt].
 729                                               mirror_enable_bitmask << 4;
 730                         }
 731
 732                         if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
 733                              cs_bitmask & 0x2) != 0) {
 734                                 data_value |= tm->interface_params[if_id].
 735                                               as_bus_params[bus_cnt].
 736                                               mirror_enable_bitmask << 5;
 737                         }
 738
 739                         if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
 740                              cs_bitmask & 0x4) != 0) {
 741                                 data_value |= tm->interface_params[if_id].
 742                                               as_bus_params[bus_cnt].
 743                                               mirror_enable_bitmask << 6;
 744                         }
 745
 746                         if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
 747                              cs_bitmask & 0x8) != 0) {
 748                                 data_value |= tm->interface_params[if_id].
 749                                               as_bus_params[bus_cnt].
 750                                               mirror_enable_bitmask << 7;
 751                         }
 752                 }
 753         }
 754
 755         CHECK_STATUS(ddr3_tip_if_write
 756                      (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
 757                       data_value, 0xff));
 758
 759         return MV_OK;
 760 }
 761
 762 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id)
 763 {
 764         u32 data_value = 0, bus_cnt;
 765         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
 766         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 767
 768         for (bus_cnt = 1; bus_cnt < octets_per_if_num; bus_cnt++) {
 769                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
 770                 if ((tm->interface_params[if_id].
 771                      as_bus_params[0].cs_bitmask !=
 772                      tm->interface_params[if_id].
 773                      as_bus_params[bus_cnt].cs_bitmask) ||
 774                     (tm->interface_params[if_id].
 775                      as_bus_params[0].mirror_enable_bitmask !=
 776                      tm->interface_params[if_id].
 777                      as_bus_params[bus_cnt].mirror_enable_bitmask))
 778                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
 779                                           ("WARNING:Wrong configuration for pup #%d CS mask and CS mirroring for all pups should be the same\n",
 780                                            bus_cnt));
 781         }
 782
 783         data_value |= tm->interface_params[if_id].
 784                 as_bus_params[0].cs_bitmask;
 785         data_value |= tm->interface_params[if_id].
 786                 as_bus_params[0].mirror_enable_bitmask << 4;
 787
 788         CHECK_STATUS(ddr3_tip_if_write
 789                      (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
 790                       data_value, 0xff));
 791
 792         return MV_OK;
 793 }
 794
 795 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
 796 {
 797         if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2)
 798                 return ddr3_tip_rev2_rank_control(dev_num, if_id);
 799         else
 800                 return ddr3_tip_rev3_rank_control(dev_num, if_id);
 801 }
 802
 803 /*
 804  * Algorithm Parameters Validation
 805  */
 806 int ddr3_tip_validate_algo_var(u32 value, u32 fail_value, char *var_name)
 807 {
 808         if (value == fail_value) {
 809                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
 810                                   ("Error: %s is not initialized (Algo Components Validation)\n",
 811                                    var_name));
 812                 return 0;
 813         }
 814
 815         return 1;
 816 }
 817
 818 int ddr3_tip_validate_algo_ptr(void *ptr, void *fail_value, char *ptr_name)
 819 {
 820         if (ptr == fail_value) {
 821                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
 822                                   ("Error: %s is not initialized (Algo Components Validation)\n",
 823                                    ptr_name));
 824                 return 0;
 825         }
 826
 827         return 1;
 828 }
 829
 830 int ddr3_tip_validate_algo_components(u8 dev_num)
 831 {
 832         int status = 1;
 833
 834         /* Check DGL parameters*/
 835         status &= ddr3_tip_validate_algo_var(ck_delay, PARAM_UNDEFINED, "ck_delay");
 836         status &= ddr3_tip_validate_algo_var(phy_reg3_val, PARAM_UNDEFINED, "phy_reg3_val");
 837         status &= ddr3_tip_validate_algo_var(g_rtt_nom, PARAM_UNDEFINED, "g_rtt_nom");
 838         status &= ddr3_tip_validate_algo_var(g_dic, PARAM_UNDEFINED, "g_dic");
 839         status &= ddr3_tip_validate_algo_var(odt_config, PARAM_UNDEFINED, "odt_config");
 840         status &= ddr3_tip_validate_algo_var(g_zpri_data, PARAM_UNDEFINED, "g_zpri_data");
 841         status &= ddr3_tip_validate_algo_var(g_znri_data, PARAM_UNDEFINED, "g_znri_data");
 842         status &= ddr3_tip_validate_algo_var(g_zpri_ctrl, PARAM_UNDEFINED, "g_zpri_ctrl");
 843         status &= ddr3_tip_validate_algo_var(g_znri_ctrl, PARAM_UNDEFINED, "g_znri_ctrl");
 844         status &= ddr3_tip_validate_algo_var(g_zpodt_data, PARAM_UNDEFINED, "g_zpodt_data");
 845         status &= ddr3_tip_validate_algo_var(g_znodt_data, PARAM_UNDEFINED, "g_znodt_data");
 846         status &= ddr3_tip_validate_algo_var(g_zpodt_ctrl, PARAM_UNDEFINED, "g_zpodt_ctrl");
 847         status &= ddr3_tip_validate_algo_var(g_znodt_ctrl, PARAM_UNDEFINED, "g_znodt_ctrl");
 848
 849         /* Check functions pointers */
 850         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func,
 851                                              NULL, "tip_dunit_mux_select_func");
 852         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write,
 853                                              NULL, "mv_ddr_dunit_write");
 854         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read,
 855                                              NULL, "mv_ddr_dunit_read");
 856         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write,
 857                                              NULL, "mv_ddr_phy_write");
 858         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read,
 859                                              NULL, "mv_ddr_phy_read");
 860         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func,
 861                                              NULL, "tip_get_freq_config_info_func");
 862         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func,
 863                                              NULL, "tip_set_freq_divider_func");
 864         status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio,
 865                                              NULL, "tip_get_clock_ratio");
 866
 867         status &= ddr3_tip_validate_algo_ptr(dq_map_table, NULL, "dq_map_table");
 868         status &= ddr3_tip_validate_algo_var(dfs_low_freq, 0, "dfs_low_freq");
 869
 870         return (status == 1) ? MV_OK : MV_NOT_INITIALIZED;
 871 }
 872
 873
 874 int ddr3_pre_algo_config(void)
 875 {
 876         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 877
 878         /* Set Bus3 ECC training mode */
 879         if (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) {
 880                 /* Set Bus3 ECC MUX */
 881                 CHECK_STATUS(ddr3_tip_if_write
 882                              (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
 883                               DRAM_PINS_MUX_REG, 0x100, 0x100));
 884         }
 885
 886         /* Set regular ECC training mode (bus4 and bus 3) */
 887         if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
 888             (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) ||
 889             (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) {
 890                 /* Enable ECC Write MUX */
 891                 CHECK_STATUS(ddr3_tip_if_write
 892                              (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
 893                               TRAINING_SW_2_REG, 0x100, 0x100));
 894                 /* General ECC enable */
 895                 CHECK_STATUS(ddr3_tip_if_write
 896                              (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
 897                               SDRAM_CFG_REG, 0x40000, 0x40000));
 898                 /* Disable Read Data ECC MUX */
 899                 CHECK_STATUS(ddr3_tip_if_write
 900                              (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
 901                               TRAINING_SW_2_REG, 0x0, 0x2));
 902         }
 903
 904         return MV_OK;
 905 }
 906
 907 int ddr3_post_algo_config(void)
 908 {
 909         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
 910         int status;
 911
 912         status = ddr3_post_run_alg();
 913         if (MV_OK != status) {
 914                 printf("DDR3 Post Run Alg - FAILED 0x%x\n", status);
 915                 return status;
 916         }
 917
 918         /* Un_set ECC training mode */
 919         if ((DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask)) ||
 920             (DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask)) ||
 921             (DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))) {
 922                 /* Disable ECC Write MUX */
 923                 CHECK_STATUS(ddr3_tip_if_write
 924                              (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
 925                               TRAINING_SW_2_REG, 0x0, 0x100));
 926                 /* General ECC and Bus3 ECC MUX remains enabled */
 927         }
 928
 929         return MV_OK;
 930 }
 931
 932 /*
 933  * Run Training Flow
 934  */
 935 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)
 936 {
 937         int status = MV_OK;
 938
 939         status = ddr3_pre_algo_config();
 940         if (MV_OK != status) {
 941                 printf("DDR3 Pre Algo Config - FAILED 0x%x\n", status);
 942                 return status;
 943         }
 944
 945 #ifdef ODT_TEST_SUPPORT
 946         if (finger_test == 1)
 947                 return odt_test(dev_num, algo_type);
 948 #endif
 949
 950         if (algo_type == ALGO_TYPE_DYNAMIC) {
 951                 status = ddr3_tip_ddr3_auto_tune(dev_num);
 952         }
 953
 954         if (status != MV_OK) {
 955                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
 956                                   ("********   DRAM initialization Failed (res 0x%x)   ********\n",
 957                                    status));
 958                 return status;
 959         }
 960
 961         status = ddr3_post_algo_config();
 962         if (MV_OK != status) {
 963                 printf("DDR3 Post Algo Config - FAILED 0x%x\n", status);
 964                 return status;
 965         }
 966
 967         return status;
 968 }
 969
 970 #ifdef ODT_TEST_SUPPORT
 971 /*
 972  * ODT Test
 973  */
 974 static int odt_test(u32 dev_num, enum hws_algo_type algo_type)
 975 {
 976         int ret = MV_OK, ret_tune = MV_OK;
 977         int pfinger_val = 0, nfinger_val;
 978
 979         for (pfinger_val = p_finger_start; pfinger_val <= p_finger_end;
 980              pfinger_val += p_finger_step) {
 981                 for (nfinger_val = n_finger_start; nfinger_val <= n_finger_end;
 982                      nfinger_val += n_finger_step) {
 983                         if (finger_test != 0) {
 984                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
 985                                                   ("pfinger_val %d nfinger_val %d\n",
 986                                                    pfinger_val, nfinger_val));
 987                                 /*
 988                                  * TODO: need to check the correctness
 989                                  * of the following two lines.
 990                                  */
 991                                 g_zpodt_data = pfinger_val;
 992                                 g_znodt_data = nfinger_val;
 993                         }
 994
 995                         if (algo_type == ALGO_TYPE_DYNAMIC) {
 996                                 ret = ddr3_tip_ddr3_auto_tune(dev_num);
 997                         }
 998                 }
 999         }
1000
1001         if (ret_tune != MV_OK) {
1002                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1003                                   ("Run_alg: tuning failed %d\n", ret_tune));
1004                 ret = (ret == MV_OK) ? ret_tune : ret;
1005         }
1006
1007         return ret;
1008 }
1009 #endif
1010
1011 /*
1012  * Select Controller
1013  */
1014 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)
1015 {
1016         return config_func_info[dev_num].
1017                 tip_dunit_mux_select_func((u8)dev_num, enable);
1018 }
1019
1020 /*
1021  * Dunit Register Write
1022  */
1023 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
1024                       u32 if_id, u32 reg_addr, u32 data_value, u32 mask)
1025 {
1026         config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value);
1027
1028         return MV_OK;
1029 }
1030
1031 /*
1032  * Dunit Register Read
1033  */
1034 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
1035                      u32 if_id, u32 reg_addr, u32 *data, u32 mask)
1036 {
1037         config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data);
1038
1039         return MV_OK;
1040 }
1041
1042 /*
1043  * Dunit Register Polling
1044  */
1045 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
1046                         u32 if_id, u32 exp_value, u32 mask, u32 offset,
1047                         u32 poll_tries)
1048 {
1049         u32 poll_cnt = 0, interface_num = 0, start_if, end_if;
1050         u32 read_data[MAX_INTERFACE_NUM];
1051         int ret;
1052         int is_fail = 0, is_if_fail;
1053         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1054
1055         if (access_type == ACCESS_TYPE_MULTICAST) {
1056                 start_if = 0;
1057                 end_if = MAX_INTERFACE_NUM - 1;
1058         } else {
1059                 start_if = if_id;
1060                 end_if = if_id;
1061         }
1062
1063         for (interface_num = start_if; interface_num <= end_if; interface_num++) {
1064                 /* polling bit 3 for n times */
1065                 VALIDATE_IF_ACTIVE(tm->if_act_mask, interface_num);
1066
1067                 is_if_fail = 0;
1068                 for (poll_cnt = 0; poll_cnt < poll_tries; poll_cnt++) {
1069                         ret =
1070                                 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
1071                                                  interface_num, offset, read_data,
1072                                                  mask);
1073                         if (ret != MV_OK)
1074                                 return ret;
1075
1076                         if (read_data[interface_num] == exp_value)
1077                                 break;
1078                 }
1079
1080                 if (poll_cnt >= poll_tries) {
1081                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1082                                           ("max poll IF #%d\n", interface_num));
1083                         is_fail = 1;
1084                         is_if_fail = 1;
1085                 }
1086
1087                 training_result[training_stage][interface_num] =
1088                         (is_if_fail == 1) ? TEST_FAILED : TEST_SUCCESS;
1089         }
1090
1091         return (is_fail == 0) ? MV_OK : MV_FAIL;
1092 }
1093
1094 /*
1095  * Bus read access
1096  */
1097 int ddr3_tip_bus_read(u32 dev_num, u32 if_id,
1098                       enum hws_access_type phy_access, u32 phy_id,
1099                       enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data)
1100 {
1101         return config_func_info[dev_num].
1102                 mv_ddr_phy_read(phy_access, phy_id, phy_type, reg_addr, data);
1103 }
1104
1105 /*
1106  * Bus write access
1107  */
1108 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
1109                        u32 if_id, enum hws_access_type phy_access,
1110                        u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
1111                        u32 data_value)
1112 {
1113         return config_func_info[dev_num].
1114                 mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE);
1115 }
1116
1117
1118 /*
1119  * Phy read-modify-write
1120  */
1121 int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,
1122                                    u32 interface_id, u32 phy_id,
1123                                    enum hws_ddr_phy phy_type, u32 reg_addr,
1124                                    u32 data_value, u32 reg_mask)
1125 {
1126         u32 data_val = 0, if_id, start_if, end_if;
1127         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1128
1129         if (access_type == ACCESS_TYPE_MULTICAST) {
1130                 start_if = 0;
1131                 end_if = MAX_INTERFACE_NUM - 1;
1132         } else {
1133                 start_if = interface_id;
1134                 end_if = interface_id;
1135         }
1136
1137         for (if_id = start_if; if_id <= end_if; if_id++) {
1138                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1139                 CHECK_STATUS(ddr3_tip_bus_read
1140                              (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id,
1141                               phy_type, reg_addr, &data_val));
1142                 data_value = (data_val & (~reg_mask)) | (data_value & reg_mask);
1143                 CHECK_STATUS(ddr3_tip_bus_write
1144                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
1145                               ACCESS_TYPE_UNICAST, phy_id, phy_type, reg_addr,
1146                               data_value));
1147         }
1148
1149         return MV_OK;
1150 }
1151
1152 /*
1153  * ADLL Calibration
1154  */
1155 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
1156                      u32 if_id, enum mv_ddr_freq frequency)
1157 {
1158         struct hws_tip_freq_config_info freq_config_info;
1159         u32 bus_cnt = 0;
1160         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1161         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1162
1163         /* Reset Diver_b assert -> de-assert */
1164         CHECK_STATUS(ddr3_tip_if_write
1165                      (dev_num, access_type, if_id, SDRAM_CFG_REG,
1166                       0, 0x10000000));
1167         mdelay(10);
1168         CHECK_STATUS(ddr3_tip_if_write
1169                      (dev_num, access_type, if_id, SDRAM_CFG_REG,
1170                       0x10000000, 0x10000000));
1171
1172         CHECK_STATUS(config_func_info[dev_num].
1173                      tip_get_freq_config_info_func((u8)dev_num, frequency,
1174                                                    &freq_config_info));
1175
1176         for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
1177                 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
1178                 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1179                              (dev_num, access_type, if_id, bus_cnt,
1180                               DDR_PHY_DATA, ADLL_CFG0_PHY_REG,
1181                               freq_config_info.bw_per_freq << 8, 0x700));
1182                 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1183                              (dev_num, access_type, if_id, bus_cnt,
1184                               DDR_PHY_DATA, ADLL_CFG2_PHY_REG,
1185                               freq_config_info.rate_per_freq, 0x7));
1186         }
1187
1188         for (bus_cnt = 0; bus_cnt < DDR_IF_CTRL_SUBPHYS_NUM; bus_cnt++) {
1189                 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1190                              (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1191                               DDR_PHY_CONTROL, ADLL_CFG0_PHY_REG,
1192                               freq_config_info.bw_per_freq << 8, 0x700));
1193                 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1194                              (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1195                               DDR_PHY_CONTROL, ADLL_CFG2_PHY_REG,
1196                               freq_config_info.rate_per_freq, 0x7));
1197         }
1198
1199         /* DUnit to Phy drive post edge, ADLL reset assert de-assert */
1200         CHECK_STATUS(ddr3_tip_if_write
1201                      (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1202                       0, (0x80000000 | 0x40000000)));
1203         mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ));
1204         CHECK_STATUS(ddr3_tip_if_write
1205                      (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1206                       (0x80000000 | 0x40000000), (0x80000000 | 0x40000000)));
1207
1208         /* polling for ADLL Done */
1209         if (ddr3_tip_if_polling(dev_num, access_type, if_id,
1210                                 0x3ff03ff, 0x3ff03ff, PHY_LOCK_STATUS_REG,
1211                                 MAX_POLLING_ITERATIONS) != MV_OK) {
1212                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1213                                   ("Freq_set: DDR3 poll failed(1)"));
1214         }
1215
1216         /* pup data_pup reset assert-> deassert */
1217         CHECK_STATUS(ddr3_tip_if_write
1218                      (dev_num, access_type, if_id, SDRAM_CFG_REG,
1219                       0, 0x60000000));
1220         mdelay(10);
1221         CHECK_STATUS(ddr3_tip_if_write
1222                      (dev_num, access_type, if_id, SDRAM_CFG_REG,
1223                       0x60000000, 0x60000000));
1224
1225         return MV_OK;
1226 }
1227
1228 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
1229                       u32 if_id, enum mv_ddr_freq frequency)
1230 {
1231         u32 cl_value = 0, cwl_value = 0, mem_mask = 0, val = 0,
1232                 bus_cnt = 0, t_wr = 0, t_ckclk = 0,
1233                 cnt_id;
1234         u32 end_if, start_if;
1235         u32 bus_index = 0;
1236         int is_dll_off = 0;
1237         enum mv_ddr_speed_bin speed_bin_index = 0;
1238         struct hws_tip_freq_config_info freq_config_info;
1239         enum hws_result *flow_result = training_result[training_stage];
1240         u32 adll_tap = 0;
1241         u32 cs_num;
1242         u32 t2t;
1243         u32 cs_mask[MAX_INTERFACE_NUM];
1244         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1245         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1246         unsigned int tclk;
1247         enum mv_ddr_timing timing = tm->interface_params[if_id].timing;
1248         u32 freq = mv_ddr_freq_get(frequency);
1249
1250         DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1251                           ("dev %d access %d IF %d freq %d\n", dev_num,
1252                            access_type, if_id, frequency));
1253
1254         if (frequency == MV_DDR_FREQ_LOW_FREQ)
1255                 is_dll_off = 1;
1256         if (access_type == ACCESS_TYPE_MULTICAST) {
1257                 start_if = 0;
1258                 end_if = MAX_INTERFACE_NUM - 1;
1259         } else {
1260                 start_if = if_id;
1261                 end_if = if_id;
1262         }
1263
1264         /* calculate interface cs mask - Oferb 4/11 */
1265         /* speed bin can be different for each interface */
1266         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1267                 /* cs enable is active low */
1268                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1269                 cs_mask[if_id] = CS_BIT_MASK;
1270                 training_result[training_stage][if_id] = TEST_SUCCESS;
1271                 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
1272                                       &cs_mask[if_id]);
1273         }
1274
1275         /* speed bin can be different for each interface */
1276         /*
1277          * moti b - need to remove the loop for multicas access functions
1278          * and loop the unicast access functions
1279          */
1280         for (if_id = start_if; if_id <= end_if; if_id++) {
1281                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1282
1283                 flow_result[if_id] = TEST_SUCCESS;
1284                 speed_bin_index =
1285                         tm->interface_params[if_id].speed_bin_index;
1286                 if (tm->interface_params[if_id].memory_freq ==
1287                     frequency) {
1288                         cl_value =
1289                                 tm->interface_params[if_id].cas_l;
1290                         cwl_value =
1291                                 tm->interface_params[if_id].cas_wl;
1292                 } else if (tm->cfg_src == MV_DDR_CFG_SPD) {
1293                         tclk = 1000000 / freq;
1294                         cl_value = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
1295                         if (cl_value == 0) {
1296                                 printf("mv_ddr: unsupported cas latency value found\n");
1297                                 return MV_FAIL;
1298                         }
1299                         cwl_value = mv_ddr_cwl_calc(tclk);
1300                         if (cwl_value == 0) {
1301                                 printf("mv_ddr: unsupported cas write latency value found\n");
1302                                 return MV_FAIL;
1303                         }
1304                 } else {
1305                         cl_value = mv_ddr_cl_val_get(speed_bin_index, frequency);
1306                         cwl_value = mv_ddr_cwl_val_get(speed_bin_index, frequency);
1307                 }
1308
1309                 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1310                                   ("Freq_set dev 0x%x access 0x%x if 0x%x freq 0x%x speed %d:\n\t",
1311                                    dev_num, access_type, if_id,
1312                                    frequency, speed_bin_index));
1313
1314                 for (cnt_id = 0; cnt_id < MV_DDR_FREQ_LAST; cnt_id++) {
1315                         DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
1316                                           ("%d ", mv_ddr_cl_val_get(speed_bin_index, cnt_id)));
1317                 }
1318
1319                 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE, ("\n"));
1320                 mem_mask = 0;
1321                 for (bus_index = 0; bus_index < octets_per_if_num;
1322                      bus_index++) {
1323                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
1324                         mem_mask |=
1325                                 tm->interface_params[if_id].
1326                                 as_bus_params[bus_index].mirror_enable_bitmask;
1327                 }
1328
1329                 if (mem_mask != 0) {
1330                         /* motib redundent in KW28 */
1331                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1332                                                        if_id,
1333                                                        DUAL_DUNIT_CFG_REG, 0, 0x8));
1334                 }
1335
1336                 /* dll state after exiting SR */
1337                 if (is_dll_off == 1) {
1338                         CHECK_STATUS(ddr3_tip_if_write
1339                                      (dev_num, access_type, if_id,
1340                                       DFS_REG, 0x1, 0x1));
1341                 } else {
1342                         CHECK_STATUS(ddr3_tip_if_write
1343                                      (dev_num, access_type, if_id,
1344                                       DFS_REG, 0, 0x1));
1345                 }
1346
1347                 CHECK_STATUS(ddr3_tip_if_write
1348                              (dev_num, access_type, if_id,
1349                               DUNIT_MMASK_REG, 0, 0x1));
1350                 /* DFS  - block  transactions */
1351                 CHECK_STATUS(ddr3_tip_if_write
1352                              (dev_num, access_type, if_id,
1353                               DFS_REG, 0x2, 0x2));
1354
1355                 /* disable ODT in case of dll off */
1356                 if (is_dll_off == 1) {
1357 #if defined(CONFIG_DDR4)
1358                         CHECK_STATUS(ddr3_tip_if_read
1359                                      (dev_num, access_type, PARAM_NOT_CARE,
1360                                       0x1974, &g_rtt_nom_cs0, MASK_ALL_BITS));
1361                         CHECK_STATUS(ddr3_tip_if_write
1362                                      (dev_num, access_type, if_id,
1363                                       0x1974, 0, (0x7 << 8)));
1364                         CHECK_STATUS(ddr3_tip_if_read
1365                                      (dev_num, access_type, PARAM_NOT_CARE,
1366                                       0x1A74, &g_rtt_nom_cs1, MASK_ALL_BITS));
1367                         CHECK_STATUS(ddr3_tip_if_write
1368                                      (dev_num, access_type, if_id,
1369                                       0x1A74, 0, (0x7 << 8)));
1370 #else /* CONFIG_DDR4 */
1371                         CHECK_STATUS(ddr3_tip_if_write
1372                                      (dev_num, access_type, if_id,
1373                                       0x1874, 0, 0x244));
1374                         CHECK_STATUS(ddr3_tip_if_write
1375                                      (dev_num, access_type, if_id,
1376                                       0x1884, 0, 0x244));
1377                         CHECK_STATUS(ddr3_tip_if_write
1378                                      (dev_num, access_type, if_id,
1379                                       0x1894, 0, 0x244));
1380                         CHECK_STATUS(ddr3_tip_if_write
1381                                      (dev_num, access_type, if_id,
1382                                       0x18a4, 0, 0x244));
1383 #endif /* CONFIG_DDR4 */
1384                 }
1385
1386                 /* DFS  - Enter Self-Refresh */
1387                 CHECK_STATUS(ddr3_tip_if_write
1388                              (dev_num, access_type, if_id, DFS_REG, 0x4,
1389                               0x4));
1390                 /* polling on self refresh entry */
1391                 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST,
1392                                         if_id, 0x8, 0x8, DFS_REG,
1393                                         MAX_POLLING_ITERATIONS) != MV_OK) {
1394                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1395                                           ("Freq_set: DDR3 poll failed on SR entry\n"));
1396                 }
1397
1398                 /* Calculate 2T mode */
1399                 if (mode_2t != 0xff) {
1400                         t2t = mode_2t;
1401                 } else if (timing != MV_DDR_TIM_DEFAULT) {
1402                         t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
1403                 } else {
1404                         /* Calculate number of CS per interface */
1405                         cs_num = mv_ddr_cs_num_get();
1406                         t2t = (cs_num == 1) ? 0 : 1;
1407                 }
1408
1409
1410                 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
1411                         /* Use 1T mode if 1:1 ratio configured */
1412                         if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
1413                                 /* Low freq*/
1414                                 CHECK_STATUS(ddr3_tip_if_write
1415                                              (dev_num, access_type, if_id,
1416                                               SDRAM_OPEN_PAGES_CTRL_REG, 0x0, 0x3C0));
1417                                 t2t = 0;
1418                         } else {
1419                                 /* Middle or target freq */
1420                                 CHECK_STATUS(ddr3_tip_if_write
1421                                              (dev_num, access_type, if_id,
1422                                               SDRAM_OPEN_PAGES_CTRL_REG, 0x3C0, 0x3C0));
1423                         }
1424                 }
1425                 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1426                                                DUNIT_CTRL_LOW_REG, t2t << 3, 0x3 << 3));
1427
1428                 /* PLL configuration */
1429                 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id,
1430                                                                     frequency);
1431
1432                 /* DFS  - CL/CWL/WR parameters after exiting SR */
1433                 CHECK_STATUS(ddr3_tip_if_write
1434                              (dev_num, access_type, if_id, DFS_REG,
1435                               (cl_mask_table[cl_value] << 8), 0xf00));
1436                 CHECK_STATUS(ddr3_tip_if_write
1437                              (dev_num, access_type, if_id, DFS_REG,
1438                               (cwl_mask_table[cwl_value] << 12), 0x7000));
1439
1440                 t_ckclk = (MEGA / freq);
1441                 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
1442                                            (speed_bin_index,
1443                                             SPEED_BIN_TWR), t_ckclk);
1444
1445                 CHECK_STATUS(ddr3_tip_if_write
1446                              (dev_num, access_type, if_id, DFS_REG,
1447                               (twr_mask_table[t_wr] << 16), 0x70000));
1448
1449                 /* Restore original RTT values if returning from DLL OFF mode */
1450                 if (is_dll_off == 1) {
1451 #if defined(CONFIG_DDR4)
1452                         CHECK_STATUS(ddr3_tip_if_write
1453                                      (dev_num, access_type, if_id,
1454                                       0x1974, g_rtt_nom_cs0, (0x7 << 8)));
1455                         CHECK_STATUS(ddr3_tip_if_write
1456                                      (dev_num, access_type, if_id,
1457                                       0x1A74, g_rtt_nom_cs1, (0x7 << 8)));
1458
1459                         mv_ddr4_mode_regs_init(dev_num);
1460 #else /* CONFIG_DDR4 */
1461                         CHECK_STATUS(ddr3_tip_if_write
1462                                      (dev_num, access_type, if_id, 0x1874,
1463                                       g_dic | g_rtt_nom, 0x266));
1464                         CHECK_STATUS(ddr3_tip_if_write
1465                                      (dev_num, access_type, if_id, 0x1884,
1466                                       g_dic | g_rtt_nom, 0x266));
1467                         CHECK_STATUS(ddr3_tip_if_write
1468                                      (dev_num, access_type, if_id, 0x1894,
1469                                       g_dic | g_rtt_nom, 0x266));
1470                         CHECK_STATUS(ddr3_tip_if_write
1471                                      (dev_num, access_type, if_id, 0x18a4,
1472                                       g_dic | g_rtt_nom, 0x266));
1473 #endif /* CONFIG_DDR4 */
1474                 }
1475
1476                 /* Reset divider_b assert -> de-assert */
1477                 CHECK_STATUS(ddr3_tip_if_write
1478                              (dev_num, access_type, if_id,
1479                               SDRAM_CFG_REG, 0, 0x10000000));
1480                 mdelay(10);
1481                 CHECK_STATUS(ddr3_tip_if_write
1482                              (dev_num, access_type, if_id,
1483                               SDRAM_CFG_REG, 0x10000000, 0x10000000));
1484
1485                 /* ADLL configuration function of process and frequency */
1486                 CHECK_STATUS(config_func_info[dev_num].
1487                              tip_get_freq_config_info_func(dev_num, frequency,
1488                                                            &freq_config_info));
1489
1490                 /* TBD check milo5 using device ID ? */
1491                 for (bus_cnt = 0; bus_cnt < octets_per_if_num;
1492                      bus_cnt++) {
1493                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
1494                         CHECK_STATUS(ddr3_tip_bus_read_modify_write
1495                                      (dev_num, ACCESS_TYPE_UNICAST,
1496                                       if_id, bus_cnt, DDR_PHY_DATA,
1497                                       0x92,
1498                                       freq_config_info.
1499                                       bw_per_freq << 8
1500                                       /*freq_mask[dev_num][frequency] << 8 */
1501                                       , 0x700));
1502                         CHECK_STATUS(ddr3_tip_bus_read_modify_write
1503                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
1504                                       bus_cnt, DDR_PHY_DATA, 0x94,
1505                                       freq_config_info.rate_per_freq, 0x7));
1506                 }
1507
1508                 /* Dunit to PHY drive post edge, ADLL reset assert -> de-assert */
1509                 CHECK_STATUS(ddr3_tip_if_write
1510                              (dev_num, access_type, if_id,
1511                               DRAM_PHY_CFG_REG, 0,
1512                               (0x80000000 | 0x40000000)));
1513                 mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)));
1514                 CHECK_STATUS(ddr3_tip_if_write
1515                              (dev_num, access_type, if_id,
1516                               DRAM_PHY_CFG_REG, (0x80000000 | 0x40000000),
1517                               (0x80000000 | 0x40000000)));
1518
1519                 /* polling for ADLL Done */
1520                 if (ddr3_tip_if_polling
1521                     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff,
1522                      0x3ff03ff, PHY_LOCK_STATUS_REG,
1523                      MAX_POLLING_ITERATIONS) != MV_OK) {
1524                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1525                                           ("Freq_set: DDR3 poll failed(1)\n"));
1526                 }
1527
1528                 /* pup data_pup reset assert-> deassert */
1529                 CHECK_STATUS(ddr3_tip_if_write
1530                              (dev_num, access_type, if_id,
1531                               SDRAM_CFG_REG, 0, 0x60000000));
1532                 mdelay(10);
1533                 CHECK_STATUS(ddr3_tip_if_write
1534                              (dev_num, access_type, if_id,
1535                               SDRAM_CFG_REG, 0x60000000, 0x60000000));
1536
1537                 /* Set proper timing params before existing Self-Refresh */
1538                 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
1539                 if (delay_enable != 0) {
1540                         adll_tap = (is_dll_off == 1) ? 1000 : (MEGA / (freq * 64));
1541                         ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
1542                 }
1543
1544                 /* Exit SR */
1545                 CHECK_STATUS(ddr3_tip_if_write
1546                              (dev_num, access_type, if_id, DFS_REG, 0,
1547                               0x4));
1548                 if (ddr3_tip_if_polling
1549                     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG,
1550                      MAX_POLLING_ITERATIONS) != MV_OK) {
1551                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1552                                           ("Freq_set: DDR3 poll failed(2)"));
1553                 }
1554
1555                 /* Refresh Command */
1556                 CHECK_STATUS(ddr3_tip_if_write
1557                              (dev_num, access_type, if_id,
1558                               SDRAM_OP_REG, 0x2, 0xf1f));
1559                 if (ddr3_tip_if_polling
1560                     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
1561                      SDRAM_OP_REG, MAX_POLLING_ITERATIONS) != MV_OK) {
1562                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1563                                           ("Freq_set: DDR3 poll failed(3)"));
1564                 }
1565
1566                 /* Release DFS Block */
1567                 CHECK_STATUS(ddr3_tip_if_write
1568                              (dev_num, access_type, if_id, DFS_REG, 0,
1569                               0x2));
1570                 /* Controller to MBUS Retry - normal */
1571                 CHECK_STATUS(ddr3_tip_if_write
1572                              (dev_num, access_type, if_id, DUNIT_MMASK_REG,
1573                               0x1, 0x1));
1574
1575                 /* MRO: Burst Length 8, CL , Auto_precharge 0x16cc */
1576                 val =
1577                         ((cl_mask_table[cl_value] & 0x1) << 2) |
1578                         ((cl_mask_table[cl_value] & 0xe) << 3);
1579                 CHECK_STATUS(ddr3_tip_if_write
1580                              (dev_num, access_type, if_id, MR0_REG,
1581                               val, (0x7 << 4) | (1 << 2)));
1582                 /* MR2:  CWL = 10 , Auto Self-Refresh - disable */
1583                 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;
1584                 /*
1585                  * nklein 24.10.13 - should not be here - leave value as set in
1586                  * the init configuration val |= (1 << 9);
1587                  * val |= ((tm->interface_params[if_id].
1588                  * interface_temp == MV_DDR_TEMP_HIGH) ? (1 << 7) : 0);
1589                  */
1590                 /* nklein 24.10.13 - see above comment */
1591                 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1592                                                if_id, MR2_REG,
1593                                                val, (0x7 << 3) | (0x3 << 9)));
1594
1595                 /* ODT TIMING */
1596                 val = ((cl_value - cwl_value + 1) << 4) |
1597                         ((cl_value - cwl_value + 6) << 8) |
1598                         ((cl_value - 1) << 12) | ((cl_value + 6) << 16);
1599                 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1600                                                if_id, DDR_ODT_TIMING_LOW_REG,
1601                                                val, 0xffff0));
1602                 val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1603                 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1604                                                if_id, DDR_ODT_TIMING_HIGH_REG,
1605                                                val, 0xffff));
1606
1607                 /* in case of ddr4 need to set the receiver to odt always 'on' (odt_config = '0')
1608                  * in case of ddr3 configure the odt through the timing
1609                  */
1610                 if (odt_config != 0) {
1611                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf));
1612                 }
1613                 else {
1614                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG,
1615                                                        0x30f, 0x30f));
1616                 }
1617
1618                 /* re-write CL */
1619                 val = ((cl_mask_table[cl_value] & 0x1) << 2) |
1620                         ((cl_mask_table[cl_value] & 0xe) << 3);
1621
1622                 cs_mask[0] = 0xc;
1623
1624                 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
1625                         val, (0x7 << 4) | (0x1 << 2)));
1626
1627                 /* re-write CWL */
1628                 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr;
1629                 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2,
1630                         val, (0x7 << 3) | (0x3 << 9)));
1631
1632                 if (mem_mask != 0) {
1633                         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1634                                                        if_id,
1635                                                        DUAL_DUNIT_CFG_REG,
1636                                                        1 << 3, 0x8));
1637                 }
1638         }
1639
1640         return MV_OK;
1641 }
1642
1643 /*
1644  * Set ODT values
1645  */
1646 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
1647                               u32 if_id, u32 cl_value, u32 cwl_value)
1648 {
1649         /* ODT TIMING */
1650         u32 val = (cl_value - cwl_value + 6);
1651
1652         val = ((cl_value - cwl_value + 1) << 4) | ((val & 0xf) << 8) |
1653                 (((cl_value - 1) & 0xf) << 12) |
1654                 (((cl_value + 6) & 0xf) << 16) | (((val & 0x10) >> 4) << 21);
1655         val |= (((cl_value - 1) >> 4) << 22) | (((cl_value + 6) >> 4) << 23);
1656
1657         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1658                                        DDR_ODT_TIMING_LOW_REG, val, 0xffff0));
1659         val = 0x91 | ((cwl_value - 1) << 8) | ((cwl_value + 5) << 12);
1660         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1661                                        DDR_ODT_TIMING_HIGH_REG, val, 0xffff));
1662         if (odt_additional == 1) {
1663                 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1664                                                if_id,
1665                                                SDRAM_ODT_CTRL_HIGH_REG,
1666                                                0xf, 0xf));
1667         }
1668
1669         /* ODT Active */
1670         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1671                                        DUNIT_ODT_CTRL_REG, 0xf, 0xf));
1672
1673         return MV_OK;
1674 }
1675
1676 /*
1677  * Set Timing values for training
1678  */
1679 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
1680                                u32 if_id, enum mv_ddr_freq frequency)
1681 {
1682         u32 t_ckclk = 0, t_ras = 0;
1683         u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0,
1684                 t_rfc = 0, t_mod = 0, t_r2r = 0x3, t_r2r_high = 0,
1685                 t_r2w_w2r = 0x3, t_r2w_w2r_high = 0x1, t_w2w = 0x3;
1686         u32 refresh_interval_cnt, t_hclk, t_refi, t_faw, t_pd, t_xpdll;
1687         u32 val = 0, page_size = 0, mask = 0;
1688         enum mv_ddr_speed_bin speed_bin_index;
1689         enum mv_ddr_die_capacity memory_size = MV_DDR_DIE_CAP_2GBIT;
1690         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1691         u32 freq = mv_ddr_freq_get(frequency);
1692
1693         speed_bin_index = tm->interface_params[if_id].speed_bin_index;
1694         memory_size = tm->interface_params[if_id].memory_size;
1695         page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size);
1696         t_ckclk = (MEGA / freq);
1697         /* HCLK in[ps] */
1698         t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency));
1699
1700         t_refi = (tm->interface_params[if_id].interface_temp == MV_DDR_TEMP_HIGH) ? TREFI_HIGH : TREFI_LOW;
1701         t_refi *= 1000; /* psec */
1702         refresh_interval_cnt = t_refi / t_hclk; /* no units */
1703
1704         if (page_size == 1) {
1705                 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW1K);
1706                 t_faw = time_to_nclk(t_faw, t_ckclk);
1707                 t_faw = GET_MAX_VALUE(20, t_faw);
1708         } else {        /* page size =2, we do not support page size 0.5k */
1709                 t_faw = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TFAW2K);
1710                 t_faw = time_to_nclk(t_faw, t_ckclk);
1711                 t_faw = GET_MAX_VALUE(28, t_faw);
1712         }
1713
1714         t_pd = GET_MAX_VALUE(t_ckclk * 3, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TPD));
1715         t_pd = time_to_nclk(t_pd, t_ckclk);
1716
1717         t_xpdll = GET_MAX_VALUE(t_ckclk * 10, mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TXPDLL));
1718         t_xpdll = time_to_nclk(t_xpdll, t_ckclk);
1719
1720         t_rrd = (page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index,
1721                                                    SPEED_BIN_TRRD1K) :
1722                 mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRD2K);
1723         t_rrd = GET_MAX_VALUE(t_ckclk * 4, t_rrd);
1724         t_rtp = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
1725                                                            SPEED_BIN_TRTP));
1726         t_mod = GET_MAX_VALUE(t_ckclk * 12, 15000);
1727 #if defined(CONFIG_DDR4)
1728         t_wtr = GET_MAX_VALUE(t_ckclk * 2, mv_ddr_speed_bin_timing_get(speed_bin_index,
1729                                                            SPEED_BIN_TWTR));
1730 #else /* CONFIG_DDR4 */
1731         t_wtr = GET_MAX_VALUE(t_ckclk * 4, mv_ddr_speed_bin_timing_get(speed_bin_index,
1732                                                            SPEED_BIN_TWTR));
1733 #endif /* CONFIG_DDR4 */
1734         t_ras = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1735                                                     SPEED_BIN_TRAS),
1736                                     t_ckclk);
1737         t_rcd = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1738                                                     SPEED_BIN_TRCD),
1739                                     t_ckclk);
1740         t_rp = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1741                                                    SPEED_BIN_TRP),
1742                                    t_ckclk);
1743         t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index,
1744                                                    SPEED_BIN_TWR),
1745                                    t_ckclk);
1746         t_wtr = time_to_nclk(t_wtr, t_ckclk);
1747         t_rrd = time_to_nclk(t_rrd, t_ckclk);
1748         t_rtp = time_to_nclk(t_rtp, t_ckclk);
1749         t_rfc = time_to_nclk(mv_ddr_rfc_get(memory_size) * 1000, t_ckclk);
1750         t_mod = time_to_nclk(t_mod, t_ckclk);
1751
1752         /* SDRAM Timing Low */
1753         val = (((t_ras - 1) & SDRAM_TIMING_LOW_TRAS_MASK) << SDRAM_TIMING_LOW_TRAS_OFFS) |
1754               (((t_rcd - 1) & SDRAM_TIMING_LOW_TRCD_MASK) << SDRAM_TIMING_LOW_TRCD_OFFS) |
1755               (((t_rcd - 1) >> SDRAM_TIMING_LOW_TRCD_OFFS & SDRAM_TIMING_HIGH_TRCD_MASK)
1756               << SDRAM_TIMING_HIGH_TRCD_OFFS) |
1757               (((t_rp - 1) & SDRAM_TIMING_LOW_TRP_MASK) << SDRAM_TIMING_LOW_TRP_OFFS) |
1758               (((t_rp - 1) >> SDRAM_TIMING_LOW_TRP_MASK & SDRAM_TIMING_HIGH_TRP_MASK)
1759               << SDRAM_TIMING_HIGH_TRP_OFFS) |
1760               (((t_wr - 1) & SDRAM_TIMING_LOW_TWR_MASK) << SDRAM_TIMING_LOW_TWR_OFFS) |
1761               (((t_wtr - 1) & SDRAM_TIMING_LOW_TWTR_MASK) << SDRAM_TIMING_LOW_TWTR_OFFS) |
1762               ((((t_ras - 1) >> 4) & SDRAM_TIMING_LOW_TRAS_HIGH_MASK) << SDRAM_TIMING_LOW_TRAS_HIGH_OFFS) |
1763               (((t_rrd - 1) & SDRAM_TIMING_LOW_TRRD_MASK) << SDRAM_TIMING_LOW_TRRD_OFFS) |
1764               (((t_rtp - 1) & SDRAM_TIMING_LOW_TRTP_MASK) << SDRAM_TIMING_LOW_TRTP_OFFS);
1765
1766         mask = (SDRAM_TIMING_LOW_TRAS_MASK << SDRAM_TIMING_LOW_TRAS_OFFS) |
1767                (SDRAM_TIMING_LOW_TRCD_MASK << SDRAM_TIMING_LOW_TRCD_OFFS) |
1768                (SDRAM_TIMING_HIGH_TRCD_MASK << SDRAM_TIMING_HIGH_TRCD_OFFS) |
1769                (SDRAM_TIMING_LOW_TRP_MASK << SDRAM_TIMING_LOW_TRP_OFFS) |
1770                (SDRAM_TIMING_HIGH_TRP_MASK << SDRAM_TIMING_HIGH_TRP_OFFS) |
1771                (SDRAM_TIMING_LOW_TWR_MASK << SDRAM_TIMING_LOW_TWR_OFFS) |
1772                (SDRAM_TIMING_LOW_TWTR_MASK << SDRAM_TIMING_LOW_TWTR_OFFS) |
1773                (SDRAM_TIMING_LOW_TRAS_HIGH_MASK << SDRAM_TIMING_LOW_TRAS_HIGH_OFFS) |
1774                (SDRAM_TIMING_LOW_TRRD_MASK << SDRAM_TIMING_LOW_TRRD_OFFS) |
1775                (SDRAM_TIMING_LOW_TRTP_MASK << SDRAM_TIMING_LOW_TRTP_OFFS);
1776
1777         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1778                                        SDRAM_TIMING_LOW_REG, val, mask));
1779
1780         /* SDRAM Timing High */
1781         val = 0;
1782         mask = 0;
1783
1784         val = (((t_rfc - 1) & SDRAM_TIMING_HIGH_TRFC_MASK) << SDRAM_TIMING_HIGH_TRFC_OFFS) |
1785               ((t_r2r & SDRAM_TIMING_HIGH_TR2R_MASK) << SDRAM_TIMING_HIGH_TR2R_OFFS) |
1786               ((t_r2w_w2r & SDRAM_TIMING_HIGH_TR2W_W2R_MASK) << SDRAM_TIMING_HIGH_TR2W_W2R_OFFS) |
1787               ((t_w2w & SDRAM_TIMING_HIGH_TW2W_MASK) << SDRAM_TIMING_HIGH_TW2W_OFFS) |
1788               ((((t_rfc - 1) >> 7) & SDRAM_TIMING_HIGH_TRFC_HIGH_MASK) << SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS) |
1789               ((t_r2r_high & SDRAM_TIMING_HIGH_TR2R_HIGH_MASK) << SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS) |
1790               ((t_r2w_w2r_high & SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK) << SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS) |
1791               (((t_mod - 1) & SDRAM_TIMING_HIGH_TMOD_MASK) << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1792               ((((t_mod - 1) >> 4) & SDRAM_TIMING_HIGH_TMOD_HIGH_MASK) << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1793
1794         mask = (SDRAM_TIMING_HIGH_TRFC_MASK << SDRAM_TIMING_HIGH_TRFC_OFFS) |
1795                (SDRAM_TIMING_HIGH_TR2R_MASK << SDRAM_TIMING_HIGH_TR2R_OFFS) |
1796                (SDRAM_TIMING_HIGH_TR2W_W2R_MASK << SDRAM_TIMING_HIGH_TR2W_W2R_OFFS) |
1797                (SDRAM_TIMING_HIGH_TW2W_MASK << SDRAM_TIMING_HIGH_TW2W_OFFS) |
1798                (SDRAM_TIMING_HIGH_TRFC_HIGH_MASK << SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS) |
1799                (SDRAM_TIMING_HIGH_TR2R_HIGH_MASK << SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS) |
1800                (SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK << SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS) |
1801                (SDRAM_TIMING_HIGH_TMOD_MASK << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1802                (SDRAM_TIMING_HIGH_TMOD_HIGH_MASK << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1803
1804         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1805                                        SDRAM_TIMING_HIGH_REG, val, mask));
1806
1807         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1808                                        SDRAM_CFG_REG,
1809                                        refresh_interval_cnt << REFRESH_OFFS,
1810                                        REFRESH_MASK << REFRESH_OFFS));
1811         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1812                                        SDRAM_ADDR_CTRL_REG, (t_faw - 1) << T_FAW_OFFS,
1813                                        T_FAW_MASK << T_FAW_OFFS));
1814
1815         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG,
1816                                        (t_pd - 1) << DDR_TIMING_TPD_OFFS |
1817                                        (t_xpdll - 1) << DDR_TIMING_TXPDLL_OFFS,
1818                                        DDR_TIMING_TPD_MASK << DDR_TIMING_TPD_OFFS |
1819                                        DDR_TIMING_TXPDLL_MASK << DDR_TIMING_TXPDLL_OFFS));
1820
1821 #if defined(CONFIG_DDR4)
1822         ddr4_tip_set_timing(dev_num, access_type, if_id, frequency);
1823 #endif /* CONFIG_DDR4 */
1824
1825         return MV_OK;
1826 }
1827
1828 #if defined(CONFIG_DDR4)
1829 static int ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
1830                                u32 if_id, enum mv_ddr_freq frequency)
1831 {
1832         u32 t_rrd_l = 0, t_wtr_l = 0, t_ckclk = 0, t_mod = 0, t_ccd = 0;
1833         u32 page_size = 0, val = 0, mask = 0;
1834         enum mv_ddr_speed_bin speed_bin_index;
1835         enum mv_ddr_die_capacity memory_size;
1836         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1837         u32 freq = mv_ddr_freq_get(frequency);
1838
1839         speed_bin_index = tm->interface_params[if_id].speed_bin_index;
1840         memory_size = tm->interface_params[if_id].memory_size;
1841         page_size = mv_ddr_page_size_get(tm->interface_params[if_id].bus_width, memory_size);
1842
1843         t_ckclk = (MEGA / freq);
1844
1845         t_rrd_l = (page_size == 1) ? mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRDL1K) :
1846                         mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TRRDL2K);
1847         t_rrd_l = GET_MAX_VALUE(t_ckclk * 4, t_rrd_l);
1848
1849         t_wtr_l = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TWTRL);
1850         t_wtr_l = GET_MAX_VALUE(t_ckclk * 4, t_wtr_l);
1851
1852         t_rrd_l = time_to_nclk(t_rrd_l, t_ckclk);
1853         t_wtr_l = time_to_nclk(t_wtr_l, t_ckclk);
1854
1855         val = (((t_rrd_l - 1) & DDR4_TRRD_L_MASK) << DDR4_TRRD_L_OFFS) |
1856               (((t_wtr_l - 1) & DDR4_TWTR_L_MASK) << DDR4_TWTR_L_OFFS);
1857         mask = (DDR4_TRRD_L_MASK << DDR4_TRRD_L_OFFS) |
1858                (DDR4_TWTR_L_MASK << DDR4_TWTR_L_OFFS);
1859         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1860                                        DRAM_LONG_TIMING_REG, val, mask));
1861
1862         val = 0;
1863         mask = 0;
1864         t_mod = mv_ddr_speed_bin_timing_get(speed_bin_index, SPEED_BIN_TMOD);
1865         t_mod = GET_MAX_VALUE(t_ckclk * 24, t_mod);
1866         t_mod = time_to_nclk(t_mod, t_ckclk);
1867
1868         val = (((t_mod - 1) & SDRAM_TIMING_HIGH_TMOD_MASK) << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1869               ((((t_mod - 1) >> 4) & SDRAM_TIMING_HIGH_TMOD_HIGH_MASK) << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1870         mask = (SDRAM_TIMING_HIGH_TMOD_MASK << SDRAM_TIMING_HIGH_TMOD_OFFS) |
1871                (SDRAM_TIMING_HIGH_TMOD_HIGH_MASK << SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS);
1872         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1873                                        SDRAM_TIMING_HIGH_REG, val, mask));
1874
1875         t_ccd = 6;
1876
1877         CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1878                                        DDR_TIMING_REG,
1879                                        ((t_ccd - 1) & DDR_TIMING_TCCD_MASK) << DDR_TIMING_TCCD_OFFS,
1880                                        DDR_TIMING_TCCD_MASK << DDR_TIMING_TCCD_OFFS));
1881
1882         return MV_OK;
1883 }
1884 #endif /* CONFIG_DDR4 */
1885
1886 /*
1887  * Write CS Result
1888  */
1889 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
1890 {
1891         u32 if_id, bus_num, cs_bitmask, data_val, cs_num;
1892         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1893         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1894
1895         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1896                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1897                 for (bus_num = 0; bus_num < octets_per_if_num;
1898                      bus_num++) {
1899                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_num);
1900                         cs_bitmask =
1901                                 tm->interface_params[if_id].
1902                                 as_bus_params[bus_num].cs_bitmask;
1903                         if (cs_bitmask != effective_cs) {
1904                                 cs_num = GET_CS_FROM_MASK(cs_bitmask);
1905                                 ddr3_tip_bus_read(dev_num, if_id,
1906                                                   ACCESS_TYPE_UNICAST, bus_num,
1907                                                   DDR_PHY_DATA,
1908                                                   offset +
1909                                                   (effective_cs * 0x4),
1910                                                   &data_val);
1911                                 ddr3_tip_bus_write(dev_num,
1912                                                    ACCESS_TYPE_UNICAST,
1913                                                    if_id,
1914                                                    ACCESS_TYPE_UNICAST,
1915                                                    bus_num, DDR_PHY_DATA,
1916                                                    offset +
1917                                                    (cs_num * 0x4),
1918                                                    data_val);
1919                         }
1920                 }
1921         }
1922
1923         return MV_OK;
1924 }
1925
1926 /*
1927  * Write MRS
1928  */
1929 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask)
1930 {
1931         u32 if_id;
1932         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1933
1934         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1935                                        PARAM_NOT_CARE, mr_data[mr_num].reg_addr, data, mask));
1936         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1937                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1938                 CHECK_STATUS(ddr3_tip_if_write
1939                              (dev_num, ACCESS_TYPE_UNICAST, if_id,
1940                               SDRAM_OP_REG,
1941                               (cs_mask_arr[if_id] << 8) | mr_data[mr_num].cmd, 0xf1f));
1942         }
1943
1944         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1945                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1946                 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
1947                                         0x1f, SDRAM_OP_REG,
1948                                         MAX_POLLING_ITERATIONS) != MV_OK) {
1949                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1950                                           ("write_mrs_cmd: Poll cmd fail"));
1951                 }
1952         }
1953
1954         return MV_OK;
1955 }
1956
1957 /*
1958  * Reset XSB Read FIFO
1959  */
1960 int ddr3_tip_reset_fifo_ptr(u32 dev_num)
1961 {
1962         u32 if_id = 0;
1963
1964         /* Configure PHY reset value to 0 in order to "clean" the FIFO */
1965         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1966                                        if_id, 0x15c8, 0, 0xff000000));
1967         /*
1968          * Move PHY to RL mode (only in RL mode the PHY overrides FIFO values
1969          * during FIFO reset)
1970          */
1971         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1972                                        if_id, TRAINING_SW_2_REG,
1973                                        0x1, 0x9));
1974         /* In order that above configuration will influence the PHY */
1975         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1976                                        if_id, 0x15b0,
1977                                        0x80000000, 0x80000000));
1978         /* Reset read fifo assertion */
1979         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1980                                        if_id, 0x1400, 0, 0x40000000));
1981         /* Reset read fifo deassertion */
1982         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1983                                        if_id, 0x1400,
1984                                        0x40000000, 0x40000000));
1985         /* Move PHY back to functional mode */
1986         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1987                                        if_id, TRAINING_SW_2_REG,
1988                                        0x8, 0x9));
1989         /* Stop training machine */
1990         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1991                                        if_id, 0x15b4, 0x10000, 0x10000));
1992
1993         return MV_OK;
1994 }
1995
1996 /*
1997  * Reset Phy registers
1998  */
1999 int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)
2000 {
2001         u32 if_id, phy_id, cs;
2002         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2003         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2004
2005         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2006                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2007                 for (phy_id = 0; phy_id < octets_per_if_num;
2008                      phy_id++) {
2009                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id);
2010                         CHECK_STATUS(ddr3_tip_bus_write
2011                                      (dev_num, ACCESS_TYPE_UNICAST,
2012                                       if_id, ACCESS_TYPE_UNICAST,
2013                                       phy_id, DDR_PHY_DATA,
2014                                       WL_PHY_REG(effective_cs),
2015                                       phy_reg0_val));
2016                         CHECK_STATUS(ddr3_tip_bus_write
2017                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2018                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2019                                       RL_PHY_REG(effective_cs),
2020                                       phy_reg2_val));
2021                         CHECK_STATUS(ddr3_tip_bus_write
2022                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2023                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2024                                       CRX_PHY_REG(effective_cs), phy_reg3_val));
2025                         CHECK_STATUS(ddr3_tip_bus_write
2026                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2027                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2028                                       CTX_PHY_REG(effective_cs), phy_reg1_val));
2029                         CHECK_STATUS(ddr3_tip_bus_write
2030                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2031                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2032                                       PBS_TX_BCAST_PHY_REG(effective_cs), 0x0));
2033                         CHECK_STATUS(ddr3_tip_bus_write
2034                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2035                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2036                                       PBS_RX_BCAST_PHY_REG(effective_cs), 0));
2037                         CHECK_STATUS(ddr3_tip_bus_write
2038                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2039                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2040                                       PBS_TX_PHY_REG(effective_cs, DQSP_PAD), 0));
2041                         CHECK_STATUS(ddr3_tip_bus_write
2042                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2043                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2044                                       PBS_RX_PHY_REG(effective_cs, DQSP_PAD), 0));
2045                         CHECK_STATUS(ddr3_tip_bus_write
2046                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2047                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2048                                       PBS_TX_PHY_REG(effective_cs, DQSN_PAD), 0));
2049                         CHECK_STATUS(ddr3_tip_bus_write
2050                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2051                                       ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2052                                       PBS_RX_PHY_REG(effective_cs, DQSN_PAD), 0));
2053                 }
2054         }
2055
2056         /* Set Receiver Calibration value */
2057         for (cs = 0; cs < MAX_CS_NUM; cs++) {
2058                 /* PHY register 0xdb bits[5:0] - configure to 63 */
2059                 CHECK_STATUS(ddr3_tip_bus_write
2060                              (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
2061                               ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
2062                               DDR_PHY_DATA, VREF_BCAST_PHY_REG(cs), 63));
2063         }
2064
2065         return MV_OK;
2066 }
2067
2068 /*
2069  * Restore Dunit registers
2070  */
2071 int ddr3_tip_restore_dunit_regs(u32 dev_num)
2072 {
2073         u32 index_cnt;
2074
2075         mv_ddr_set_calib_controller();
2076
2077         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2078                                        PARAM_NOT_CARE, MAIN_PADS_CAL_MACH_CTRL_REG,
2079                                        0x1, 0x1));
2080         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2081                                        PARAM_NOT_CARE, MAIN_PADS_CAL_MACH_CTRL_REG,
2082                                        calibration_update_control << 3,
2083                                        0x3 << 3));
2084         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2085                                        PARAM_NOT_CARE,
2086                                        ODPG_WR_RD_MODE_ENA_REG,
2087                                        0xffff, MASK_ALL_BITS));
2088
2089         for (index_cnt = 0; index_cnt < ARRAY_SIZE(odpg_default_value);
2090              index_cnt++) {
2091                 CHECK_STATUS(ddr3_tip_if_write
2092                              (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
2093                               odpg_default_value[index_cnt].reg_addr,
2094                               odpg_default_value[index_cnt].reg_data,
2095                               odpg_default_value[index_cnt].reg_mask));
2096         }
2097
2098         return MV_OK;
2099 }
2100
2101 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)
2102 {
2103         u32 if_id, phy_id;
2104         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2105         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2106
2107         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2108                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2109                 for (phy_id = 0; phy_id < octets_per_if_num; phy_id++) {
2110                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, phy_id);
2111                         CHECK_STATUS(ddr3_tip_bus_write
2112                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2113                                      ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2114                                      CTX_PHY_REG(effective_cs), reg_val1));
2115                         CHECK_STATUS(ddr3_tip_bus_write
2116                                      (dev_num, ACCESS_TYPE_UNICAST, if_id,
2117                                      ACCESS_TYPE_UNICAST, phy_id, DDR_PHY_DATA,
2118                                      PBS_TX_BCAST_PHY_REG(effective_cs), reg_val2));
2119                 }
2120         }
2121
2122         return MV_OK;
2123 }
2124
2125 /*
2126  * Auto tune main flow
2127  */
2128 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
2129 {
2130 /* TODO: enable this functionality for other platforms */
2131         struct init_cntr_param init_cntr_prm;
2132         int ret = MV_OK;
2133         int adll_bypass_flag = 0;
2134         u32 if_id;
2135         unsigned int max_cs = mv_ddr_cs_num_get();
2136         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2137         enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
2138         unsigned int *freq_tbl = mv_ddr_freq_tbl_get();
2139
2140 #ifdef DDR_VIEWER_TOOL
2141         if (debug_training == DEBUG_LEVEL_TRACE) {
2142                 CHECK_STATUS(print_device_info((u8)dev_num));
2143         }
2144 #endif
2145
2146         ddr3_tip_validate_algo_components(dev_num);
2147
2148         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2149                 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
2150         }
2151         /* Set to 0 after each loop to avoid illegal value may be used */
2152         effective_cs = 0;
2153
2154         freq_tbl[MV_DDR_FREQ_LOW_FREQ] = dfs_low_freq;
2155
2156         if (is_pll_before_init != 0) {
2157                 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
2158                         VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2159                         config_func_info[dev_num].tip_set_freq_divider_func(
2160                                 (u8)dev_num, if_id, freq);
2161                 }
2162         }
2163
2164 /* TODO: enable this functionality for other platforms */
2165         if (is_adll_calib_before_init != 0) {
2166                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2167                                   ("with adll calib before init\n"));
2168                 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2169         }
2170
2171         if (is_reg_dump != 0) {
2172                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2173                                   ("Dump before init controller\n"));
2174                 ddr3_tip_reg_dump(dev_num);
2175         }
2176
2177         if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
2178                 training_stage = INIT_CONTROLLER;
2179                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2180                                   ("INIT_CONTROLLER_MASK_BIT\n"));
2181                 init_cntr_prm.do_mrs_phy = 1;
2182                 init_cntr_prm.is_ctrl64_bit = 0;
2183                 init_cntr_prm.init_phy = 1;
2184                 init_cntr_prm.msys_init = 0;
2185                 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
2186                 if (is_reg_dump != 0)
2187                         ddr3_tip_reg_dump(dev_num);
2188                 if (ret != MV_OK) {
2189                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2190                                           ("hws_ddr3_tip_init_controller failure\n"));
2191                         if (debug_mode == 0)
2192                                 return MV_FAIL;
2193                 }
2194         }
2195
2196         ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2197         if (ret != MV_OK) {
2198                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2199                         ("adll_calibration failure\n"));
2200                 if (debug_mode == 0)
2201                         return MV_FAIL;
2202         }
2203
2204         if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
2205                 training_stage = SET_LOW_FREQ;
2206
2207                 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2208                         ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f);
2209                         adll_bypass_flag = 1;
2210                 }
2211                 effective_cs = 0;
2212
2213                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2214                                   ("SET_LOW_FREQ_MASK_BIT %d\n",
2215                                    freq_tbl[low_freq]));
2216                 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2217                                         PARAM_NOT_CARE, low_freq);
2218                 if (is_reg_dump != 0)
2219                         ddr3_tip_reg_dump(dev_num);
2220                 if (ret != MV_OK) {
2221                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2222                                           ("ddr3_tip_freq_set failure\n"));
2223                         if (debug_mode == 0)
2224                                 return MV_FAIL;
2225                 }
2226         }
2227
2228         if (mask_tune_func & WRITE_LEVELING_LF_MASK_BIT) {
2229                 training_stage = WRITE_LEVELING_LF;
2230                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2231                         ("WRITE_LEVELING_LF_MASK_BIT\n"));
2232                 ret = ddr3_tip_dynamic_write_leveling(dev_num, 1);
2233                 if (is_reg_dump != 0)
2234                         ddr3_tip_reg_dump(dev_num);
2235                 if (ret != MV_OK) {
2236                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2237                                 ("ddr3_tip_dynamic_write_leveling LF failure\n"));
2238                         if (debug_mode == 0)
2239                                 return MV_FAIL;
2240                 }
2241         }
2242
2243         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2244                 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
2245                         training_stage = LOAD_PATTERN;
2246                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2247                                           ("LOAD_PATTERN_MASK_BIT #%d\n",
2248                                            effective_cs));
2249                         ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2250                         if (is_reg_dump != 0)
2251                                 ddr3_tip_reg_dump(dev_num);
2252                         if (ret != MV_OK) {
2253                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2254                                                   ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2255                                                    effective_cs));
2256                                 if (debug_mode == 0)
2257                                         return MV_FAIL;
2258                         }
2259                 }
2260         }
2261
2262         if (adll_bypass_flag == 1) {
2263                 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2264                         ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0);
2265                         adll_bypass_flag = 0;
2266                 }
2267         }
2268
2269         /* Set to 0 after each loop to avoid illegal value may be used */
2270         effective_cs = 0;
2271
2272         if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
2273                 training_stage = SET_MEDIUM_FREQ;
2274                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2275                                   ("SET_MEDIUM_FREQ_MASK_BIT %d\n",
2276                                    freq_tbl[medium_freq]));
2277                 ret =
2278                         ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2279                                           PARAM_NOT_CARE, medium_freq);
2280                 if (is_reg_dump != 0)
2281                         ddr3_tip_reg_dump(dev_num);
2282                 if (ret != MV_OK) {
2283                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2284                                           ("ddr3_tip_freq_set failure\n"));
2285                         if (debug_mode == 0)
2286                                 return MV_FAIL;
2287                 }
2288         }
2289
2290         if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
2291                 training_stage = WRITE_LEVELING;
2292                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2293                                   ("WRITE_LEVELING_MASK_BIT\n"));
2294                 if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
2295                         ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2296                 } else {
2297                         /* Use old WL */
2298                         ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
2299                 }
2300
2301                 if (is_reg_dump != 0)
2302                         ddr3_tip_reg_dump(dev_num);
2303                 if (ret != MV_OK) {
2304                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2305                                           ("ddr3_tip_dynamic_write_leveling failure\n"));
2306                         if (debug_mode == 0)
2307                                 return MV_FAIL;
2308                 }
2309         }
2310
2311         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2312                 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
2313                         training_stage = LOAD_PATTERN_2;
2314                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2315                                           ("LOAD_PATTERN_2_MASK_BIT CS #%d\n",
2316                                            effective_cs));
2317                         ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2318                         if (is_reg_dump != 0)
2319                                 ddr3_tip_reg_dump(dev_num);
2320                         if (ret != MV_OK) {
2321                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2322                                                   ("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
2323                                                    effective_cs));
2324                                 if (debug_mode == 0)
2325                                         return MV_FAIL;
2326                         }
2327                 }
2328         }
2329         /* Set to 0 after each loop to avoid illegal value may be used */
2330         effective_cs = 0;
2331
2332         if (mask_tune_func & READ_LEVELING_MASK_BIT) {
2333                 training_stage = READ_LEVELING;
2334                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2335                                   ("READ_LEVELING_MASK_BIT\n"));
2336                 if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
2337                         ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
2338                 } else {
2339                         /* Use old RL */
2340                         ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
2341                 }
2342
2343                 if (is_reg_dump != 0)
2344                         ddr3_tip_reg_dump(dev_num);
2345                 if (ret != MV_OK) {
2346                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2347                                           ("ddr3_tip_dynamic_read_leveling failure\n"));
2348                         if (debug_mode == 0)
2349                                 return MV_FAIL;
2350                 }
2351         }
2352
2353         if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
2354                 training_stage = WRITE_LEVELING_SUPP;
2355                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2356                                   ("WRITE_LEVELING_SUPP_MASK_BIT\n"));
2357                 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2358                 if (is_reg_dump != 0)
2359                         ddr3_tip_reg_dump(dev_num);
2360                 if (ret != MV_OK) {
2361                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2362                                           ("ddr3_tip_dynamic_write_leveling_supp failure\n"));
2363                         if (debug_mode == 0)
2364                                 return MV_FAIL;
2365                 }
2366         }
2367
2368 #if !defined(CONFIG_DDR4)
2369         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2370                 if (mask_tune_func & PBS_RX_MASK_BIT) {
2371                         training_stage = PBS_RX;
2372                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2373                                           ("PBS_RX_MASK_BIT CS #%d\n",
2374                                            effective_cs));
2375                         ret = ddr3_tip_pbs_rx(dev_num);
2376                         if (is_reg_dump != 0)
2377                                 ddr3_tip_reg_dump(dev_num);
2378                         if (ret != MV_OK) {
2379                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2380                                                   ("ddr3_tip_pbs_rx failure CS #%d\n",
2381                                                    effective_cs));
2382                                 if (debug_mode == 0)
2383                                         return MV_FAIL;
2384                         }
2385                 }
2386         }
2387
2388         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2389                 if (mask_tune_func & PBS_TX_MASK_BIT) {
2390                         training_stage = PBS_TX;
2391                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2392                                           ("PBS_TX_MASK_BIT CS #%d\n",
2393                                            effective_cs));
2394                         ret = ddr3_tip_pbs_tx(dev_num);
2395                         if (is_reg_dump != 0)
2396                                 ddr3_tip_reg_dump(dev_num);
2397                         if (ret != MV_OK) {
2398                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2399                                                   ("ddr3_tip_pbs_tx failure CS #%d\n",
2400                                                    effective_cs));
2401                                 if (debug_mode == 0)
2402                                         return MV_FAIL;
2403                         }
2404                 }
2405         }
2406         /* Set to 0 after each loop to avoid illegal value may be used */
2407         effective_cs = 0;
2408 #endif /* CONFIG_DDR4 */
2409
2410         if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
2411                 training_stage = SET_TARGET_FREQ;
2412                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2413                                   ("SET_TARGET_FREQ_MASK_BIT %d\n",
2414                                    freq_tbl[tm->
2415                                             interface_params[first_active_if].
2416                                             memory_freq]));
2417                 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2418                                         PARAM_NOT_CARE,
2419                                         tm->interface_params[first_active_if].
2420                                         memory_freq);
2421                 if (is_reg_dump != 0)
2422                         ddr3_tip_reg_dump(dev_num);
2423                 if (ret != MV_OK) {
2424                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2425                                           ("ddr3_tip_freq_set failure\n"));
2426                         if (debug_mode == 0)
2427                                 return MV_FAIL;
2428                 }
2429         }
2430
2431         if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
2432                 training_stage = WRITE_LEVELING_TF;
2433                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2434                                   ("WRITE_LEVELING_TF_MASK_BIT\n"));
2435                 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2436                 if (is_reg_dump != 0)
2437                         ddr3_tip_reg_dump(dev_num);
2438                 if (ret != MV_OK) {
2439                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2440                                           ("ddr3_tip_dynamic_write_leveling TF failure\n"));
2441                         if (debug_mode == 0)
2442                                 return MV_FAIL;
2443                 }
2444         }
2445
2446         if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {
2447                 training_stage = LOAD_PATTERN_HIGH;
2448                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("LOAD_PATTERN_HIGH\n"));
2449                 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2450                 if (is_reg_dump != 0)
2451                         ddr3_tip_reg_dump(dev_num);
2452                 if (ret != MV_OK) {
2453                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2454                                           ("ddr3_tip_load_all_pattern_to_mem failure\n"));
2455                         if (debug_mode == 0)
2456                                 return MV_FAIL;
2457                 }
2458         }
2459
2460         if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
2461                 training_stage = READ_LEVELING_TF;
2462                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2463                                   ("READ_LEVELING_TF_MASK_BIT\n"));
2464                 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
2465                                                      interface_params[first_active_if].
2466                                                      memory_freq);
2467                 if (is_reg_dump != 0)
2468                         ddr3_tip_reg_dump(dev_num);
2469                 if (ret != MV_OK) {
2470                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2471                                           ("ddr3_tip_dynamic_read_leveling TF failure\n"));
2472                         if (debug_mode == 0)
2473                                 return MV_FAIL;
2474                 }
2475         }
2476
2477         if (mask_tune_func & RL_DQS_BURST_MASK_BIT) {
2478                 training_stage = READ_LEVELING_TF;
2479                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2480                                   ("RL_DQS_BURST_MASK_BIT\n"));
2481                 ret = mv_ddr_rl_dqs_burst(0, 0, tm->interface_params[0].memory_freq);
2482                 if (is_reg_dump != 0)
2483                         ddr3_tip_reg_dump(dev_num);
2484                 if (ret != MV_OK) {
2485                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2486                                           ("mv_ddr_rl_dqs_burst TF failure\n"));
2487                         if (debug_mode == 0)
2488                                 return MV_FAIL;
2489                 }
2490         }
2491
2492 #if !defined(CONFIG_DDR4)
2493         if (mask_tune_func & DM_PBS_TX_MASK_BIT) {
2494                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_PBS_TX_MASK_BIT\n"));
2495         }
2496
2497         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2498                 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
2499                         training_stage = VREF_CALIBRATION;
2500                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("VREF\n"));
2501                         ret = ddr3_tip_vref(dev_num);
2502                         if (is_reg_dump != 0) {
2503                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2504                                                   ("VREF Dump\n"));
2505                                 ddr3_tip_reg_dump(dev_num);
2506                         }
2507                         if (ret != MV_OK) {
2508                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2509                                                   ("ddr3_tip_vref failure\n"));
2510                                 if (debug_mode == 0)
2511                                         return MV_FAIL;
2512                         }
2513                 }
2514         }
2515         /* Set to 0 after each loop to avoid illegal value may be used */
2516         effective_cs = 0;
2517
2518         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2519                 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
2520                         training_stage = CENTRALIZATION_RX;
2521                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2522                                           ("CENTRALIZATION_RX_MASK_BIT CS #%d\n",
2523                                            effective_cs));
2524                         ret = ddr3_tip_centralization_rx(dev_num);
2525                         if (is_reg_dump != 0)
2526                                 ddr3_tip_reg_dump(dev_num);
2527                         if (ret != MV_OK) {
2528                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2529                                                   ("ddr3_tip_centralization_rx failure CS #%d\n",
2530                                                    effective_cs));
2531                                 if (debug_mode == 0)
2532                                         return MV_FAIL;
2533                         }
2534                 }
2535         }
2536         /* Set to 0 after each loop to avoid illegal value may be used */
2537         effective_cs = 0;
2538 #endif /* CONFIG_DDR4 */
2539
2540         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2541                 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
2542                         training_stage = WRITE_LEVELING_SUPP_TF;
2543                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2544                                           ("WRITE_LEVELING_SUPP_TF_MASK_BIT CS #%d\n",
2545                                            effective_cs));
2546                         ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2547                         if (is_reg_dump != 0)
2548                                 ddr3_tip_reg_dump(dev_num);
2549                         if (ret != MV_OK) {
2550                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2551                                                   ("ddr3_tip_dynamic_write_leveling_supp TF failure CS #%d\n",
2552                                                    effective_cs));
2553                                 if (debug_mode == 0)
2554                                         return MV_FAIL;
2555                         }
2556                 }
2557         }
2558         /* Set to 0 after each loop to avoid illegal value may be used */
2559         effective_cs = 0;
2560
2561 #if defined(CONFIG_DDR4)
2562         for (effective_cs = 0; effective_cs < max_cs; effective_cs++)
2563                 CHECK_STATUS(mv_ddr4_training_main_flow(dev_num));
2564 #endif /* CONFIG_DDR4 */
2565
2566 #if !defined(CONFIG_DDR4)
2567         for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
2568                 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
2569                         training_stage = CENTRALIZATION_TX;
2570                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2571                                           ("CENTRALIZATION_TX_MASK_BIT CS #%d\n",
2572                                            effective_cs));
2573                         ret = ddr3_tip_centralization_tx(dev_num);
2574                         if (is_reg_dump != 0)
2575                                 ddr3_tip_reg_dump(dev_num);
2576                         if (ret != MV_OK) {
2577                                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2578                                                   ("ddr3_tip_centralization_tx failure CS #%d\n",
2579                                                    effective_cs));
2580                                 if (debug_mode == 0)
2581                                         return MV_FAIL;
2582                         }
2583                 }
2584         }
2585         /* Set to 0 after each loop to avoid illegal value may be used */
2586         effective_cs = 0;
2587 #endif /* CONFIG_DDR4 */
2588
2589         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("restore registers to default\n"));
2590         /* restore register values */
2591         CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
2592
2593         if (is_reg_dump != 0)
2594                 ddr3_tip_reg_dump(dev_num);
2595
2596         return MV_OK;
2597 }
2598
2599 /*
2600  * DDR3 Dynamic training flow
2601  */
2602 static int ddr3_tip_ddr3_auto_tune(u32 dev_num)
2603 {
2604         int status;
2605         u32 if_id, stage;
2606         int is_if_fail = 0, is_auto_tune_fail = 0;
2607
2608         training_stage = INIT_CONTROLLER;
2609
2610         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2611                 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++)
2612                         training_result[stage][if_id] = NO_TEST_DONE;
2613         }
2614
2615         status = ddr3_tip_ddr3_training_main_flow(dev_num);
2616
2617         /* activate XSB test */
2618         if (xsb_validate_type != 0) {
2619                 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1,
2620                              0x1024);
2621         }
2622
2623         if (is_reg_dump != 0)
2624                 ddr3_tip_reg_dump(dev_num);
2625
2626         /* print log */
2627         CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr));
2628
2629 #ifndef EXCLUDE_DEBUG_PRINTS
2630         if (status != MV_OK) {
2631                 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num));
2632         }
2633 #endif /* EXCLUDE_DEBUG_PRINTS */
2634
2635         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2636                 is_if_fail = 0;
2637                 for (stage = 0; stage < MAX_STAGE_LIMIT; stage++) {
2638                         if (training_result[stage][if_id] == TEST_FAILED)
2639                                 is_if_fail = 1;
2640                 }
2641                 if (is_if_fail == 1) {
2642                         is_auto_tune_fail = 1;
2643                         DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2644                                           ("Auto Tune failed for IF %d\n",
2645                                            if_id));
2646                 }
2647         }
2648
2649         if (((status == MV_FAIL) && (is_auto_tune_fail == 0)) ||
2650             ((status == MV_OK) && (is_auto_tune_fail == 1))) {
2651                 /*
2652                  * If MainFlow result and trainingResult DB not in sync,
2653                  * issue warning (caused by no update of trainingResult DB
2654                  * when failed)
2655                  */
2656                 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
2657                                   ("Warning: Algorithm return value and Result DB"
2658                                    "are not synced (status 0x%x  result DB %d)\n",
2659                                    status, is_auto_tune_fail));
2660         }
2661
2662         if ((status != MV_OK) || (is_auto_tune_fail == 1))
2663                 return MV_FAIL;
2664         else
2665                 return MV_OK;
2666 }
2667
2668 /*
2669  * Enable init sequence
2670  */
2671 int ddr3_tip_enable_init_sequence(u32 dev_num)
2672 {
2673         int is_fail = 0;
2674         u32 if_id = 0, mem_mask = 0, bus_index = 0;
2675         u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2676         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2677
2678         /* Enable init sequence */
2679         CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0,
2680                                        SDRAM_INIT_CTRL_REG, 0x1, 0x1));
2681
2682         for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
2683                 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
2684
2685                 if (ddr3_tip_if_polling
2686                     (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1,
2687                      SDRAM_INIT_CTRL_REG,
2688                      MAX_POLLING_ITERATIONS) != MV_OK) {
2689                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2690                                           ("polling failed IF %d\n",
2691                                            if_id));
2692                         is_fail = 1;
2693                         continue;
2694                 }
2695
2696                 mem_mask = 0;
2697                 for (bus_index = 0; bus_index < octets_per_if_num;
2698                      bus_index++) {
2699                         VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
2700                         mem_mask |=
2701                                 tm->interface_params[if_id].
2702                                 as_bus_params[bus_index].mirror_enable_bitmask;
2703                 }
2704
2705                 if (mem_mask != 0) {
2706                         /* Disable Multi CS */
2707                         CHECK_STATUS(ddr3_tip_if_write
2708                                      (dev_num, ACCESS_TYPE_MULTICAST,
2709                                       if_id, DUAL_DUNIT_CFG_REG, 1 << 3,
2710                                       1 << 3));
2711                 }
2712         }
2713
2714         return (is_fail == 0) ? MV_OK : MV_FAIL;
2715 }
2716
2717 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)
2718 {
2719         dq_map_table = table;
2720
2721         return MV_OK;
2722 }
2723
2724 /*
2725  * Check if pup search is locked
2726  */
2727 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode)
2728 {
2729         u32 bit_start = 0, bit_end = 0, bit_id;
2730
2731         if (read_mode == RESULT_PER_BIT) {
2732                 bit_start = 0;
2733                 bit_end = BUS_WIDTH_IN_BITS - 1;
2734         } else {
2735                 bit_start = 0;
2736                 bit_end = 0;
2737         }
2738
2739         for (bit_id = bit_start; bit_id <= bit_end; bit_id++) {
2740                 if (GET_LOCK_RESULT(pup_buf[bit_id]) == 0)
2741                         return 0;
2742         }
2743
2744         return 1;
2745 }
2746
2747 /*
2748  * Get minimum buffer value
2749  */
2750 u8 ddr3_tip_get_buf_min(u8 *buf_ptr)
2751 {
2752         u8 min_val = 0xff;
2753         u8 cnt = 0;
2754
2755         for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2756                 if (buf_ptr[cnt] < min_val)
2757                         min_val = buf_ptr[cnt];
2758         }
2759
2760         return min_val;
2761 }
2762
2763 /*
2764  * Get maximum buffer value
2765  */
2766 u8 ddr3_tip_get_buf_max(u8 *buf_ptr)
2767 {
2768         u8 max_val = 0;
2769         u8 cnt = 0;
2770
2771         for (cnt = 0; cnt < BUS_WIDTH_IN_BITS; cnt++) {
2772                 if (buf_ptr[cnt] > max_val)
2773                         max_val = buf_ptr[cnt];
2774         }
2775
2776         return max_val;
2777 }
2778
2779 /*
2780  * The following functions return memory parameters:
2781  * bus and device width, device size
2782  */
2783
2784 u32 hws_ddr3_get_bus_width(void)
2785 {
2786         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2787
2788         return (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask) ==
2789                 1) ? 16 : 32;
2790 }
2791
2792 u32 hws_ddr3_get_device_width(u32 if_id)
2793 {
2794         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2795
2796         return (tm->interface_params[if_id].bus_width ==
2797                 MV_DDR_DEV_WIDTH_8BIT) ? 8 : 16;
2798 }
2799
2800 u32 hws_ddr3_get_device_size(u32 if_id)
2801 {
2802         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2803
2804         if (tm->interface_params[if_id].memory_size >=
2805             MV_DDR_DIE_CAP_LAST) {
2806                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2807                                   ("Error: Wrong device size of Cs: %d",
2808                                    tm->interface_params[if_id].memory_size));
2809                 return 0;
2810         } else {
2811                 return 1 << tm->interface_params[if_id].memory_size;
2812         }
2813 }
2814
2815 int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size)
2816 {
2817         u32 cs_mem_size, dev_size;
2818
2819         dev_size = hws_ddr3_get_device_size(if_id);
2820         if (dev_size != 0) {
2821                 cs_mem_size = ((hws_ddr3_get_bus_width() /
2822                                 hws_ddr3_get_device_width(if_id)) * dev_size);
2823
2824                 /* the calculated result in Gbytex16 to avoid float using */
2825
2826                 if (cs_mem_size == 2) {
2827                         *cs_size = _128M;
2828                 } else if (cs_mem_size == 4) {
2829                         *cs_size = _256M;
2830                 } else if (cs_mem_size == 8) {
2831                         *cs_size = _512M;
2832                 } else if (cs_mem_size == 16) {
2833                         *cs_size = _1G;
2834                 } else if (cs_mem_size == 32) {
2835                         *cs_size = _2G;
2836                 } else {
2837                         DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2838                                           ("Error: Wrong Memory size of Cs: %d", cs));
2839                         return MV_FAIL;
2840                 }
2841                 return MV_OK;
2842         } else {
2843                 return MV_FAIL;
2844         }
2845 }
2846
2847 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr)
2848 {
2849         u32 cs_mem_size = 0;
2850 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2851         u32 physical_mem_size;
2852         u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
2853 #endif
2854
2855         if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK)
2856                 return MV_FAIL;
2857
2858 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
2859         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2860         /*
2861          * if number of address pins doesn't allow to use max mem size that
2862          * is defined in topology mem size is defined by
2863          * DEVICE_MAX_DRAM_ADDRESS_SIZE
2864          */
2865         physical_mem_size = mem_size[tm->interface_params[0].memory_size];
2866
2867         if (hws_ddr3_get_device_width(cs) == 16) {
2868                 /*
2869                  * 16bit mem device can be twice more - no need in less
2870                  * significant pin
2871                  */
2872                 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
2873         }
2874
2875         if (physical_mem_size > max_mem_size) {
2876                 cs_mem_size = max_mem_size *
2877                         (hws_ddr3_get_bus_width() /
2878                          hws_ddr3_get_device_width(if_id));
2879                 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
2880                                   ("Updated Physical Mem size is from 0x%x to %x\n",
2881                                    physical_mem_size,
2882                                    DEVICE_MAX_DRAM_ADDRESS_SIZE));
2883         }
2884 #endif
2885
2886         /* calculate CS base addr */
2887         *cs_base_addr = ((cs_mem_size) * cs) & 0xffff0000;
2888
2889         return MV_OK;
2890 }
2891
2892 /* TODO: consider to move to misl phy driver */
2893 enum {
2894         MISL_PHY_DRV_OHM_30 = 0xf,
2895         MISL_PHY_DRV_OHM_48 = 0xa,
2896         MISL_PHY_DRV_OHM_80 = 0x6,
2897         MISL_PHY_DRV_OHM_120 = 0x4
2898 };
2899
2900 enum {
2901         MISL_PHY_ODT_OHM_60 = 0x8,
2902         MISL_PHY_ODT_OHM_80 = 0x6,
2903         MISL_PHY_ODT_OHM_120 = 0x4,
2904         MISL_PHY_ODT_OHM_240 = 0x2
2905 };
2906
2907 static unsigned int mv_ddr_misl_phy_drv_calc(unsigned int cfg)
2908 {
2909         unsigned int val;
2910
2911         switch (cfg) {
2912         case MV_DDR_OHM_30:
2913                 val = MISL_PHY_DRV_OHM_30;
2914                 break;
2915         case MV_DDR_OHM_48:
2916                 val = MISL_PHY_DRV_OHM_48;
2917                 break;
2918         case MV_DDR_OHM_80:
2919                 val = MISL_PHY_DRV_OHM_80;
2920                 break;
2921         case MV_DDR_OHM_120:
2922                 val = MISL_PHY_DRV_OHM_120;
2923                 break;
2924         default:
2925                 val = PARAM_UNDEFINED;
2926         }
2927
2928         return val;
2929 }
2930
2931 static unsigned int mv_ddr_misl_phy_odt_calc(unsigned int cfg)
2932 {
2933         unsigned int val;
2934
2935         switch (cfg) {
2936         case MV_DDR_OHM_60:
2937                 val = MISL_PHY_ODT_OHM_60;
2938                 break;
2939         case MV_DDR_OHM_80:
2940                 val = MISL_PHY_ODT_OHM_80;
2941                 break;
2942         case MV_DDR_OHM_120:
2943                 val = MISL_PHY_ODT_OHM_120;
2944                 break;
2945         case MV_DDR_OHM_240:
2946                 val = MISL_PHY_ODT_OHM_240;
2947                 break;
2948         default:
2949                 val = PARAM_UNDEFINED;
2950         }
2951
2952         return val;
2953 }
2954
2955 unsigned int mv_ddr_misl_phy_drv_data_p_get(void)
2956 {
2957         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2958         unsigned int drv_data_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_p);
2959
2960         if (drv_data_p == PARAM_UNDEFINED)
2961                 printf("error: %s: unsupported drv_data_p parameter found\n", __func__);
2962
2963         return drv_data_p;
2964 }
2965
2966 unsigned int mv_ddr_misl_phy_drv_data_n_get(void)
2967 {
2968         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2969         unsigned int drv_data_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_data_n);
2970
2971         if (drv_data_n == PARAM_UNDEFINED)
2972                 printf("error: %s: unsupported drv_data_n parameter found\n", __func__);
2973
2974         return drv_data_n;
2975 }
2976
2977 unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void)
2978 {
2979         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2980         unsigned int drv_ctrl_p = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_p);
2981
2982         if (drv_ctrl_p == PARAM_UNDEFINED)
2983                 printf("error: %s: unsupported drv_ctrl_p parameter found\n", __func__);
2984
2985         return drv_ctrl_p;
2986 }
2987
2988 unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void)
2989 {
2990         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
2991         unsigned int drv_ctrl_n = mv_ddr_misl_phy_drv_calc(tm->edata.phy_edata.drv_ctrl_n);
2992
2993         if (drv_ctrl_n == PARAM_UNDEFINED)
2994                 printf("error: %s: unsupported drv_ctrl_n parameter found\n", __func__);
2995
2996         return drv_ctrl_n;
2997 }
2998
2999 unsigned int mv_ddr_misl_phy_odt_p_get(void)
3000 {
3001         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
3002         unsigned int cs_num = mv_ddr_cs_num_get();
3003         unsigned int odt_p = PARAM_UNDEFINED;
3004
3005         if (cs_num > 0 && cs_num <= MAX_CS_NUM)
3006                 odt_p = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_p[cs_num - 1]);
3007
3008         if (odt_p == PARAM_UNDEFINED)
3009                 printf("error: %s: unsupported odt_p parameter found\n", __func__);
3010
3011         return odt_p;
3012 }
3013
3014 unsigned int mv_ddr_misl_phy_odt_n_get(void)
3015 {
3016         struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
3017         unsigned int cs_num = mv_ddr_cs_num_get();
3018         unsigned int odt_n = PARAM_UNDEFINED;
3019
3020         if (cs_num > 0 && cs_num <= MAX_CS_NUM)
3021                 odt_n = mv_ddr_misl_phy_odt_calc(tm->edata.phy_edata.odt_n[cs_num - 1]);
3022
3023         if (odt_n == PARAM_UNDEFINED)
3024                 printf("error: %s: unsupported odt_n parameter found\n", __func__);
3025
3026         return odt_n;
3027 }
3028