drivers/ddr/imx/imx8m/lpddr4_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3 * Copyright 2018 NXP
   4 *
   5 */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/ddr.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/ddr.h>
  13 #include <asm/arch/lpddr4_define.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
  17 {
  18         int i = 0;
  19
  20         for (i = 0; i < num; i++) {
  21                 reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
  22                 ddrc_cfg++;
  23         }
  24 }
  25
  26 void ddr_init(struct dram_timing_info *dram_timing)
  27 {
  28         unsigned int tmp;
  29
  30         debug("DDRINFO: start lpddr4 ddr init\n");
  31         /* step 1: reset */
  32         if (is_imx8mq()) {
  33                 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
  34                 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  35                 reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
  36         } else {
  37                 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
  38                 reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  39         }
  40
  41         mdelay(100);
  42
  43         debug("DDRINFO: reset done\n");
  44         /*
  45          * change the clock source of dram_apb_clk_root:
  46          * source 4 800MHz /4 = 200MHz
  47          */
  48         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  49                              CLK_ROOT_SOURCE_SEL(4) |
  50                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
  51
  52         /* disable iso */
  53         reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
  54         reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
  55
  56         debug("DDRINFO: cfg clk\n");
  57         if (is_imx8mq())
  58                 dram_pll_init(MHZ(800));
  59         else
  60                 dram_pll_init(MHZ(750));
  61
  62         /*
  63          * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
  64          * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
  65          */
  66         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
  67
  68         /*step2 Configure uMCTL2's registers */
  69         debug("DDRINFO: ddrc config start\n");
  70         lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
  71         debug("DDRINFO: ddrc config done\n");
  72
  73         /*
  74          * step3 de-assert all reset
  75          * RESET: <core_ddrc_rstn> DEASSERTED
  76          * RESET: <aresetn> for Port 0  DEASSERT(0)ED
  77          */
  78         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
  79         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
  80
  81         reg32_write(DDRC_DBG1(0), 0x00000000);
  82         /* step4 */
  83         /* [0]dis_auto_refresh=1 */
  84         reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
  85
  86         /* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
  87         reg32_write(DDRC_PWRCTL(0), 0x000000a8);
  88
  89         do {
  90                 tmp = reg32_read(DDRC_STAT(0));
  91         } while ((tmp & 0x33f) != 0x223);
  92
  93         reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
  94
  95         /* step5 */
  96         reg32_write(DDRC_SWCTL(0), 0x00000000);
  97
  98         /* step6 */
  99         tmp = reg32_read(DDRC_MSTR2(0));
 100         if (tmp == 0x2)
 101                 reg32_write(DDRC_DFIMISC(0), 0x00000210);
 102         else if (tmp == 0x1)
 103                 reg32_write(DDRC_DFIMISC(0), 0x00000110);
 104         else
 105                 reg32_write(DDRC_DFIMISC(0), 0x00000010);
 106
 107         /* step7 [0]--1: disable quasi-dynamic programming */
 108         reg32_write(DDRC_SWCTL(0), 0x00000001);
 109
 110         /* step8 Configure LPDDR4 PHY's registers */
 111         debug("DDRINFO:ddrphy config start\n");
 112         ddr_cfg_phy(dram_timing);
 113         debug("DDRINFO: ddrphy config done\n");
 114
 115         /*
 116          * step14 CalBusy.0 =1, indicates the calibrator is actively
 117          * calibrating. Wait Calibrating done.
 118          */
 119         do {
 120                 tmp = reg32_read(DDRPHY_CalBusy(0));
 121         } while ((tmp & 0x1));
 122
 123         debug("DDRINFO:ddrphy calibration done\n");
 124
 125         /* step15 [0]--0: to enable quasi-dynamic programming */
 126         reg32_write(DDRC_SWCTL(0), 0x00000000);
 127
 128         /* step16 */
 129         tmp = reg32_read(DDRC_MSTR2(0));
 130         if (tmp == 0x2)
 131                 reg32_write(DDRC_DFIMISC(0), 0x00000230);
 132         else if (tmp == 0x1)
 133                 reg32_write(DDRC_DFIMISC(0), 0x00000130);
 134         else
 135                 reg32_write(DDRC_DFIMISC(0), 0x00000030);
 136
 137         /* step17 [0]--1: disable quasi-dynamic programming */
 138         reg32_write(DDRC_SWCTL(0), 0x00000001);
 139         /* step18 wait DFISTAT.dfi_init_complete to 1 */
 140         do {
 141                 tmp = reg32_read(DDRC_DFISTAT(0));
 142         } while ((tmp & 0x1) == 0x0);
 143
 144         /* step19 */
 145         reg32_write(DDRC_SWCTL(0), 0x00000000);
 146
 147         /* step20~22 */
 148         tmp = reg32_read(DDRC_MSTR2(0));
 149         if (tmp == 0x2) {
 150                 reg32_write(DDRC_DFIMISC(0), 0x00000210);
 151                 /* set DFIMISC.dfi_init_complete_en again */
 152                 reg32_write(DDRC_DFIMISC(0), 0x00000211);
 153         } else if (tmp == 0x1) {
 154                 reg32_write(DDRC_DFIMISC(0), 0x00000110);
 155                 /* set DFIMISC.dfi_init_complete_en again */
 156                 reg32_write(DDRC_DFIMISC(0), 0x00000111);
 157         } else {
 158                 /* clear DFIMISC.dfi_init_complete_en */
 159                 reg32_write(DDRC_DFIMISC(0), 0x00000010);
 160                 /* set DFIMISC.dfi_init_complete_en again */
 161                 reg32_write(DDRC_DFIMISC(0), 0x00000011);
 162         }
 163
 164         /* step23 [5]selfref_sw=0; */
 165         reg32_write(DDRC_PWRCTL(0), 0x00000008);
 166         /* step24 sw_done=1 */
 167         reg32_write(DDRC_SWCTL(0), 0x00000001);
 168
 169         /* step25 wait SWSTAT.sw_done_ack to 1 */
 170         do {
 171                 tmp = reg32_read(DDRC_SWSTAT(0));
 172         } while ((tmp & 0x1) == 0x0);
 173
 174 #ifdef DFI_BUG_WR
 175         reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
 176 #endif
 177         /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
 178         do {
 179                 tmp = reg32_read(DDRC_STAT(0));
 180         } while ((tmp & 0x3) != 0x1);
 181
 182         /* step26 */
 183         reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
 184
 185         /* enable port 0 */
 186         reg32_write(DDRC_PCTRL_0(0), 0x00000001);
 187         debug("DDRINFO: ddrmix config done\n");
 188
 189         /* save the dram timing config into memory */
 190         dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
 191 }