drivers/ddr/imx/imx8m/helper.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <log.h>
   8 #include <spl.h>
   9 #include <asm/io.h>
  10 #include <errno.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/ddr.h>
  13 #include <asm/arch/ddr.h>
  14 #include <asm/arch/lpddr4_define.h>
  15 #include <asm/sections.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 #define IMEM_LEN 32768 /* byte */
  20 #define DMEM_LEN 16384 /* byte */
  21 #define IMEM_2D_OFFSET  49152
  22
  23 #define IMEM_OFFSET_ADDR 0x00050000
  24 #define DMEM_OFFSET_ADDR 0x00054000
  25 #define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
  26
  27 /* We need PHY iMEM PHY is 32KB padded */
  28 void ddr_load_train_firmware(enum fw_type type)
  29 {
  30         u32 tmp32, i;
  31         u32 error = 0;
  32         unsigned long pr_to32, pr_from32;
  33         unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
  34         unsigned long imem_start = (unsigned long)&_end + fw_offset;
  35         unsigned long dmem_start;
  36
  37 #ifdef CONFIG_SPL_OF_CONTROL
  38         if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
  39                 imem_start = roundup((unsigned long)&_end +
  40                                      fdt_totalsize(gd->fdt_blob), 4) +
  41                         fw_offset;
  42         }
  43 #endif
  44
  45         dmem_start = imem_start + IMEM_LEN;
  46
  47         pr_from32 = imem_start;
  48         pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  49         for (i = 0x0; i < IMEM_LEN; ) {
  50                 tmp32 = readl(pr_from32);
  51                 writew(tmp32 & 0x0000ffff, pr_to32);
  52                 pr_to32 += 4;
  53                 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  54                 pr_to32 += 4;
  55                 pr_from32 += 4;
  56                 i += 4;
  57         }
  58
  59         pr_from32 = dmem_start;
  60         pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  61         for (i = 0x0; i < DMEM_LEN; ) {
  62                 tmp32 = readl(pr_from32);
  63                 writew(tmp32 & 0x0000ffff, pr_to32);
  64                 pr_to32 += 4;
  65                 writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
  66                 pr_to32 += 4;
  67                 pr_from32 += 4;
  68                 i += 4;
  69         }
  70
  71         debug("check ddr_pmu_train_imem code\n");
  72         pr_from32 = imem_start;
  73         pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
  74         for (i = 0x0; i < IMEM_LEN; ) {
  75                 tmp32 = (readw(pr_to32) & 0x0000ffff);
  76                 pr_to32 += 4;
  77                 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  78
  79                 if (tmp32 != readl(pr_from32)) {
  80                         debug("%lx %lx\n", pr_from32, pr_to32);
  81                         error++;
  82                 }
  83                 pr_from32 += 4;
  84                 pr_to32 += 4;
  85                 i += 4;
  86         }
  87         if (error)
  88                 printf("check ddr_pmu_train_imem code fail=%d\n", error);
  89         else
  90                 debug("check ddr_pmu_train_imem code pass\n");
  91
  92         debug("check ddr4_pmu_train_dmem code\n");
  93         pr_from32 = dmem_start;
  94         pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
  95         for (i = 0x0; i < DMEM_LEN;) {
  96                 tmp32 = (readw(pr_to32) & 0x0000ffff);
  97                 pr_to32 += 4;
  98                 tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
  99                 if (tmp32 != readl(pr_from32)) {
 100                         debug("%lx %lx\n", pr_from32, pr_to32);
 101                         error++;
 102                 }
 103                 pr_from32 += 4;
 104                 pr_to32 += 4;
 105                 i += 4;
 106         }
 107
 108         if (error)
 109                 printf("check ddr_pmu_train_dmem code fail=%d", error);
 110         else
 111                 debug("check ddr_pmu_train_dmem code pass\n");
 112 }
 113
 114 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
 115                              unsigned int num)
 116 {
 117         int i = 0;
 118
 119         /* enable the ddrphy apb */
 120         dwc_ddrphy_apb_wr(0xd0000, 0x0);
 121         dwc_ddrphy_apb_wr(0xc0080, 0x3);
 122         for (i = 0; i < num; i++) {
 123                 ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
 124                 ddrphy_csr++;
 125         }
 126         /* disable the ddrphy apb */
 127         dwc_ddrphy_apb_wr(0xc0080, 0x2);
 128         dwc_ddrphy_apb_wr(0xd0000, 0x1);
 129 }
 130
 131 void dram_config_save(struct dram_timing_info *timing_info,
 132                       unsigned long saved_timing_base)
 133 {
 134         int i = 0;
 135         struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
 136         struct dram_cfg_param *cfg;
 137
 138         saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
 139         saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
 140         saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
 141         saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
 142
 143         /* save the fsp table */
 144         for (i = 0; i < 4; i++)
 145                 saved_timing->fsp_table[i] = timing_info->fsp_table[i];
 146
 147         cfg = (struct dram_cfg_param *)(saved_timing_base +
 148                                         sizeof(*timing_info));
 149
 150         /* save ddrc config */
 151         saved_timing->ddrc_cfg = cfg;
 152         for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
 153                 cfg->reg = timing_info->ddrc_cfg[i].reg;
 154                 cfg->val = timing_info->ddrc_cfg[i].val;
 155                 cfg++;
 156         }
 157
 158         /* save ddrphy config */
 159         saved_timing->ddrphy_cfg = cfg;
 160         for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
 161                 cfg->reg = timing_info->ddrphy_cfg[i].reg;
 162                 cfg->val = timing_info->ddrphy_cfg[i].val;
 163                 cfg++;
 164         }
 165
 166         /* save the ddrphy csr */
 167         saved_timing->ddrphy_trained_csr = cfg;
 168         for (i = 0; i < ddrphy_trained_csr_num; i++) {
 169                 cfg->reg = ddrphy_trained_csr[i].reg;
 170                 cfg->val = ddrphy_trained_csr[i].val;
 171                 cfg++;
 172         }
 173
 174         /* save the ddrphy pie */
 175         saved_timing->ddrphy_pie = cfg;
 176         for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
 177                 cfg->reg = timing_info->ddrphy_pie[i].reg;
 178                 cfg->val = timing_info->ddrphy_pie[i].val;
 179                 cfg++;
 180         }
 181 }