drivers/ddr/imx/imx8m/ddr4_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/ddr.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/sys_proto.h>
  12
  13 void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
  14 {
  15         int i = 0;
  16
  17         for (i = 0; i < num; i++) {
  18                 reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
  19                 ddrc_cfg++;
  20         }
  21 }
  22
  23 void ddr_init(struct dram_timing_info *dram_timing)
  24 {
  25         volatile unsigned int tmp_t;
  26         /*
  27          * assert [0]ddr1_preset_n, [1]ddr1_core_reset_n,
  28          * [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n,
  29          * [4]src_system_rst_b!
  30          */
  31         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00003F);
  32         /* deassert [4]src_system_rst_b! */
  33         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
  34
  35         /*
  36          * change the clock source of dram_apb_clk_root
  37          * to source 4 --800MHz/4
  38          */
  39         clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  40                              CLK_ROOT_SOURCE_SEL(4) |
  41                              CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
  42
  43         dram_pll_init(MHZ(600));
  44
  45         reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
  46         reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
  47
  48         /* release [0]ddr1_preset_n, [3]ddr1_phy_pwrokin_n */
  49         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
  50
  51         reg32_write(DDRC_DBG1(0), 0x00000001);
  52         reg32_write(DDRC_PWRCTL(0), 0x00000001);
  53
  54         while (0 != (0x7 & reg32_read(DDRC_STAT(0))))
  55                 ;
  56
  57         /* config the uMCTL2's registers */
  58         ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
  59
  60         reg32_write(DDRC_RFSHCTL3(0), 0x00000001);
  61         /* RESET: <ctn> DEASSERTED */
  62         /* RESET: <a Port 0  DEASSERTED(0) */
  63         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
  64         reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
  65
  66         reg32_write(DDRC_DBG1(0), 0x00000000);
  67         reg32_write(DDRC_PWRCTL(0), 0x00000aa);
  68         reg32_write(DDRC_SWCTL(0), 0x00000000);
  69
  70         reg32_write(DDRC_DFIMISC(0), 0x00000000);
  71
  72         /* config the DDR PHY's registers */
  73         ddr_cfg_phy(dram_timing);
  74
  75         do {
  76                 tmp_t = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) +
  77                                    4 * 0x00020097);
  78         } while (tmp_t != 0);
  79
  80         reg32_write(DDRC_DFIMISC(0), 0x00000020);
  81
  82         /* wait DFISTAT.dfi_init_complete to 1 */
  83         while (0 == (0x1 & reg32_read(DDRC_DFISTAT(0))))
  84                 ;
  85
  86         /* clear DFIMISC.dfi_init_complete_en */
  87         reg32_write(DDRC_DFIMISC(0), 0x00000000);
  88         /* set DFIMISC.dfi_init_complete_en again */
  89         reg32_write(DDRC_DFIMISC(0), 0x00000001);
  90         reg32_write(DDRC_PWRCTL(0), 0x0000088);
  91
  92         /*
  93          * set SWCTL.sw_done to enable quasi-dynamic register
  94          * programming outside reset.
  95          */
  96         reg32_write(DDRC_SWCTL(0), 0x00000001);
  97         /* wait SWSTAT.sw_done_ack to 1 */
  98         while (0 == (0x1 & reg32_read(DDRC_SWSTAT(0))))
  99                 ;
 100
 101         /* wait STAT to normal state */
 102         while (0x1 != (0x7 & reg32_read(DDRC_STAT(0))))
 103                 ;
 104
 105         reg32_write(DDRC_PWRCTL(0), 0x0000088);
 106         reg32_write(DDRC_PCTRL_0(0), 0x00000001);
 107         /* dis_auto-refresh is set to 0 */
 108         reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
 109
 110         /* save the dram timing config into memory */
 111         dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
 112 }