drivers/ddr/fsl/util.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #ifdef CONFIG_PPC
   8 #include <asm/fsl_law.h>
   9 #endif
  10 #include <div64.h>
  11
  12 #include <fsl_ddr.h>
  13 #include <fsl_immap.h>
  14 #include <asm/io.h>
  15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  16         defined(CONFIG_ARM)
  17 #include <asm/arch/clock.h>
  18 #endif
  19
  20 /* To avoid 64-bit full-divides, we factor this here */
  21 #define ULL_2E12 2000000000000ULL
  22 #define UL_5POW12 244140625UL
  23 #define UL_2POW13 (1UL << 13)
  24
  25 #define ULL_8FS 0xFFFFFFFFULL
  26
  27 u32 fsl_ddr_get_version(unsigned int ctrl_num)
  28 {
  29         struct ccsr_ddr __iomem *ddr;
  30         u32 ver_major_minor_errata;
  31
  32         switch (ctrl_num) {
  33         case 0:
  34                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  35                 break;
  36 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  37         case 1:
  38                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  39                 break;
  40 #endif
  41 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  42         case 2:
  43                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  44                 break;
  45 #endif
  46 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
  47         case 3:
  48                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  49                 break;
  50 #endif
  51         default:
  52                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  53                 return 0;
  54         }
  55         ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
  56         ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
  57
  58         return ver_major_minor_errata;
  59 }
  60
  61 /*
  62  * Round up mclk_ps to nearest 1 ps in memory controller code
  63  * if the error is 0.5ps or more.
  64  *
  65  * If an imprecise data rate is too high due to rounding error
  66  * propagation, compute a suitably rounded mclk_ps to compute
  67  * a working memory controller configuration.
  68  */
  69 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
  70 {
  71         unsigned int data_rate = get_ddr_freq(ctrl_num);
  72         unsigned int result;
  73
  74         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  75         unsigned long long rem, mclk_ps = ULL_2E12;
  76
  77         /* Now perform the big divide, the result fits in 32-bits */
  78         rem = do_div(mclk_ps, data_rate);
  79         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
  80
  81         return result;
  82 }
  83
  84 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  85 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
  86 {
  87         unsigned long long clks, clks_rem;
  88         unsigned long data_rate = get_ddr_freq(ctrl_num);
  89
  90         /* Short circuit for zero picos */
  91         if (!picos)
  92                 return 0;
  93
  94         /* First multiply the time by the data rate (32x32 => 64) */
  95         clks = picos * (unsigned long long)data_rate;
  96         /*
  97          * Now divide by 5^12 and track the 32-bit remainder, then divide
  98          * by 2*(2^12) using shifts (and updating the remainder).
  99          */
 100         clks_rem = do_div(clks, UL_5POW12);
 101         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
 102         clks >>= 13;
 103
 104         /* If we had a remainder greater than the 1ps error, then round up */
 105         if (clks_rem > data_rate)
 106                 clks++;
 107
 108         /* Clamp to the maximum representable value */
 109         if (clks > ULL_8FS)
 110                 clks = ULL_8FS;
 111         return (unsigned int) clks;
 112 }
 113
 114 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
 115 {
 116         return get_memory_clk_period_ps(ctrl_num) * mclk;
 117 }
 118
 119 #ifdef CONFIG_PPC
 120 void
 121 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 122                            unsigned int law_memctl,
 123                            unsigned int ctrl_num)
 124 {
 125         unsigned long long base = memctl_common_params->base_address;
 126         unsigned long long size = memctl_common_params->total_mem;
 127
 128         /*
 129          * If no DIMMs on this controller, do not proceed any further.
 130          */
 131         if (!memctl_common_params->ndimms_present) {
 132                 return;
 133         }
 134
 135 #if !defined(CONFIG_PHYS_64BIT)
 136         if (base >= CONFIG_MAX_MEM_MAPPED)
 137                 return;
 138         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
 139                 size = CONFIG_MAX_MEM_MAPPED - base;
 140 #endif
 141         if (set_ddr_laws(base, size, law_memctl) < 0) {
 142                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
 143                         law_memctl);
 144                 return ;
 145         }
 146         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
 147                 base, size, law_memctl);
 148 }
 149
 150 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 151 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 152                          unsigned int memctl_interleaved,
 153                          unsigned int ctrl_num);
 154 #endif
 155
 156 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 157 {
 158 #ifdef CONFIG_E6500
 159         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 160         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
 161         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
 162 #endif
 163 }
 164
 165 u32 fsl_ddr_get_intl3r(void)
 166 {
 167         u32 val = 0;
 168 #ifdef CONFIG_E6500
 169         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 170         val = *mcintl3r;
 171 #endif
 172         return val;
 173 }
 174
 175 void print_ddr_info(unsigned int start_ctrl)
 176 {
 177         struct ccsr_ddr __iomem *ddr =
 178                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 179
 180 #if     defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 181         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 182 #endif
 183 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 184         uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 185 #endif
 186         uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 187         int cas_lat;
 188
 189 #if CONFIG_SYS_NUM_DDR_CTLRS >= 2
 190         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 191             (start_ctrl == 1)) {
 192                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 193                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 194         }
 195 #endif
 196 #if CONFIG_SYS_NUM_DDR_CTLRS >= 3
 197         if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
 198             (start_ctrl == 2)) {
 199                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
 200                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 201         }
 202 #endif
 203
 204         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 205                 puts(" (DDR not enabled)\n");
 206                 return;
 207         }
 208
 209         puts(" (DDR");
 210         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 211                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 212         case SDRAM_TYPE_DDR1:
 213                 puts("1");
 214                 break;
 215         case SDRAM_TYPE_DDR2:
 216                 puts("2");
 217                 break;
 218         case SDRAM_TYPE_DDR3:
 219                 puts("3");
 220                 break;
 221         case SDRAM_TYPE_DDR4:
 222                 puts("4");
 223                 break;
 224         default:
 225                 puts("?");
 226                 break;
 227         }
 228
 229         if (sdram_cfg & SDRAM_CFG_32_BE)
 230                 puts(", 32-bit");
 231         else if (sdram_cfg & SDRAM_CFG_16_BE)
 232                 puts(", 16-bit");
 233         else
 234                 puts(", 64-bit");
 235
 236         /* Calculate CAS latency based on timing cfg values */
 237         cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
 238         if (fsl_ddr_get_version(0) <= 0x40400)
 239                 cas_lat += 1;
 240         else
 241                 cas_lat += 2;
 242         cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
 243         printf(", CL=%d", cas_lat >> 1);
 244         if (cas_lat & 0x1)
 245                 puts(".5");
 246
 247         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 248                 puts(", ECC on)");
 249         else
 250                 puts(", ECC off)");
 251
 252 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
 253 #ifdef CONFIG_E6500
 254         if (*mcintl3r & 0x80000000) {
 255                 puts("\n");
 256                 puts("       DDR Controller Interleaving Mode: ");
 257                 switch (*mcintl3r & 0x1f) {
 258                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 259                         puts("3-way 1KB");
 260                         break;
 261                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 262                         puts("3-way 4KB");
 263                         break;
 264                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 265                         puts("3-way 8KB");
 266                         break;
 267                 default:
 268                         puts("3-way UNKNOWN");
 269                         break;
 270                 }
 271         }
 272 #endif
 273 #endif
 274 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 275         if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
 276                 puts("\n");
 277                 puts("       DDR Controller Interleaving Mode: ");
 278
 279                 switch ((cs0_config >> 24) & 0xf) {
 280                 case FSL_DDR_256B_INTERLEAVING:
 281                         puts("256B");
 282                         break;
 283                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 284                         puts("cache line");
 285                         break;
 286                 case FSL_DDR_PAGE_INTERLEAVING:
 287                         puts("page");
 288                         break;
 289                 case FSL_DDR_BANK_INTERLEAVING:
 290                         puts("bank");
 291                         break;
 292                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 293                         puts("super-bank");
 294                         break;
 295                 default:
 296                         puts("invalid");
 297                         break;
 298                 }
 299         }
 300 #endif
 301
 302         if ((sdram_cfg >> 8) & 0x7f) {
 303                 puts("\n");
 304                 puts("       DDR Chip-Select Interleaving Mode: ");
 305                 switch(sdram_cfg >> 8 & 0x7f) {
 306                 case FSL_DDR_CS0_CS1_CS2_CS3:
 307                         puts("CS0+CS1+CS2+CS3");
 308                         break;
 309                 case FSL_DDR_CS0_CS1:
 310                         puts("CS0+CS1");
 311                         break;
 312                 case FSL_DDR_CS2_CS3:
 313                         puts("CS2+CS3");
 314                         break;
 315                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 316                         puts("CS0+CS1 and CS2+CS3");
 317                         break;
 318                 default:
 319                         puts("invalid");
 320                         break;
 321                 }
 322         }
 323 }
 324
 325 void __weak detail_board_ddr_info(void)
 326 {
 327         print_ddr_info(0);
 328 }
 329
 330 void board_add_ram_info(int use_default)
 331 {
 332         detail_board_ddr_info();
 333 }
 334
 335 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 336 #define DDRC_DEBUG20_INIT_DONE  0x80000000
 337 #define DDRC_DEBUG2_RF          0x00000040
 338 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
 339                                  unsigned int last_ctrl)
 340 {
 341         unsigned int i;
 342         u32 ddrc_debug20;
 343         u32 ddrc_debug2[CONFIG_SYS_NUM_DDR_CTLRS] = {};
 344         u32 *ddrc_debug2_p[CONFIG_SYS_NUM_DDR_CTLRS] = {};
 345         struct ccsr_ddr __iomem *ddr;
 346
 347         for (i = first_ctrl; i <= last_ctrl; i++) {
 348                 switch (i) {
 349                 case 0:
 350                         ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 351                         break;
 352 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
 353                 case 1:
 354                         ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
 355                         break;
 356 #endif
 357 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
 358                 case 2:
 359                         ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
 360                         break;
 361 #endif
 362 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
 363                 case 3:
 364                         ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 365                         break;
 366 #endif
 367                 default:
 368                         printf("%s unexpected ctrl = %u\n", __func__, i);
 369                         return;
 370                 }
 371                 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 372                 ddrc_debug2_p[i] = &ddr->debug[1];
 373                 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
 374                         /* keep polling until DDRC init is done */
 375                         udelay(100);
 376                         ddrc_debug20 = ddr_in32(&ddr->debug[19]);
 377                 }
 378                 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
 379         }
 380         /*
 381          * Sync refresh
 382          * This is put together to make sure the refresh reqeusts are sent
 383          * closely to each other.
 384          */
 385         for (i = first_ctrl; i <= last_ctrl; i++)
 386                 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 387 }
 388 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
 389
 390 void remove_unused_controllers(fsl_ddr_info_t *info)
 391 {
 392 #ifdef CONFIG_SYS_FSL_HAS_CCN504
 393         int i;
 394         u64 nodeid;
 395         void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
 396         bool ddr0_used = false;
 397         bool ddr1_used = false;
 398
 399         for (i = 0; i < 8; i++) {
 400                 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
 401                 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
 402                         ddr0_used = true;
 403                 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
 404                         ddr1_used = true;
 405                 } else {
 406                         printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
 407                                nodeid);
 408                 }
 409                 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
 410         }
 411         if (!ddr0_used && !ddr1_used) {
 412                 printf("Invalid configuration in HN-F SAM control\n");
 413                 return;
 414         }
 415
 416         if (!ddr0_used && info->first_ctrl == 0) {
 417                 info->first_ctrl = 1;
 418                 info->num_ctrls = 1;
 419                 debug("First DDR controller disabled\n");
 420                 return;
 421         }
 422
 423         if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
 424                 info->num_ctrls = 1;
 425                 debug("Second DDR controller disabled\n");
 426         }
 427 #endif
 428 }