2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_law.h>
16 #include <fsl_immap.h>
19 /* To avoid 64-bit full-divides, we factor this here */
20 #define ULL_2E12 2000000000000ULL
21 #define UL_5POW12 244140625UL
22 #define UL_2POW13 (1UL << 13)
24 #define ULL_8FS 0xFFFFFFFFULL
26 u32 fsl_ddr_get_version(unsigned int ctrl_num)
28 struct ccsr_ddr __iomem *ddr;
29 u32 ver_major_minor_errata;
33 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
35 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
37 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
40 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
42 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
45 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
47 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
51 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
54 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
55 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
57 return ver_major_minor_errata;
61 * Round up mclk_ps to nearest 1 ps in memory controller code
62 * if the error is 0.5ps or more.
64 * If an imprecise data rate is too high due to rounding error
65 * propagation, compute a suitably rounded mclk_ps to compute
66 * a working memory controller configuration.
68 unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
70 unsigned int data_rate = get_ddr_freq(ctrl_num);
73 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
74 unsigned long long rem, mclk_ps = ULL_2E12;
76 /* Now perform the big divide, the result fits in 32-bits */
77 rem = do_div(mclk_ps, data_rate);
78 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
83 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
84 unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos)
86 unsigned long long clks, clks_rem;
87 unsigned long data_rate = get_ddr_freq(ctrl_num);
89 /* Short circuit for zero picos */
93 /* First multiply the time by the data rate (32x32 => 64) */
94 clks = picos * (unsigned long long)data_rate;
96 * Now divide by 5^12 and track the 32-bit remainder, then divide
97 * by 2*(2^12) using shifts (and updating the remainder).
99 clks_rem = do_div(clks, UL_5POW12);
100 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
103 /* If we had a remainder greater than the 1ps error, then round up */
104 if (clks_rem > data_rate)
107 /* Clamp to the maximum representable value */
110 return (unsigned int) clks;
113 unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk)
115 return get_memory_clk_period_ps(ctrl_num) * mclk;
120 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
121 unsigned int law_memctl,
122 unsigned int ctrl_num)
124 unsigned long long base = memctl_common_params->base_address;
125 unsigned long long size = memctl_common_params->total_mem;
128 * If no DIMMs on this controller, do not proceed any further.
130 if (!memctl_common_params->ndimms_present) {
134 #if !defined(CONFIG_PHYS_64BIT)
135 if (base >= CONFIG_MAX_MEM_MAPPED)
137 if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
138 size = CONFIG_MAX_MEM_MAPPED - base;
140 if (set_ddr_laws(base, size, law_memctl) < 0) {
141 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
145 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
146 base, size, law_memctl);
149 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
150 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
151 unsigned int memctl_interleaved,
152 unsigned int ctrl_num);
155 void fsl_ddr_set_intl3r(const unsigned int granule_size)
158 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
159 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
160 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
164 u32 fsl_ddr_get_intl3r(void)
168 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
174 void print_ddr_info(unsigned int start_ctrl)
176 struct ccsr_ddr __iomem *ddr =
177 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
179 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
180 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
182 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
183 uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
185 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
188 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
189 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
191 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
192 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
195 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
196 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
198 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
199 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
203 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
204 puts(" (DDR not enabled)\n");
209 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
210 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
211 case SDRAM_TYPE_DDR1:
214 case SDRAM_TYPE_DDR2:
217 case SDRAM_TYPE_DDR3:
220 case SDRAM_TYPE_DDR4:
228 if (sdram_cfg & SDRAM_CFG_32_BE)
230 else if (sdram_cfg & SDRAM_CFG_16_BE)
235 /* Calculate CAS latency based on timing cfg values */
236 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
237 if (fsl_ddr_get_version(0) <= 0x40400)
241 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
242 printf(", CL=%d", cas_lat >> 1);
246 if (sdram_cfg & SDRAM_CFG_ECC_EN)
251 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
253 if (*mcintl3r & 0x80000000) {
255 puts(" DDR Controller Interleaving Mode: ");
256 switch (*mcintl3r & 0x1f) {
257 case FSL_DDR_3WAY_1KB_INTERLEAVING:
260 case FSL_DDR_3WAY_4KB_INTERLEAVING:
263 case FSL_DDR_3WAY_8KB_INTERLEAVING:
267 puts("3-way UNKNOWN");
273 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
274 if ((cs0_config & 0x20000000) && (start_ctrl == 0)) {
276 puts(" DDR Controller Interleaving Mode: ");
278 switch ((cs0_config >> 24) & 0xf) {
279 case FSL_DDR_256B_INTERLEAVING:
282 case FSL_DDR_CACHE_LINE_INTERLEAVING:
285 case FSL_DDR_PAGE_INTERLEAVING:
288 case FSL_DDR_BANK_INTERLEAVING:
291 case FSL_DDR_SUPERBANK_INTERLEAVING:
301 if ((sdram_cfg >> 8) & 0x7f) {
303 puts(" DDR Chip-Select Interleaving Mode: ");
304 switch(sdram_cfg >> 8 & 0x7f) {
305 case FSL_DDR_CS0_CS1_CS2_CS3:
306 puts("CS0+CS1+CS2+CS3");
308 case FSL_DDR_CS0_CS1:
311 case FSL_DDR_CS2_CS3:
314 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
315 puts("CS0+CS1 and CS2+CS3");
324 void __weak detail_board_ddr_info(void)
329 void board_add_ram_info(int use_default)
331 detail_board_ddr_info();
334 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
335 #define DDRC_DEBUG20_INIT_DONE 0x80000000
336 #define DDRC_DEBUG2_RF 0x00000040
337 void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
338 unsigned int last_ctrl)
342 u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {};
343 u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {};
344 struct ccsr_ddr __iomem *ddr;
346 for (i = first_ctrl; i <= last_ctrl; i++) {
349 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
351 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
353 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
356 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
358 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
361 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
363 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
367 printf("%s unexpected ctrl = %u\n", __func__, i);
370 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
371 ddrc_debug2_p[i] = &ddr->debug[1];
372 while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) {
373 /* keep polling until DDRC init is done */
375 ddrc_debug20 = ddr_in32(&ddr->debug[19]);
377 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF;
381 * This is put together to make sure the refresh reqeusts are sent
382 * closely to each other.
384 for (i = first_ctrl; i <= last_ctrl; i++)
385 ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
387 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
389 void remove_unused_controllers(fsl_ddr_info_t *info)
391 #ifdef CONFIG_FSL_LSCH3
394 void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
395 bool ddr0_used = false;
396 bool ddr1_used = false;
398 for (i = 0; i < 8; i++) {
399 nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
400 if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
402 } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
405 printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
408 hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
410 if (!ddr0_used && !ddr1_used) {
411 printf("Invalid configuration in HN-F SAM control\n");
415 if (!ddr0_used && info->first_ctrl == 0) {
416 info->first_ctrl = 1;
418 debug("First DDR controller disabled\n");
422 if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
424 debug("Second DDR controller disabled\n");