2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
11 #include <asm/fsl_law.h>
16 #include <fsl_immap.h>
19 /* To avoid 64-bit full-divides, we factor this here */
20 #define ULL_2E12 2000000000000ULL
21 #define UL_5POW12 244140625UL
22 #define UL_2POW13 (1UL << 13)
24 #define ULL_8FS 0xFFFFFFFFULL
27 * Round up mclk_ps to nearest 1 ps in memory controller code
28 * if the error is 0.5ps or more.
30 * If an imprecise data rate is too high due to rounding error
31 * propagation, compute a suitably rounded mclk_ps to compute
32 * a working memory controller configuration.
34 unsigned int get_memory_clk_period_ps(void)
36 unsigned int data_rate = get_ddr_freq(0);
39 /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
40 unsigned long long rem, mclk_ps = ULL_2E12;
42 /* Now perform the big divide, the result fits in 32-bits */
43 rem = do_div(mclk_ps, data_rate);
44 result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
49 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
50 unsigned int picos_to_mclk(unsigned int picos)
52 unsigned long long clks, clks_rem;
53 unsigned long data_rate = get_ddr_freq(0);
55 /* Short circuit for zero picos */
59 /* First multiply the time by the data rate (32x32 => 64) */
60 clks = picos * (unsigned long long)data_rate;
62 * Now divide by 5^12 and track the 32-bit remainder, then divide
63 * by 2*(2^12) using shifts (and updating the remainder).
65 clks_rem = do_div(clks, UL_5POW12);
66 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
69 /* If we had a remainder greater than the 1ps error, then round up */
70 if (clks_rem > data_rate)
73 /* Clamp to the maximum representable value */
76 return (unsigned int) clks;
79 unsigned int mclk_to_picos(unsigned int mclk)
81 return get_memory_clk_period_ps() * mclk;
86 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
87 unsigned int law_memctl,
88 unsigned int ctrl_num)
90 unsigned long long base = memctl_common_params->base_address;
91 unsigned long long size = memctl_common_params->total_mem;
94 * If no DIMMs on this controller, do not proceed any further.
96 if (!memctl_common_params->ndimms_present) {
100 #if !defined(CONFIG_PHYS_64BIT)
101 if (base >= CONFIG_MAX_MEM_MAPPED)
103 if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
104 size = CONFIG_MAX_MEM_MAPPED - base;
106 if (set_ddr_laws(base, size, law_memctl) < 0) {
107 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
111 debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
112 base, size, law_memctl);
115 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
116 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
117 unsigned int memctl_interleaved,
118 unsigned int ctrl_num);
121 void fsl_ddr_set_intl3r(const unsigned int granule_size)
124 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
125 *mcintl3r = 0x80000000 | (granule_size & 0x1f);
126 debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
130 u32 fsl_ddr_get_intl3r(void)
134 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
140 void board_add_ram_info(int use_default)
142 struct ccsr_ddr __iomem *ddr =
143 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
145 #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
146 u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
148 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
149 uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
151 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
154 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
155 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
156 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
157 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
160 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
161 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
162 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
163 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
167 switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
168 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
169 case SDRAM_TYPE_DDR1:
172 case SDRAM_TYPE_DDR2:
175 case SDRAM_TYPE_DDR3:
183 if (sdram_cfg & SDRAM_CFG_32_BE)
185 else if (sdram_cfg & SDRAM_CFG_16_BE)
190 /* Calculate CAS latency based on timing cfg values */
191 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
192 if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1)
194 printf(", CL=%d", cas_lat >> 1);
198 if (sdram_cfg & SDRAM_CFG_ECC_EN)
203 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
205 if (*mcintl3r & 0x80000000) {
207 puts(" DDR Controller Interleaving Mode: ");
208 switch (*mcintl3r & 0x1f) {
209 case FSL_DDR_3WAY_1KB_INTERLEAVING:
212 case FSL_DDR_3WAY_4KB_INTERLEAVING:
215 case FSL_DDR_3WAY_8KB_INTERLEAVING:
219 puts("3-way UNKNOWN");
225 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
226 if (cs0_config & 0x20000000) {
228 puts(" DDR Controller Interleaving Mode: ");
230 switch ((cs0_config >> 24) & 0xf) {
231 case FSL_DDR_CACHE_LINE_INTERLEAVING:
234 case FSL_DDR_PAGE_INTERLEAVING:
237 case FSL_DDR_BANK_INTERLEAVING:
240 case FSL_DDR_SUPERBANK_INTERLEAVING:
250 if ((sdram_cfg >> 8) & 0x7f) {
252 puts(" DDR Chip-Select Interleaving Mode: ");
253 switch(sdram_cfg >> 8 & 0x7f) {
254 case FSL_DDR_CS0_CS1_CS2_CS3:
255 puts("CS0+CS1+CS2+CS3");
257 case FSL_DDR_CS0_CS1:
260 case FSL_DDR_CS2_CS3:
263 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
264 puts("CS0+CS1 and CS2+CS3");