1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
9 #include <fsl_ddr_sdram.h>
12 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
14 #include <asm/arch/clock.h>
18 * Use our own stack based buffer before relocation to allow accessing longer
19 * hwconfig strings that might be in the environment before we've relocated.
20 * This is pretty fragile on both the use of stack and if the buffer is big
21 * enough. However we will get a warning from env_get_f() for the latter.
24 /* Board-specific functions defined in each board's ddr.c */
25 void __weak fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num)
33 unsigned int odt_rd_cfg;
34 unsigned int odt_wr_cfg;
35 unsigned int odt_rtt_norm;
36 unsigned int odt_rtt_wr;
39 #ifdef CONFIG_SYS_FSL_DDR4
40 /* Quad rank is not verified yet due availability.
41 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
43 static __maybe_unused const struct dynamic_odt single_Q[4] = {
46 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
47 DDR4_RTT_34_OHM, /* unverified */
58 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
64 FSL_DDR_ODT_NEVER, /* tied high */
70 static __maybe_unused const struct dynamic_odt single_D[4] = {
87 static __maybe_unused const struct dynamic_odt single_S[4] = {
99 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
102 FSL_DDR_ODT_SAME_DIMM,
107 FSL_DDR_ODT_OTHER_DIMM,
108 FSL_DDR_ODT_OTHER_DIMM,
114 FSL_DDR_ODT_SAME_DIMM,
119 FSL_DDR_ODT_OTHER_DIMM,
120 FSL_DDR_ODT_OTHER_DIMM,
126 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
129 FSL_DDR_ODT_SAME_DIMM,
134 FSL_DDR_ODT_OTHER_DIMM,
135 FSL_DDR_ODT_OTHER_DIMM,
140 FSL_DDR_ODT_OTHER_DIMM,
147 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
149 FSL_DDR_ODT_OTHER_DIMM,
157 FSL_DDR_ODT_SAME_DIMM,
162 FSL_DDR_ODT_OTHER_DIMM,
163 FSL_DDR_ODT_OTHER_DIMM,
169 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
171 FSL_DDR_ODT_OTHER_DIMM,
178 FSL_DDR_ODT_OTHER_DIMM,
186 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
189 FSL_DDR_ODT_SAME_DIMM,
203 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
208 FSL_DDR_ODT_SAME_DIMM,
220 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
233 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
246 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
272 #elif defined(CONFIG_SYS_FSL_DDR3)
273 static __maybe_unused const struct dynamic_odt single_Q[4] = {
276 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
282 FSL_DDR_ODT_NEVER, /* tied high */
288 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
294 FSL_DDR_ODT_NEVER, /* tied high */
300 static __maybe_unused const struct dynamic_odt single_D[4] = {
317 static __maybe_unused const struct dynamic_odt single_S[4] = {
329 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
332 FSL_DDR_ODT_SAME_DIMM,
337 FSL_DDR_ODT_OTHER_DIMM,
338 FSL_DDR_ODT_OTHER_DIMM,
344 FSL_DDR_ODT_SAME_DIMM,
349 FSL_DDR_ODT_OTHER_DIMM,
350 FSL_DDR_ODT_OTHER_DIMM,
356 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
359 FSL_DDR_ODT_SAME_DIMM,
364 FSL_DDR_ODT_OTHER_DIMM,
365 FSL_DDR_ODT_OTHER_DIMM,
370 FSL_DDR_ODT_OTHER_DIMM,
377 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
379 FSL_DDR_ODT_OTHER_DIMM,
387 FSL_DDR_ODT_SAME_DIMM,
392 FSL_DDR_ODT_OTHER_DIMM,
393 FSL_DDR_ODT_OTHER_DIMM,
399 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
401 FSL_DDR_ODT_OTHER_DIMM,
408 FSL_DDR_ODT_OTHER_DIMM,
416 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
419 FSL_DDR_ODT_SAME_DIMM,
433 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
438 FSL_DDR_ODT_SAME_DIMM,
450 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
463 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
476 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
502 #else /* CONFIG_SYS_FSL_DDR3 */
503 static __maybe_unused const struct dynamic_odt single_Q[4] = {
510 static __maybe_unused const struct dynamic_odt single_D[4] = {
527 static __maybe_unused const struct dynamic_odt single_S[4] = {
539 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
541 FSL_DDR_ODT_OTHER_DIMM,
542 FSL_DDR_ODT_OTHER_DIMM,
553 FSL_DDR_ODT_OTHER_DIMM,
554 FSL_DDR_ODT_OTHER_DIMM,
566 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
568 FSL_DDR_ODT_OTHER_DIMM,
569 FSL_DDR_ODT_OTHER_DIMM,
580 FSL_DDR_ODT_OTHER_DIMM,
581 FSL_DDR_ODT_OTHER_DIMM,
588 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
590 FSL_DDR_ODT_OTHER_DIMM,
591 FSL_DDR_ODT_OTHER_DIMM,
597 FSL_DDR_ODT_OTHER_DIMM,
598 FSL_DDR_ODT_OTHER_DIMM,
610 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
612 FSL_DDR_ODT_OTHER_DIMM,
613 FSL_DDR_ODT_OTHER_DIMM,
619 FSL_DDR_ODT_OTHER_DIMM,
620 FSL_DDR_ODT_OTHER_DIMM,
627 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
644 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
661 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
674 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
687 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
716 * Automatically seleect bank interleaving mode based on DIMMs
717 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
718 * This function only deal with one or two slots per controller.
720 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
722 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
723 if (pdimm[0].n_ranks == 4)
724 return FSL_DDR_CS0_CS1_CS2_CS3;
725 else if (pdimm[0].n_ranks == 2)
726 return FSL_DDR_CS0_CS1;
727 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
728 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
729 if (pdimm[0].n_ranks == 4)
730 return FSL_DDR_CS0_CS1_CS2_CS3;
732 if (pdimm[0].n_ranks == 2) {
733 if (pdimm[1].n_ranks == 2)
734 return FSL_DDR_CS0_CS1_CS2_CS3;
736 return FSL_DDR_CS0_CS1;
742 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
743 memctl_options_t *popts,
744 dimm_params_t *pdimm,
745 unsigned int ctrl_num)
748 char buf[HWCONFIG_BUFFER_SIZE];
749 #if defined(CONFIG_SYS_FSL_DDR3) || \
750 defined(CONFIG_SYS_FSL_DDR2) || \
751 defined(CONFIG_SYS_FSL_DDR4)
752 const struct dynamic_odt *pdodt = odt_unknown;
754 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
759 * Extract hwconfig from environment since we have not properly setup
760 * the environment but need it for ddr config params
762 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
765 #if defined(CONFIG_SYS_FSL_DDR3) || \
766 defined(CONFIG_SYS_FSL_DDR2) || \
767 defined(CONFIG_SYS_FSL_DDR4)
768 /* Chip select options. */
769 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
770 switch (pdimm[0].n_ranks) {
781 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
782 switch (pdimm[0].n_ranks) {
783 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
786 if (pdimm[1].n_ranks)
787 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
791 switch (pdimm[1].n_ranks) {
804 switch (pdimm[1].n_ranks) {
817 switch (pdimm[1].n_ranks) {
827 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
828 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
830 /* Pick chip-select local options. */
831 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
832 #if defined(CONFIG_SYS_FSL_DDR3) || \
833 defined(CONFIG_SYS_FSL_DDR2) || \
834 defined(CONFIG_SYS_FSL_DDR4)
835 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
836 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
837 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
838 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
840 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
841 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
843 popts->cs_local_opts[i].auto_precharge = 0;
846 /* Pick interleaving mode. */
849 * 0 = no interleaving
850 * 1 = interleaving between 2 controllers
852 popts->memctl_interleaving = 0;
858 * 3 = superbank (only if CS interleaving is enabled)
860 popts->memctl_interleaving_mode = 0;
863 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
864 * 1: page: bit to the left of the column bits selects the memctl
865 * 2: bank: bit to the left of the bank bits selects the memctl
866 * 3: superbank: bit to the left of the chip select selects the memctl
868 * NOTE: ba_intlv (rank interleaving) is independent of memory
869 * controller interleaving; it is only within a memory controller.
870 * Must use superbank interleaving if rank interleaving is used and
871 * memory controller interleaving is enabled.
878 * 0x60 = CS0,CS1 + CS2,CS3
879 * 0x04 = CS0,CS1,CS2,CS3
881 popts->ba_intlv_ctl = 0;
883 /* Memory Organization Parameters */
884 popts->registered_dimm_en = common_dimm->all_dimms_registered;
886 /* Operational Mode Paramters */
889 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
890 #ifdef CONFIG_DDR_ECC
891 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
892 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
897 /* 1 = use memory controler to init data */
898 popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
905 #if defined(CONFIG_SYS_FSL_DDR1)
906 popts->dqs_config = 0;
907 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
908 popts->dqs_config = 1;
911 /* Choose self-refresh during sleep. */
912 popts->self_refresh_in_sleep = 1;
914 /* Choose dynamic power management mode. */
915 popts->dynamic_power = 0;
918 * check first dimm for primary sdram width
919 * presuming all dimms are similar
920 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
922 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
923 if (pdimm[0].n_ranks != 0) {
924 if ((pdimm[0].data_width >= 64) && \
925 (pdimm[0].data_width <= 72))
926 popts->data_bus_width = 0;
927 else if ((pdimm[0].data_width >= 32) && \
928 (pdimm[0].data_width <= 40))
929 popts->data_bus_width = 1;
931 panic("Error: data width %u is invalid!\n",
932 pdimm[0].data_width);
936 if (pdimm[0].n_ranks != 0) {
937 if (pdimm[0].primary_sdram_width == 64)
938 popts->data_bus_width = 0;
939 else if (pdimm[0].primary_sdram_width == 32)
940 popts->data_bus_width = 1;
941 else if (pdimm[0].primary_sdram_width == 16)
942 popts->data_bus_width = 2;
944 panic("Error: primary sdram width %u is invalid!\n",
945 pdimm[0].primary_sdram_width);
950 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
952 /* Choose burst length. */
953 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
954 #if defined(CONFIG_E500MC)
955 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
956 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
958 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
959 /* 32-bit or 16-bit bus */
960 popts->otf_burst_chop_en = 0;
961 popts->burst_length = DDR_BL8;
963 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
964 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
968 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
971 /* Choose ddr controller address mirror mode */
972 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
973 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
974 if (pdimm[i].n_ranks) {
975 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
981 /* Global Timing Parameters. */
982 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
984 /* Pick a caslat override. */
985 popts->cas_latency_override = 0;
986 popts->cas_latency_override_value = 3;
987 if (popts->cas_latency_override) {
988 debug("using caslat override value = %u\n",
989 popts->cas_latency_override_value);
992 /* Decide whether to use the computed derated latency */
993 popts->use_derated_caslat = 0;
995 /* Choose an additive latency. */
996 popts->additive_latency_override = 0;
997 popts->additive_latency_override_value = 3;
998 if (popts->additive_latency_override) {
999 debug("using additive latency override value = %u\n",
1000 popts->additive_latency_override_value);
1006 * Factors to consider for 2T_EN:
1007 * - number of DIMMs installed
1008 * - number of components, number of active ranks
1009 * - how much time you want to spend playing around
1012 popts->threet_en = 0;
1014 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1015 if (popts->registered_dimm_en)
1016 popts->ap_en = 1; /* 0 = disable, 1 = enable */
1018 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1020 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
1021 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
1022 if (popts->registered_dimm_en ||
1023 (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
1029 * BSTTOPRE precharge interval
1031 * Set this to 0 for global auto precharge
1032 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1033 * It is not wrong. Any value should be OK. The performance depends on
1034 * applications. There is no one good value for all. One way to set
1035 * is to use 1/4 of refint value.
1037 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1041 * Window for four activates -- tFAW
1043 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1044 * FIXME: varies depending upon number of column addresses or data
1045 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1047 #if defined(CONFIG_SYS_FSL_DDR1)
1048 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1050 #elif defined(CONFIG_SYS_FSL_DDR2)
1052 * x4/x8; some datasheets have 35000
1053 * x16 wide columns only? Use 50000?
1055 popts->tfaw_window_four_activates_ps = 37500;
1058 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1061 popts->wrlvl_en = 0;
1062 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1064 * due to ddr3 dimm is fly-by topology
1065 * we suggest to enable write leveling to
1066 * meet the tQDSS under different loading.
1068 popts->wrlvl_en = 1;
1070 popts->wrlvl_override = 0;
1074 * Check interleaving configuration from environment.
1075 * Please refer to doc/README.fsl-ddr for the detail.
1077 * If memory controller interleaving is enabled, then the data
1078 * bus widths must be programmed identically for all memory controllers.
1080 * Attempt to set all controllers to the same chip select
1081 * interleaving mode. It will do a best effort to get the
1082 * requested ranks interleaved together such that the result
1083 * should be a subset of the requested configuration.
1085 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1086 * with 256 Byte is enabled.
1088 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
1089 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1090 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1095 if (pdimm[0].n_ranks == 0) {
1096 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1097 popts->memctl_interleaving = 0;
1100 popts->memctl_interleaving = 1;
1101 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1102 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1103 popts->memctl_interleaving = 1;
1104 debug("256 Byte interleaving\n");
1107 * test null first. if CONFIG_HWCONFIG is not defined
1108 * hwconfig_arg_cmp returns non-zero
1110 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1112 popts->memctl_interleaving = 0;
1113 debug("memory controller interleaving disabled.\n");
1114 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1116 "cacheline", buf)) {
1117 popts->memctl_interleaving_mode =
1118 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1119 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1120 popts->memctl_interleaving =
1121 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1123 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1126 popts->memctl_interleaving_mode =
1127 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1128 0 : FSL_DDR_PAGE_INTERLEAVING;
1129 popts->memctl_interleaving =
1130 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1132 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1135 popts->memctl_interleaving_mode =
1136 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1137 0 : FSL_DDR_BANK_INTERLEAVING;
1138 popts->memctl_interleaving =
1139 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1141 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1143 "superbank", buf)) {
1144 popts->memctl_interleaving_mode =
1145 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1146 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1147 popts->memctl_interleaving =
1148 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1150 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
1151 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1154 popts->memctl_interleaving_mode =
1155 FSL_DDR_3WAY_1KB_INTERLEAVING;
1156 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1159 popts->memctl_interleaving_mode =
1160 FSL_DDR_3WAY_4KB_INTERLEAVING;
1161 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1164 popts->memctl_interleaving_mode =
1165 FSL_DDR_3WAY_8KB_INTERLEAVING;
1166 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
1167 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1170 popts->memctl_interleaving_mode =
1171 FSL_DDR_4WAY_1KB_INTERLEAVING;
1172 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1175 popts->memctl_interleaving_mode =
1176 FSL_DDR_4WAY_4KB_INTERLEAVING;
1177 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1180 popts->memctl_interleaving_mode =
1181 FSL_DDR_4WAY_8KB_INTERLEAVING;
1184 popts->memctl_interleaving = 0;
1185 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1187 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1189 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
1190 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1191 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1192 /* test null first. if CONFIG_HWCONFIG is not defined,
1193 * hwconfig_subarg_cmp_f returns non-zero */
1194 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1196 debug("bank interleaving disabled.\n");
1197 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1199 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1200 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1202 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1203 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1204 "cs0_cs1_and_cs2_cs3", buf))
1205 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1206 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1207 "cs0_cs1_cs2_cs3", buf))
1208 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1209 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1211 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1213 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1214 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1215 case FSL_DDR_CS0_CS1_CS2_CS3:
1216 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1217 if (pdimm[0].n_ranks < 4) {
1218 popts->ba_intlv_ctl = 0;
1219 printf("Not enough bank(chip-select) for "
1220 "CS0+CS1+CS2+CS3 on controller %d, "
1221 "interleaving disabled!\n", ctrl_num);
1223 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1224 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1225 if (pdimm[0].n_ranks == 4)
1228 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1229 popts->ba_intlv_ctl = 0;
1230 printf("Not enough bank(chip-select) for "
1231 "CS0+CS1+CS2+CS3 on controller %d, "
1232 "interleaving disabled!\n", ctrl_num);
1234 if (pdimm[0].capacity != pdimm[1].capacity) {
1235 popts->ba_intlv_ctl = 0;
1236 printf("Not identical DIMM size for "
1237 "CS0+CS1+CS2+CS3 on controller %d, "
1238 "interleaving disabled!\n", ctrl_num);
1242 case FSL_DDR_CS0_CS1:
1243 if (pdimm[0].n_ranks < 2) {
1244 popts->ba_intlv_ctl = 0;
1245 printf("Not enough bank(chip-select) for "
1246 "CS0+CS1 on controller %d, "
1247 "interleaving disabled!\n", ctrl_num);
1250 case FSL_DDR_CS2_CS3:
1251 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1252 if (pdimm[0].n_ranks < 4) {
1253 popts->ba_intlv_ctl = 0;
1254 printf("Not enough bank(chip-select) for CS2+CS3 "
1255 "on controller %d, interleaving disabled!\n", ctrl_num);
1257 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1258 if (pdimm[1].n_ranks < 2) {
1259 popts->ba_intlv_ctl = 0;
1260 printf("Not enough bank(chip-select) for CS2+CS3 "
1261 "on controller %d, interleaving disabled!\n", ctrl_num);
1265 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1266 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1267 if (pdimm[0].n_ranks < 4) {
1268 popts->ba_intlv_ctl = 0;
1269 printf("Not enough bank(CS) for CS0+CS1 and "
1270 "CS2+CS3 on controller %d, "
1271 "interleaving disabled!\n", ctrl_num);
1273 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1274 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1275 popts->ba_intlv_ctl = 0;
1276 printf("Not enough bank(CS) for CS0+CS1 and "
1277 "CS2+CS3 on controller %d, "
1278 "interleaving disabled!\n", ctrl_num);
1283 popts->ba_intlv_ctl = 0;
1288 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1289 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1290 popts->addr_hash = 0;
1291 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1293 popts->addr_hash = 1;
1296 if (pdimm[0].n_ranks == 4)
1297 popts->quad_rank_present = 1;
1299 popts->package_3ds = pdimm->package_3ds;
1301 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
1302 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1303 if (popts->registered_dimm_en) {
1304 popts->rcw_override = 1;
1305 popts->rcw_1 = 0x000a5a00;
1306 if (ddr_freq <= 800)
1307 popts->rcw_2 = 0x00000000;
1308 else if (ddr_freq <= 1066)
1309 popts->rcw_2 = 0x00100000;
1310 else if (ddr_freq <= 1333)
1311 popts->rcw_2 = 0x00200000;
1313 popts->rcw_2 = 0x00300000;
1317 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1322 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1324 int i, j, k, check_n_ranks, intlv_invalid = 0;
1325 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1326 unsigned long long check_rank_density;
1327 struct dimm_params_s *dimm;
1328 int first_ctrl = pinfo->first_ctrl;
1329 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1332 * Check if all controllers are configured for memory
1333 * controller interleaving. Identical dimms are recommended. At least
1334 * the size, row and col address should be checked.
1337 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1338 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1339 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1340 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1341 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1342 for (i = first_ctrl; i <= last_ctrl; i++) {
1343 dimm = &pinfo->dimm_params[i][0];
1344 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1346 } else if (((check_rank_density != dimm->rank_density) ||
1347 (check_n_ranks != dimm->n_ranks) ||
1348 (check_n_row_addr != dimm->n_row_addr) ||
1349 (check_n_col_addr != dimm->n_col_addr) ||
1351 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1359 if (intlv_invalid) {
1360 for (i = first_ctrl; i <= last_ctrl; i++)
1361 pinfo->memctl_opts[i].memctl_interleaving = 0;
1362 printf("Not all DIMMs are identical. "
1363 "Memory controller interleaving disabled.\n");
1365 switch (check_intlv) {
1366 case FSL_DDR_256B_INTERLEAVING:
1367 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1368 case FSL_DDR_PAGE_INTERLEAVING:
1369 case FSL_DDR_BANK_INTERLEAVING:
1370 case FSL_DDR_SUPERBANK_INTERLEAVING:
1371 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
1374 k = CONFIG_SYS_NUM_DDR_CTLRS;
1377 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1378 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1379 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1380 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1381 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1382 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1384 k = CONFIG_SYS_NUM_DDR_CTLRS;
1387 debug("%d of %d controllers are interleaving.\n", j, k);
1388 if (j && (j != k)) {
1389 for (i = first_ctrl; i <= last_ctrl; i++)
1390 pinfo->memctl_opts[i].memctl_interleaving = 0;
1391 if ((last_ctrl - first_ctrl) > 1)
1392 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1395 debug("Checking interleaving options completed\n");
1398 int fsl_use_spd(void)
1402 #ifdef CONFIG_DDR_SPD
1403 char buf[HWCONFIG_BUFFER_SIZE];
1406 * Extract hwconfig from environment since we have not properly setup
1407 * the environment but need it for ddr config params
1409 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
1412 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1413 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1414 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1416 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",