1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
10 #include <fsl_ddr_sdram.h>
14 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
16 #include <asm/arch/clock.h>
20 * Use our own stack based buffer before relocation to allow accessing longer
21 * hwconfig strings that might be in the environment before we've relocated.
22 * This is pretty fragile on both the use of stack and if the buffer is big
23 * enough. However we will get a warning from env_get_f() for the latter.
26 /* Board-specific functions defined in each board's ddr.c */
27 void __weak fsl_ddr_board_options(memctl_options_t *popts,
29 unsigned int ctrl_num)
35 unsigned int odt_rd_cfg;
36 unsigned int odt_wr_cfg;
37 unsigned int odt_rtt_norm;
38 unsigned int odt_rtt_wr;
41 #ifdef CONFIG_SYS_FSL_DDR4
42 /* Quad rank is not verified yet due availability.
43 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
45 static __maybe_unused const struct dynamic_odt single_Q[4] = {
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
49 DDR4_RTT_34_OHM, /* unverified */
60 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
66 FSL_DDR_ODT_NEVER, /* tied high */
72 static __maybe_unused const struct dynamic_odt single_D[4] = {
89 static __maybe_unused const struct dynamic_odt single_S[4] = {
101 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
104 FSL_DDR_ODT_SAME_DIMM,
109 FSL_DDR_ODT_OTHER_DIMM,
110 FSL_DDR_ODT_OTHER_DIMM,
116 FSL_DDR_ODT_SAME_DIMM,
121 FSL_DDR_ODT_OTHER_DIMM,
122 FSL_DDR_ODT_OTHER_DIMM,
128 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
131 FSL_DDR_ODT_SAME_DIMM,
136 FSL_DDR_ODT_OTHER_DIMM,
137 FSL_DDR_ODT_OTHER_DIMM,
142 FSL_DDR_ODT_OTHER_DIMM,
149 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
151 FSL_DDR_ODT_OTHER_DIMM,
159 FSL_DDR_ODT_SAME_DIMM,
164 FSL_DDR_ODT_OTHER_DIMM,
165 FSL_DDR_ODT_OTHER_DIMM,
171 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
173 FSL_DDR_ODT_OTHER_DIMM,
180 FSL_DDR_ODT_OTHER_DIMM,
188 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
191 FSL_DDR_ODT_SAME_DIMM,
205 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
210 FSL_DDR_ODT_SAME_DIMM,
222 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
235 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
248 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
274 #elif defined(CONFIG_SYS_FSL_DDR3)
275 static __maybe_unused const struct dynamic_odt single_Q[4] = {
278 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
284 FSL_DDR_ODT_NEVER, /* tied high */
290 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
296 FSL_DDR_ODT_NEVER, /* tied high */
302 static __maybe_unused const struct dynamic_odt single_D[4] = {
319 static __maybe_unused const struct dynamic_odt single_S[4] = {
331 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
334 FSL_DDR_ODT_SAME_DIMM,
339 FSL_DDR_ODT_OTHER_DIMM,
340 FSL_DDR_ODT_OTHER_DIMM,
346 FSL_DDR_ODT_SAME_DIMM,
351 FSL_DDR_ODT_OTHER_DIMM,
352 FSL_DDR_ODT_OTHER_DIMM,
358 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
361 FSL_DDR_ODT_SAME_DIMM,
366 FSL_DDR_ODT_OTHER_DIMM,
367 FSL_DDR_ODT_OTHER_DIMM,
372 FSL_DDR_ODT_OTHER_DIMM,
379 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
381 FSL_DDR_ODT_OTHER_DIMM,
389 FSL_DDR_ODT_SAME_DIMM,
394 FSL_DDR_ODT_OTHER_DIMM,
395 FSL_DDR_ODT_OTHER_DIMM,
401 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
403 FSL_DDR_ODT_OTHER_DIMM,
410 FSL_DDR_ODT_OTHER_DIMM,
418 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
421 FSL_DDR_ODT_SAME_DIMM,
435 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
440 FSL_DDR_ODT_SAME_DIMM,
452 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
465 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
478 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
504 #else /* CONFIG_SYS_FSL_DDR3 */
505 static __maybe_unused const struct dynamic_odt single_Q[4] = {
512 static __maybe_unused const struct dynamic_odt single_D[4] = {
529 static __maybe_unused const struct dynamic_odt single_S[4] = {
541 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
543 FSL_DDR_ODT_OTHER_DIMM,
544 FSL_DDR_ODT_OTHER_DIMM,
555 FSL_DDR_ODT_OTHER_DIMM,
556 FSL_DDR_ODT_OTHER_DIMM,
568 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
570 FSL_DDR_ODT_OTHER_DIMM,
571 FSL_DDR_ODT_OTHER_DIMM,
582 FSL_DDR_ODT_OTHER_DIMM,
583 FSL_DDR_ODT_OTHER_DIMM,
590 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
592 FSL_DDR_ODT_OTHER_DIMM,
593 FSL_DDR_ODT_OTHER_DIMM,
599 FSL_DDR_ODT_OTHER_DIMM,
600 FSL_DDR_ODT_OTHER_DIMM,
612 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
614 FSL_DDR_ODT_OTHER_DIMM,
615 FSL_DDR_ODT_OTHER_DIMM,
621 FSL_DDR_ODT_OTHER_DIMM,
622 FSL_DDR_ODT_OTHER_DIMM,
629 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
646 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
663 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
676 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
689 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
718 * Automatically seleect bank interleaving mode based on DIMMs
719 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
720 * This function only deal with one or two slots per controller.
722 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
724 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
725 if (pdimm[0].n_ranks == 4)
726 return FSL_DDR_CS0_CS1_CS2_CS3;
727 else if (pdimm[0].n_ranks == 2)
728 return FSL_DDR_CS0_CS1;
729 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
730 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
731 if (pdimm[0].n_ranks == 4)
732 return FSL_DDR_CS0_CS1_CS2_CS3;
734 if (pdimm[0].n_ranks == 2) {
735 if (pdimm[1].n_ranks == 2)
736 return FSL_DDR_CS0_CS1_CS2_CS3;
738 return FSL_DDR_CS0_CS1;
744 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
745 memctl_options_t *popts,
746 dimm_params_t *pdimm,
747 unsigned int ctrl_num)
750 char buf[HWCONFIG_BUFFER_SIZE];
751 #if defined(CONFIG_SYS_FSL_DDR3) || \
752 defined(CONFIG_SYS_FSL_DDR2) || \
753 defined(CONFIG_SYS_FSL_DDR4)
754 const struct dynamic_odt *pdodt = odt_unknown;
756 #if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
761 * Extract hwconfig from environment since we have not properly setup
762 * the environment but need it for ddr config params
764 #if CONFIG_IS_ENABLED(ENV_SUPPORT)
765 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
769 #if defined(CONFIG_SYS_FSL_DDR3) || \
770 defined(CONFIG_SYS_FSL_DDR2) || \
771 defined(CONFIG_SYS_FSL_DDR4)
772 /* Chip select options. */
773 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
774 switch (pdimm[0].n_ranks) {
785 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
786 switch (pdimm[0].n_ranks) {
787 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
790 if (pdimm[1].n_ranks)
791 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
795 switch (pdimm[1].n_ranks) {
808 switch (pdimm[1].n_ranks) {
821 switch (pdimm[1].n_ranks) {
831 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
832 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
834 /* Pick chip-select local options. */
835 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
836 #if defined(CONFIG_SYS_FSL_DDR3) || \
837 defined(CONFIG_SYS_FSL_DDR2) || \
838 defined(CONFIG_SYS_FSL_DDR4)
839 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
840 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
841 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
842 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
844 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
845 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
847 popts->cs_local_opts[i].auto_precharge = 0;
850 /* Pick interleaving mode. */
853 * 0 = no interleaving
854 * 1 = interleaving between 2 controllers
856 popts->memctl_interleaving = 0;
862 * 3 = superbank (only if CS interleaving is enabled)
864 popts->memctl_interleaving_mode = 0;
867 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
868 * 1: page: bit to the left of the column bits selects the memctl
869 * 2: bank: bit to the left of the bank bits selects the memctl
870 * 3: superbank: bit to the left of the chip select selects the memctl
872 * NOTE: ba_intlv (rank interleaving) is independent of memory
873 * controller interleaving; it is only within a memory controller.
874 * Must use superbank interleaving if rank interleaving is used and
875 * memory controller interleaving is enabled.
882 * 0x60 = CS0,CS1 + CS2,CS3
883 * 0x04 = CS0,CS1,CS2,CS3
885 popts->ba_intlv_ctl = 0;
887 /* Memory Organization Parameters */
888 popts->registered_dimm_en = common_dimm->all_dimms_registered;
890 /* Operational Mode Paramters */
893 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
894 #ifdef CONFIG_DDR_ECC
895 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
896 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
901 /* 1 = use memory controler to init data */
902 popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
909 #if defined(CONFIG_SYS_FSL_DDR1)
910 popts->dqs_config = 0;
911 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
912 popts->dqs_config = 1;
915 /* Choose self-refresh during sleep. */
916 popts->self_refresh_in_sleep = 1;
918 /* Choose dynamic power management mode. */
919 popts->dynamic_power = 0;
922 * check first dimm for primary sdram width
923 * presuming all dimms are similar
924 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
926 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
927 if (pdimm[0].n_ranks != 0) {
928 if ((pdimm[0].data_width >= 64) && \
929 (pdimm[0].data_width <= 72))
930 popts->data_bus_width = 0;
931 else if ((pdimm[0].data_width >= 32) && \
932 (pdimm[0].data_width <= 40))
933 popts->data_bus_width = 1;
935 panic("Error: data width %u is invalid!\n",
936 pdimm[0].data_width);
940 if (pdimm[0].n_ranks != 0) {
941 if (pdimm[0].primary_sdram_width == 64)
942 popts->data_bus_width = 0;
943 else if (pdimm[0].primary_sdram_width == 32)
944 popts->data_bus_width = 1;
945 else if (pdimm[0].primary_sdram_width == 16)
946 popts->data_bus_width = 2;
948 panic("Error: primary sdram width %u is invalid!\n",
949 pdimm[0].primary_sdram_width);
954 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
956 /* Choose burst length. */
957 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
958 #if defined(CONFIG_E500MC)
959 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
960 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
962 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
963 /* 32-bit or 16-bit bus */
964 popts->otf_burst_chop_en = 0;
965 popts->burst_length = DDR_BL8;
967 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
968 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
972 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
975 /* Choose ddr controller address mirror mode */
976 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
977 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
978 if (pdimm[i].n_ranks) {
979 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
985 /* Global Timing Parameters. */
986 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
988 /* Pick a caslat override. */
989 popts->cas_latency_override = 0;
990 popts->cas_latency_override_value = 3;
991 if (popts->cas_latency_override) {
992 debug("using caslat override value = %u\n",
993 popts->cas_latency_override_value);
996 /* Decide whether to use the computed derated latency */
997 popts->use_derated_caslat = 0;
999 /* Choose an additive latency. */
1000 popts->additive_latency_override = 0;
1001 popts->additive_latency_override_value = 3;
1002 if (popts->additive_latency_override) {
1003 debug("using additive latency override value = %u\n",
1004 popts->additive_latency_override_value);
1010 * Factors to consider for 2T_EN:
1011 * - number of DIMMs installed
1012 * - number of components, number of active ranks
1013 * - how much time you want to spend playing around
1016 popts->threet_en = 0;
1018 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1019 if (popts->registered_dimm_en)
1020 popts->ap_en = 1; /* 0 = disable, 1 = enable */
1022 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1024 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
1025 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
1026 if (popts->registered_dimm_en ||
1027 (CFG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
1033 * BSTTOPRE precharge interval
1035 * Set this to 0 for global auto precharge
1036 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1037 * It is not wrong. Any value should be OK. The performance depends on
1038 * applications. There is no one good value for all. One way to set
1039 * is to use 1/4 of refint value.
1041 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1045 * Window for four activates -- tFAW
1047 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1048 * FIXME: varies depending upon number of column addresses or data
1049 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1051 #if defined(CONFIG_SYS_FSL_DDR1)
1052 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1054 #elif defined(CONFIG_SYS_FSL_DDR2)
1056 * x4/x8; some datasheets have 35000
1057 * x16 wide columns only? Use 50000?
1059 popts->tfaw_window_four_activates_ps = 37500;
1062 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1065 popts->wrlvl_en = 0;
1066 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1068 * due to ddr3 dimm is fly-by topology
1069 * we suggest to enable write leveling to
1070 * meet the tQDSS under different loading.
1072 popts->wrlvl_en = 1;
1074 popts->wrlvl_override = 0;
1078 * Check interleaving configuration from environment.
1079 * Please refer to doc/README.fsl-ddr for the detail.
1081 * If memory controller interleaving is enabled, then the data
1082 * bus widths must be programmed identically for all memory controllers.
1084 * Attempt to set all controllers to the same chip select
1085 * interleaving mode. It will do a best effort to get the
1086 * requested ranks interleaved together such that the result
1087 * should be a subset of the requested configuration.
1089 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1090 * with 256 Byte is enabled.
1092 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
1093 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1094 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1099 if (pdimm[0].n_ranks == 0) {
1100 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1101 popts->memctl_interleaving = 0;
1104 popts->memctl_interleaving = 1;
1105 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1106 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1107 popts->memctl_interleaving = 1;
1108 debug("256 Byte interleaving\n");
1111 * test null first. if CONFIG_HWCONFIG is not defined
1112 * hwconfig_arg_cmp returns non-zero
1114 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1116 popts->memctl_interleaving = 0;
1117 debug("memory controller interleaving disabled.\n");
1118 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1120 "cacheline", buf)) {
1121 popts->memctl_interleaving_mode =
1122 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1123 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1124 popts->memctl_interleaving =
1125 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1127 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1130 popts->memctl_interleaving_mode =
1131 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1132 0 : FSL_DDR_PAGE_INTERLEAVING;
1133 popts->memctl_interleaving =
1134 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1136 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1139 popts->memctl_interleaving_mode =
1140 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1141 0 : FSL_DDR_BANK_INTERLEAVING;
1142 popts->memctl_interleaving =
1143 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1145 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1147 "superbank", buf)) {
1148 popts->memctl_interleaving_mode =
1149 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1150 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1151 popts->memctl_interleaving =
1152 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1154 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
1155 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1158 popts->memctl_interleaving_mode =
1159 FSL_DDR_3WAY_1KB_INTERLEAVING;
1160 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1163 popts->memctl_interleaving_mode =
1164 FSL_DDR_3WAY_4KB_INTERLEAVING;
1165 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1168 popts->memctl_interleaving_mode =
1169 FSL_DDR_3WAY_8KB_INTERLEAVING;
1170 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
1171 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1174 popts->memctl_interleaving_mode =
1175 FSL_DDR_4WAY_1KB_INTERLEAVING;
1176 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1179 popts->memctl_interleaving_mode =
1180 FSL_DDR_4WAY_4KB_INTERLEAVING;
1181 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1184 popts->memctl_interleaving_mode =
1185 FSL_DDR_4WAY_8KB_INTERLEAVING;
1188 popts->memctl_interleaving = 0;
1189 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1191 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1193 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
1194 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1195 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1196 /* test null first. if CONFIG_HWCONFIG is not defined,
1197 * hwconfig_subarg_cmp_f returns non-zero */
1198 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1200 debug("bank interleaving disabled.\n");
1201 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1203 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1204 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1206 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1207 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1208 "cs0_cs1_and_cs2_cs3", buf))
1209 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1210 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1211 "cs0_cs1_cs2_cs3", buf))
1212 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1213 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1215 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1217 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1218 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1219 case FSL_DDR_CS0_CS1_CS2_CS3:
1220 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1221 if (pdimm[0].n_ranks < 4) {
1222 popts->ba_intlv_ctl = 0;
1223 printf("Not enough bank(chip-select) for "
1224 "CS0+CS1+CS2+CS3 on controller %d, "
1225 "interleaving disabled!\n", ctrl_num);
1227 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1228 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1229 if (pdimm[0].n_ranks == 4)
1232 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1233 popts->ba_intlv_ctl = 0;
1234 printf("Not enough bank(chip-select) for "
1235 "CS0+CS1+CS2+CS3 on controller %d, "
1236 "interleaving disabled!\n", ctrl_num);
1238 if (pdimm[0].capacity != pdimm[1].capacity) {
1239 popts->ba_intlv_ctl = 0;
1240 printf("Not identical DIMM size for "
1241 "CS0+CS1+CS2+CS3 on controller %d, "
1242 "interleaving disabled!\n", ctrl_num);
1246 case FSL_DDR_CS0_CS1:
1247 if (pdimm[0].n_ranks < 2) {
1248 popts->ba_intlv_ctl = 0;
1249 printf("Not enough bank(chip-select) for "
1250 "CS0+CS1 on controller %d, "
1251 "interleaving disabled!\n", ctrl_num);
1254 case FSL_DDR_CS2_CS3:
1255 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1256 if (pdimm[0].n_ranks < 4) {
1257 popts->ba_intlv_ctl = 0;
1258 printf("Not enough bank(chip-select) for CS2+CS3 "
1259 "on controller %d, interleaving disabled!\n", ctrl_num);
1261 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1262 if (pdimm[1].n_ranks < 2) {
1263 popts->ba_intlv_ctl = 0;
1264 printf("Not enough bank(chip-select) for CS2+CS3 "
1265 "on controller %d, interleaving disabled!\n", ctrl_num);
1269 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1270 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1271 if (pdimm[0].n_ranks < 4) {
1272 popts->ba_intlv_ctl = 0;
1273 printf("Not enough bank(CS) for CS0+CS1 and "
1274 "CS2+CS3 on controller %d, "
1275 "interleaving disabled!\n", ctrl_num);
1277 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1278 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1279 popts->ba_intlv_ctl = 0;
1280 printf("Not enough bank(CS) for CS0+CS1 and "
1281 "CS2+CS3 on controller %d, "
1282 "interleaving disabled!\n", ctrl_num);
1287 popts->ba_intlv_ctl = 0;
1292 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1293 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1294 popts->addr_hash = 0;
1295 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1297 popts->addr_hash = 1;
1300 if (pdimm[0].n_ranks == 4)
1301 popts->quad_rank_present = 1;
1303 popts->package_3ds = pdimm->package_3ds;
1305 #if (CFG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
1306 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1307 if (popts->registered_dimm_en) {
1308 popts->rcw_override = 1;
1309 popts->rcw_1 = 0x000a5a00;
1310 if (ddr_freq <= 800)
1311 popts->rcw_2 = 0x00000000;
1312 else if (ddr_freq <= 1066)
1313 popts->rcw_2 = 0x00100000;
1314 else if (ddr_freq <= 1333)
1315 popts->rcw_2 = 0x00200000;
1317 popts->rcw_2 = 0x00300000;
1321 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1326 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1328 int i, j, k, check_n_ranks, intlv_invalid = 0;
1329 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1330 unsigned long long check_rank_density;
1331 struct dimm_params_s *dimm;
1332 int first_ctrl = pinfo->first_ctrl;
1333 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1336 * Check if all controllers are configured for memory
1337 * controller interleaving. Identical dimms are recommended. At least
1338 * the size, row and col address should be checked.
1341 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1342 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1343 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1344 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1345 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1346 for (i = first_ctrl; i <= last_ctrl; i++) {
1347 dimm = &pinfo->dimm_params[i][0];
1348 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1350 } else if (((check_rank_density != dimm->rank_density) ||
1351 (check_n_ranks != dimm->n_ranks) ||
1352 (check_n_row_addr != dimm->n_row_addr) ||
1353 (check_n_col_addr != dimm->n_col_addr) ||
1355 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1363 if (intlv_invalid) {
1364 for (i = first_ctrl; i <= last_ctrl; i++)
1365 pinfo->memctl_opts[i].memctl_interleaving = 0;
1366 printf("Not all DIMMs are identical. "
1367 "Memory controller interleaving disabled.\n");
1369 switch (check_intlv) {
1370 case FSL_DDR_256B_INTERLEAVING:
1371 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1372 case FSL_DDR_PAGE_INTERLEAVING:
1373 case FSL_DDR_BANK_INTERLEAVING:
1374 case FSL_DDR_SUPERBANK_INTERLEAVING:
1375 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
1378 k = CONFIG_SYS_NUM_DDR_CTLRS;
1381 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1382 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1383 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1384 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1385 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1386 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1388 k = CONFIG_SYS_NUM_DDR_CTLRS;
1391 debug("%d of %d controllers are interleaving.\n", j, k);
1392 if (j && (j != k)) {
1393 for (i = first_ctrl; i <= last_ctrl; i++)
1394 pinfo->memctl_opts[i].memctl_interleaving = 0;
1395 if ((last_ctrl - first_ctrl) > 1)
1396 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1399 debug("Checking interleaving options completed\n");
1402 int fsl_use_spd(void)
1406 #ifdef CONFIG_DDR_SPD
1407 char buf[HWCONFIG_BUFFER_SIZE];
1410 * Extract hwconfig from environment since we have not properly setup
1411 * the environment but need it for ddr config params
1413 #if CONFIG_IS_ENABLED(ENV_SUPPORT)
1414 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
1418 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1419 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1420 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1422 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",