1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
9 #include <fsl_ddr_sdram.h>
12 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
14 #include <asm/arch/clock.h>
18 * Use our own stack based buffer before relocation to allow accessing longer
19 * hwconfig strings that might be in the environment before we've relocated.
20 * This is pretty fragile on both the use of stack and if the buffer is big
21 * enough. However we will get a warning from env_get_f() for the latter.
24 /* Board-specific functions defined in each board's ddr.c */
25 extern void fsl_ddr_board_options(memctl_options_t *popts,
27 unsigned int ctrl_num);
30 unsigned int odt_rd_cfg;
31 unsigned int odt_wr_cfg;
32 unsigned int odt_rtt_norm;
33 unsigned int odt_rtt_wr;
36 #ifdef CONFIG_SYS_FSL_DDR4
37 /* Quad rank is not verified yet due availability.
38 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
40 static __maybe_unused const struct dynamic_odt single_Q[4] = {
43 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
44 DDR4_RTT_34_OHM, /* unverified */
55 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
61 FSL_DDR_ODT_NEVER, /* tied high */
67 static __maybe_unused const struct dynamic_odt single_D[4] = {
84 static __maybe_unused const struct dynamic_odt single_S[4] = {
96 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
99 FSL_DDR_ODT_SAME_DIMM,
104 FSL_DDR_ODT_OTHER_DIMM,
105 FSL_DDR_ODT_OTHER_DIMM,
111 FSL_DDR_ODT_SAME_DIMM,
116 FSL_DDR_ODT_OTHER_DIMM,
117 FSL_DDR_ODT_OTHER_DIMM,
123 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
126 FSL_DDR_ODT_SAME_DIMM,
131 FSL_DDR_ODT_OTHER_DIMM,
132 FSL_DDR_ODT_OTHER_DIMM,
137 FSL_DDR_ODT_OTHER_DIMM,
144 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
146 FSL_DDR_ODT_OTHER_DIMM,
154 FSL_DDR_ODT_SAME_DIMM,
159 FSL_DDR_ODT_OTHER_DIMM,
160 FSL_DDR_ODT_OTHER_DIMM,
166 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
168 FSL_DDR_ODT_OTHER_DIMM,
175 FSL_DDR_ODT_OTHER_DIMM,
183 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
186 FSL_DDR_ODT_SAME_DIMM,
200 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
205 FSL_DDR_ODT_SAME_DIMM,
217 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
230 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
243 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
269 #elif defined(CONFIG_SYS_FSL_DDR3)
270 static __maybe_unused const struct dynamic_odt single_Q[4] = {
273 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
279 FSL_DDR_ODT_NEVER, /* tied high */
285 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
291 FSL_DDR_ODT_NEVER, /* tied high */
297 static __maybe_unused const struct dynamic_odt single_D[4] = {
314 static __maybe_unused const struct dynamic_odt single_S[4] = {
326 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
329 FSL_DDR_ODT_SAME_DIMM,
334 FSL_DDR_ODT_OTHER_DIMM,
335 FSL_DDR_ODT_OTHER_DIMM,
341 FSL_DDR_ODT_SAME_DIMM,
346 FSL_DDR_ODT_OTHER_DIMM,
347 FSL_DDR_ODT_OTHER_DIMM,
353 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
356 FSL_DDR_ODT_SAME_DIMM,
361 FSL_DDR_ODT_OTHER_DIMM,
362 FSL_DDR_ODT_OTHER_DIMM,
367 FSL_DDR_ODT_OTHER_DIMM,
374 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
376 FSL_DDR_ODT_OTHER_DIMM,
384 FSL_DDR_ODT_SAME_DIMM,
389 FSL_DDR_ODT_OTHER_DIMM,
390 FSL_DDR_ODT_OTHER_DIMM,
396 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
398 FSL_DDR_ODT_OTHER_DIMM,
405 FSL_DDR_ODT_OTHER_DIMM,
413 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
416 FSL_DDR_ODT_SAME_DIMM,
430 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
435 FSL_DDR_ODT_SAME_DIMM,
447 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
460 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
473 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
499 #else /* CONFIG_SYS_FSL_DDR3 */
500 static __maybe_unused const struct dynamic_odt single_Q[4] = {
507 static __maybe_unused const struct dynamic_odt single_D[4] = {
524 static __maybe_unused const struct dynamic_odt single_S[4] = {
536 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
538 FSL_DDR_ODT_OTHER_DIMM,
539 FSL_DDR_ODT_OTHER_DIMM,
550 FSL_DDR_ODT_OTHER_DIMM,
551 FSL_DDR_ODT_OTHER_DIMM,
563 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
565 FSL_DDR_ODT_OTHER_DIMM,
566 FSL_DDR_ODT_OTHER_DIMM,
577 FSL_DDR_ODT_OTHER_DIMM,
578 FSL_DDR_ODT_OTHER_DIMM,
585 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
587 FSL_DDR_ODT_OTHER_DIMM,
588 FSL_DDR_ODT_OTHER_DIMM,
594 FSL_DDR_ODT_OTHER_DIMM,
595 FSL_DDR_ODT_OTHER_DIMM,
607 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
609 FSL_DDR_ODT_OTHER_DIMM,
610 FSL_DDR_ODT_OTHER_DIMM,
616 FSL_DDR_ODT_OTHER_DIMM,
617 FSL_DDR_ODT_OTHER_DIMM,
624 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
641 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
658 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
671 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
684 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
713 * Automatically seleect bank interleaving mode based on DIMMs
714 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
715 * This function only deal with one or two slots per controller.
717 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
719 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
720 if (pdimm[0].n_ranks == 4)
721 return FSL_DDR_CS0_CS1_CS2_CS3;
722 else if (pdimm[0].n_ranks == 2)
723 return FSL_DDR_CS0_CS1;
724 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
725 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
726 if (pdimm[0].n_ranks == 4)
727 return FSL_DDR_CS0_CS1_CS2_CS3;
729 if (pdimm[0].n_ranks == 2) {
730 if (pdimm[1].n_ranks == 2)
731 return FSL_DDR_CS0_CS1_CS2_CS3;
733 return FSL_DDR_CS0_CS1;
739 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
740 memctl_options_t *popts,
741 dimm_params_t *pdimm,
742 unsigned int ctrl_num)
745 char buf[HWCONFIG_BUFFER_SIZE];
746 #if defined(CONFIG_SYS_FSL_DDR3) || \
747 defined(CONFIG_SYS_FSL_DDR2) || \
748 defined(CONFIG_SYS_FSL_DDR4)
749 const struct dynamic_odt *pdodt = odt_unknown;
751 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
756 * Extract hwconfig from environment since we have not properly setup
757 * the environment but need it for ddr config params
759 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
762 #if defined(CONFIG_SYS_FSL_DDR3) || \
763 defined(CONFIG_SYS_FSL_DDR2) || \
764 defined(CONFIG_SYS_FSL_DDR4)
765 /* Chip select options. */
766 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
767 switch (pdimm[0].n_ranks) {
778 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
779 switch (pdimm[0].n_ranks) {
780 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
783 if (pdimm[1].n_ranks)
784 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
788 switch (pdimm[1].n_ranks) {
801 switch (pdimm[1].n_ranks) {
814 switch (pdimm[1].n_ranks) {
824 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
825 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
827 /* Pick chip-select local options. */
828 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
829 #if defined(CONFIG_SYS_FSL_DDR3) || \
830 defined(CONFIG_SYS_FSL_DDR2) || \
831 defined(CONFIG_SYS_FSL_DDR4)
832 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
833 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
834 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
835 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
837 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
838 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
840 popts->cs_local_opts[i].auto_precharge = 0;
843 /* Pick interleaving mode. */
846 * 0 = no interleaving
847 * 1 = interleaving between 2 controllers
849 popts->memctl_interleaving = 0;
855 * 3 = superbank (only if CS interleaving is enabled)
857 popts->memctl_interleaving_mode = 0;
860 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
861 * 1: page: bit to the left of the column bits selects the memctl
862 * 2: bank: bit to the left of the bank bits selects the memctl
863 * 3: superbank: bit to the left of the chip select selects the memctl
865 * NOTE: ba_intlv (rank interleaving) is independent of memory
866 * controller interleaving; it is only within a memory controller.
867 * Must use superbank interleaving if rank interleaving is used and
868 * memory controller interleaving is enabled.
875 * 0x60 = CS0,CS1 + CS2,CS3
876 * 0x04 = CS0,CS1,CS2,CS3
878 popts->ba_intlv_ctl = 0;
880 /* Memory Organization Parameters */
881 popts->registered_dimm_en = common_dimm->all_dimms_registered;
883 /* Operational Mode Paramters */
886 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
887 #ifdef CONFIG_DDR_ECC
888 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
889 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
894 /* 1 = use memory controler to init data */
895 popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
902 #if defined(CONFIG_SYS_FSL_DDR1)
903 popts->dqs_config = 0;
904 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
905 popts->dqs_config = 1;
908 /* Choose self-refresh during sleep. */
909 popts->self_refresh_in_sleep = 1;
911 /* Choose dynamic power management mode. */
912 popts->dynamic_power = 0;
915 * check first dimm for primary sdram width
916 * presuming all dimms are similar
917 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
919 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
920 if (pdimm[0].n_ranks != 0) {
921 if ((pdimm[0].data_width >= 64) && \
922 (pdimm[0].data_width <= 72))
923 popts->data_bus_width = 0;
924 else if ((pdimm[0].data_width >= 32) && \
925 (pdimm[0].data_width <= 40))
926 popts->data_bus_width = 1;
928 panic("Error: data width %u is invalid!\n",
929 pdimm[0].data_width);
933 if (pdimm[0].n_ranks != 0) {
934 if (pdimm[0].primary_sdram_width == 64)
935 popts->data_bus_width = 0;
936 else if (pdimm[0].primary_sdram_width == 32)
937 popts->data_bus_width = 1;
938 else if (pdimm[0].primary_sdram_width == 16)
939 popts->data_bus_width = 2;
941 panic("Error: primary sdram width %u is invalid!\n",
942 pdimm[0].primary_sdram_width);
947 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
949 /* Choose burst length. */
950 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
951 #if defined(CONFIG_E500MC)
952 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
953 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
955 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
956 /* 32-bit or 16-bit bus */
957 popts->otf_burst_chop_en = 0;
958 popts->burst_length = DDR_BL8;
960 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
961 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
965 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
968 /* Choose ddr controller address mirror mode */
969 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
970 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
971 if (pdimm[i].n_ranks) {
972 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
978 /* Global Timing Parameters. */
979 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
981 /* Pick a caslat override. */
982 popts->cas_latency_override = 0;
983 popts->cas_latency_override_value = 3;
984 if (popts->cas_latency_override) {
985 debug("using caslat override value = %u\n",
986 popts->cas_latency_override_value);
989 /* Decide whether to use the computed derated latency */
990 popts->use_derated_caslat = 0;
992 /* Choose an additive latency. */
993 popts->additive_latency_override = 0;
994 popts->additive_latency_override_value = 3;
995 if (popts->additive_latency_override) {
996 debug("using additive latency override value = %u\n",
997 popts->additive_latency_override_value);
1003 * Factors to consider for 2T_EN:
1004 * - number of DIMMs installed
1005 * - number of components, number of active ranks
1006 * - how much time you want to spend playing around
1009 popts->threet_en = 0;
1011 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1012 if (popts->registered_dimm_en)
1013 popts->ap_en = 1; /* 0 = disable, 1 = enable */
1015 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1017 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
1018 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
1019 if (popts->registered_dimm_en ||
1020 (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
1026 * BSTTOPRE precharge interval
1028 * Set this to 0 for global auto precharge
1029 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1030 * It is not wrong. Any value should be OK. The performance depends on
1031 * applications. There is no one good value for all. One way to set
1032 * is to use 1/4 of refint value.
1034 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1038 * Window for four activates -- tFAW
1040 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1041 * FIXME: varies depending upon number of column addresses or data
1042 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1044 #if defined(CONFIG_SYS_FSL_DDR1)
1045 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1047 #elif defined(CONFIG_SYS_FSL_DDR2)
1049 * x4/x8; some datasheets have 35000
1050 * x16 wide columns only? Use 50000?
1052 popts->tfaw_window_four_activates_ps = 37500;
1055 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1058 popts->wrlvl_en = 0;
1059 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1061 * due to ddr3 dimm is fly-by topology
1062 * we suggest to enable write leveling to
1063 * meet the tQDSS under different loading.
1065 popts->wrlvl_en = 1;
1067 popts->wrlvl_override = 0;
1071 * Check interleaving configuration from environment.
1072 * Please refer to doc/README.fsl-ddr for the detail.
1074 * If memory controller interleaving is enabled, then the data
1075 * bus widths must be programmed identically for all memory controllers.
1077 * Attempt to set all controllers to the same chip select
1078 * interleaving mode. It will do a best effort to get the
1079 * requested ranks interleaved together such that the result
1080 * should be a subset of the requested configuration.
1082 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1083 * with 256 Byte is enabled.
1085 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
1086 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1087 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1092 if (pdimm[0].n_ranks == 0) {
1093 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1094 popts->memctl_interleaving = 0;
1097 popts->memctl_interleaving = 1;
1098 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1099 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1100 popts->memctl_interleaving = 1;
1101 debug("256 Byte interleaving\n");
1104 * test null first. if CONFIG_HWCONFIG is not defined
1105 * hwconfig_arg_cmp returns non-zero
1107 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1109 popts->memctl_interleaving = 0;
1110 debug("memory controller interleaving disabled.\n");
1111 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1113 "cacheline", buf)) {
1114 popts->memctl_interleaving_mode =
1115 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1116 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1117 popts->memctl_interleaving =
1118 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1120 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1123 popts->memctl_interleaving_mode =
1124 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1125 0 : FSL_DDR_PAGE_INTERLEAVING;
1126 popts->memctl_interleaving =
1127 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1129 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1132 popts->memctl_interleaving_mode =
1133 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1134 0 : FSL_DDR_BANK_INTERLEAVING;
1135 popts->memctl_interleaving =
1136 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1138 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1140 "superbank", buf)) {
1141 popts->memctl_interleaving_mode =
1142 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1143 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1144 popts->memctl_interleaving =
1145 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1147 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
1148 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1151 popts->memctl_interleaving_mode =
1152 FSL_DDR_3WAY_1KB_INTERLEAVING;
1153 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1156 popts->memctl_interleaving_mode =
1157 FSL_DDR_3WAY_4KB_INTERLEAVING;
1158 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1161 popts->memctl_interleaving_mode =
1162 FSL_DDR_3WAY_8KB_INTERLEAVING;
1163 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
1164 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1167 popts->memctl_interleaving_mode =
1168 FSL_DDR_4WAY_1KB_INTERLEAVING;
1169 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1172 popts->memctl_interleaving_mode =
1173 FSL_DDR_4WAY_4KB_INTERLEAVING;
1174 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1177 popts->memctl_interleaving_mode =
1178 FSL_DDR_4WAY_8KB_INTERLEAVING;
1181 popts->memctl_interleaving = 0;
1182 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1184 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1186 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
1187 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1188 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1189 /* test null first. if CONFIG_HWCONFIG is not defined,
1190 * hwconfig_subarg_cmp_f returns non-zero */
1191 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1193 debug("bank interleaving disabled.\n");
1194 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1196 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1197 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1199 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1200 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1201 "cs0_cs1_and_cs2_cs3", buf))
1202 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1203 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1204 "cs0_cs1_cs2_cs3", buf))
1205 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1206 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1208 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1210 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1211 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1212 case FSL_DDR_CS0_CS1_CS2_CS3:
1213 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1214 if (pdimm[0].n_ranks < 4) {
1215 popts->ba_intlv_ctl = 0;
1216 printf("Not enough bank(chip-select) for "
1217 "CS0+CS1+CS2+CS3 on controller %d, "
1218 "interleaving disabled!\n", ctrl_num);
1220 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1221 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1222 if (pdimm[0].n_ranks == 4)
1225 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1226 popts->ba_intlv_ctl = 0;
1227 printf("Not enough bank(chip-select) for "
1228 "CS0+CS1+CS2+CS3 on controller %d, "
1229 "interleaving disabled!\n", ctrl_num);
1231 if (pdimm[0].capacity != pdimm[1].capacity) {
1232 popts->ba_intlv_ctl = 0;
1233 printf("Not identical DIMM size for "
1234 "CS0+CS1+CS2+CS3 on controller %d, "
1235 "interleaving disabled!\n", ctrl_num);
1239 case FSL_DDR_CS0_CS1:
1240 if (pdimm[0].n_ranks < 2) {
1241 popts->ba_intlv_ctl = 0;
1242 printf("Not enough bank(chip-select) for "
1243 "CS0+CS1 on controller %d, "
1244 "interleaving disabled!\n", ctrl_num);
1247 case FSL_DDR_CS2_CS3:
1248 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1249 if (pdimm[0].n_ranks < 4) {
1250 popts->ba_intlv_ctl = 0;
1251 printf("Not enough bank(chip-select) for CS2+CS3 "
1252 "on controller %d, interleaving disabled!\n", ctrl_num);
1254 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1255 if (pdimm[1].n_ranks < 2) {
1256 popts->ba_intlv_ctl = 0;
1257 printf("Not enough bank(chip-select) for CS2+CS3 "
1258 "on controller %d, interleaving disabled!\n", ctrl_num);
1262 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1263 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1264 if (pdimm[0].n_ranks < 4) {
1265 popts->ba_intlv_ctl = 0;
1266 printf("Not enough bank(CS) for CS0+CS1 and "
1267 "CS2+CS3 on controller %d, "
1268 "interleaving disabled!\n", ctrl_num);
1270 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1271 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1272 popts->ba_intlv_ctl = 0;
1273 printf("Not enough bank(CS) for CS0+CS1 and "
1274 "CS2+CS3 on controller %d, "
1275 "interleaving disabled!\n", ctrl_num);
1280 popts->ba_intlv_ctl = 0;
1285 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1286 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1287 popts->addr_hash = 0;
1288 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1290 popts->addr_hash = 1;
1293 if (pdimm[0].n_ranks == 4)
1294 popts->quad_rank_present = 1;
1296 popts->package_3ds = pdimm->package_3ds;
1298 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
1299 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1300 if (popts->registered_dimm_en) {
1301 popts->rcw_override = 1;
1302 popts->rcw_1 = 0x000a5a00;
1303 if (ddr_freq <= 800)
1304 popts->rcw_2 = 0x00000000;
1305 else if (ddr_freq <= 1066)
1306 popts->rcw_2 = 0x00100000;
1307 else if (ddr_freq <= 1333)
1308 popts->rcw_2 = 0x00200000;
1310 popts->rcw_2 = 0x00300000;
1314 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1319 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1321 int i, j, k, check_n_ranks, intlv_invalid = 0;
1322 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1323 unsigned long long check_rank_density;
1324 struct dimm_params_s *dimm;
1325 int first_ctrl = pinfo->first_ctrl;
1326 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1329 * Check if all controllers are configured for memory
1330 * controller interleaving. Identical dimms are recommended. At least
1331 * the size, row and col address should be checked.
1334 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1335 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1336 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1337 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1338 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1339 for (i = first_ctrl; i <= last_ctrl; i++) {
1340 dimm = &pinfo->dimm_params[i][0];
1341 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1343 } else if (((check_rank_density != dimm->rank_density) ||
1344 (check_n_ranks != dimm->n_ranks) ||
1345 (check_n_row_addr != dimm->n_row_addr) ||
1346 (check_n_col_addr != dimm->n_col_addr) ||
1348 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1356 if (intlv_invalid) {
1357 for (i = first_ctrl; i <= last_ctrl; i++)
1358 pinfo->memctl_opts[i].memctl_interleaving = 0;
1359 printf("Not all DIMMs are identical. "
1360 "Memory controller interleaving disabled.\n");
1362 switch (check_intlv) {
1363 case FSL_DDR_256B_INTERLEAVING:
1364 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1365 case FSL_DDR_PAGE_INTERLEAVING:
1366 case FSL_DDR_BANK_INTERLEAVING:
1367 case FSL_DDR_SUPERBANK_INTERLEAVING:
1368 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
1371 k = CONFIG_SYS_NUM_DDR_CTLRS;
1374 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1375 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1376 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1377 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1378 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1379 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1381 k = CONFIG_SYS_NUM_DDR_CTLRS;
1384 debug("%d of %d controllers are interleaving.\n", j, k);
1385 if (j && (j != k)) {
1386 for (i = first_ctrl; i <= last_ctrl; i++)
1387 pinfo->memctl_opts[i].memctl_interleaving = 0;
1388 if ((last_ctrl - first_ctrl) > 1)
1389 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1392 debug("Checking interleaving options completed\n");
1395 int fsl_use_spd(void)
1399 #ifdef CONFIG_DDR_SPD
1400 char buf[HWCONFIG_BUFFER_SIZE];
1403 * Extract hwconfig from environment since we have not properly setup
1404 * the environment but need it for ddr config params
1406 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
1409 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1410 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1411 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1413 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",