1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
10 #include <fsl_ddr_sdram.h>
14 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
16 #include <asm/arch/clock.h>
20 * Use our own stack based buffer before relocation to allow accessing longer
21 * hwconfig strings that might be in the environment before we've relocated.
22 * This is pretty fragile on both the use of stack and if the buffer is big
23 * enough. However we will get a warning from env_get_f() for the latter.
26 /* Board-specific functions defined in each board's ddr.c */
27 void __weak fsl_ddr_board_options(memctl_options_t *popts,
29 unsigned int ctrl_num)
35 unsigned int odt_rd_cfg;
36 unsigned int odt_wr_cfg;
37 unsigned int odt_rtt_norm;
38 unsigned int odt_rtt_wr;
41 #ifdef CONFIG_SYS_FSL_DDR4
42 /* Quad rank is not verified yet due availability.
43 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
45 static __maybe_unused const struct dynamic_odt single_Q[4] = {
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
49 DDR4_RTT_34_OHM, /* unverified */
60 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
66 FSL_DDR_ODT_NEVER, /* tied high */
72 static __maybe_unused const struct dynamic_odt single_D[4] = {
89 static __maybe_unused const struct dynamic_odt single_S[4] = {
101 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
104 FSL_DDR_ODT_SAME_DIMM,
109 FSL_DDR_ODT_OTHER_DIMM,
110 FSL_DDR_ODT_OTHER_DIMM,
116 FSL_DDR_ODT_SAME_DIMM,
121 FSL_DDR_ODT_OTHER_DIMM,
122 FSL_DDR_ODT_OTHER_DIMM,
128 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
131 FSL_DDR_ODT_SAME_DIMM,
136 FSL_DDR_ODT_OTHER_DIMM,
137 FSL_DDR_ODT_OTHER_DIMM,
142 FSL_DDR_ODT_OTHER_DIMM,
149 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
151 FSL_DDR_ODT_OTHER_DIMM,
159 FSL_DDR_ODT_SAME_DIMM,
164 FSL_DDR_ODT_OTHER_DIMM,
165 FSL_DDR_ODT_OTHER_DIMM,
171 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
173 FSL_DDR_ODT_OTHER_DIMM,
180 FSL_DDR_ODT_OTHER_DIMM,
188 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
191 FSL_DDR_ODT_SAME_DIMM,
205 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
210 FSL_DDR_ODT_SAME_DIMM,
222 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
235 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
248 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
274 #elif defined(CONFIG_SYS_FSL_DDR3)
275 static __maybe_unused const struct dynamic_odt single_Q[4] = {
278 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
284 FSL_DDR_ODT_NEVER, /* tied high */
290 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
296 FSL_DDR_ODT_NEVER, /* tied high */
302 static __maybe_unused const struct dynamic_odt single_D[4] = {
319 static __maybe_unused const struct dynamic_odt single_S[4] = {
331 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
334 FSL_DDR_ODT_SAME_DIMM,
339 FSL_DDR_ODT_OTHER_DIMM,
340 FSL_DDR_ODT_OTHER_DIMM,
346 FSL_DDR_ODT_SAME_DIMM,
351 FSL_DDR_ODT_OTHER_DIMM,
352 FSL_DDR_ODT_OTHER_DIMM,
358 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
361 FSL_DDR_ODT_SAME_DIMM,
366 FSL_DDR_ODT_OTHER_DIMM,
367 FSL_DDR_ODT_OTHER_DIMM,
372 FSL_DDR_ODT_OTHER_DIMM,
379 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
381 FSL_DDR_ODT_OTHER_DIMM,
389 FSL_DDR_ODT_SAME_DIMM,
394 FSL_DDR_ODT_OTHER_DIMM,
395 FSL_DDR_ODT_OTHER_DIMM,
401 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
403 FSL_DDR_ODT_OTHER_DIMM,
410 FSL_DDR_ODT_OTHER_DIMM,
418 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
421 FSL_DDR_ODT_SAME_DIMM,
435 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
440 FSL_DDR_ODT_SAME_DIMM,
452 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
465 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
478 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
504 #else /* CONFIG_SYS_FSL_DDR3 */
505 static __maybe_unused const struct dynamic_odt single_Q[4] = {
512 static __maybe_unused const struct dynamic_odt single_D[4] = {
529 static __maybe_unused const struct dynamic_odt single_S[4] = {
541 static __maybe_unused const struct dynamic_odt dual_DD[4] = {
543 FSL_DDR_ODT_OTHER_DIMM,
544 FSL_DDR_ODT_OTHER_DIMM,
555 FSL_DDR_ODT_OTHER_DIMM,
556 FSL_DDR_ODT_OTHER_DIMM,
568 static __maybe_unused const struct dynamic_odt dual_DS[4] = {
570 FSL_DDR_ODT_OTHER_DIMM,
571 FSL_DDR_ODT_OTHER_DIMM,
582 FSL_DDR_ODT_OTHER_DIMM,
583 FSL_DDR_ODT_OTHER_DIMM,
590 static __maybe_unused const struct dynamic_odt dual_SD[4] = {
592 FSL_DDR_ODT_OTHER_DIMM,
593 FSL_DDR_ODT_OTHER_DIMM,
599 FSL_DDR_ODT_OTHER_DIMM,
600 FSL_DDR_ODT_OTHER_DIMM,
612 static __maybe_unused const struct dynamic_odt dual_SS[4] = {
614 FSL_DDR_ODT_OTHER_DIMM,
615 FSL_DDR_ODT_OTHER_DIMM,
621 FSL_DDR_ODT_OTHER_DIMM,
622 FSL_DDR_ODT_OTHER_DIMM,
629 static __maybe_unused const struct dynamic_odt dual_D0[4] = {
646 static __maybe_unused const struct dynamic_odt dual_0D[4] = {
663 static __maybe_unused const struct dynamic_odt dual_S0[4] = {
676 static __maybe_unused const struct dynamic_odt dual_0S[4] = {
689 static __maybe_unused const struct dynamic_odt odt_unknown[4] = {
718 * Automatically seleect bank interleaving mode based on DIMMs
719 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
720 * This function only deal with one or two slots per controller.
722 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
724 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
725 if (pdimm[0].n_ranks == 4)
726 return FSL_DDR_CS0_CS1_CS2_CS3;
727 else if (pdimm[0].n_ranks == 2)
728 return FSL_DDR_CS0_CS1;
729 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
730 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
731 if (pdimm[0].n_ranks == 4)
732 return FSL_DDR_CS0_CS1_CS2_CS3;
734 if (pdimm[0].n_ranks == 2) {
735 if (pdimm[1].n_ranks == 2)
736 return FSL_DDR_CS0_CS1_CS2_CS3;
738 return FSL_DDR_CS0_CS1;
744 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
745 memctl_options_t *popts,
746 dimm_params_t *pdimm,
747 unsigned int ctrl_num)
750 char buf[HWCONFIG_BUFFER_SIZE];
751 #if defined(CONFIG_SYS_FSL_DDR3) || \
752 defined(CONFIG_SYS_FSL_DDR2) || \
753 defined(CONFIG_SYS_FSL_DDR4)
754 const struct dynamic_odt *pdodt = odt_unknown;
756 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
761 * Extract hwconfig from environment since we have not properly setup
762 * the environment but need it for ddr config params
764 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
767 #if defined(CONFIG_SYS_FSL_DDR3) || \
768 defined(CONFIG_SYS_FSL_DDR2) || \
769 defined(CONFIG_SYS_FSL_DDR4)
770 /* Chip select options. */
771 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
772 switch (pdimm[0].n_ranks) {
783 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
784 switch (pdimm[0].n_ranks) {
785 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
788 if (pdimm[1].n_ranks)
789 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
793 switch (pdimm[1].n_ranks) {
806 switch (pdimm[1].n_ranks) {
819 switch (pdimm[1].n_ranks) {
829 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
830 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
832 /* Pick chip-select local options. */
833 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
834 #if defined(CONFIG_SYS_FSL_DDR3) || \
835 defined(CONFIG_SYS_FSL_DDR2) || \
836 defined(CONFIG_SYS_FSL_DDR4)
837 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
838 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
839 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
840 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
842 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
843 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
845 popts->cs_local_opts[i].auto_precharge = 0;
848 /* Pick interleaving mode. */
851 * 0 = no interleaving
852 * 1 = interleaving between 2 controllers
854 popts->memctl_interleaving = 0;
860 * 3 = superbank (only if CS interleaving is enabled)
862 popts->memctl_interleaving_mode = 0;
865 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
866 * 1: page: bit to the left of the column bits selects the memctl
867 * 2: bank: bit to the left of the bank bits selects the memctl
868 * 3: superbank: bit to the left of the chip select selects the memctl
870 * NOTE: ba_intlv (rank interleaving) is independent of memory
871 * controller interleaving; it is only within a memory controller.
872 * Must use superbank interleaving if rank interleaving is used and
873 * memory controller interleaving is enabled.
880 * 0x60 = CS0,CS1 + CS2,CS3
881 * 0x04 = CS0,CS1,CS2,CS3
883 popts->ba_intlv_ctl = 0;
885 /* Memory Organization Parameters */
886 popts->registered_dimm_en = common_dimm->all_dimms_registered;
888 /* Operational Mode Paramters */
891 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
892 #ifdef CONFIG_DDR_ECC
893 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
894 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
899 /* 1 = use memory controler to init data */
900 popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
907 #if defined(CONFIG_SYS_FSL_DDR1)
908 popts->dqs_config = 0;
909 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
910 popts->dqs_config = 1;
913 /* Choose self-refresh during sleep. */
914 popts->self_refresh_in_sleep = 1;
916 /* Choose dynamic power management mode. */
917 popts->dynamic_power = 0;
920 * check first dimm for primary sdram width
921 * presuming all dimms are similar
922 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
924 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
925 if (pdimm[0].n_ranks != 0) {
926 if ((pdimm[0].data_width >= 64) && \
927 (pdimm[0].data_width <= 72))
928 popts->data_bus_width = 0;
929 else if ((pdimm[0].data_width >= 32) && \
930 (pdimm[0].data_width <= 40))
931 popts->data_bus_width = 1;
933 panic("Error: data width %u is invalid!\n",
934 pdimm[0].data_width);
938 if (pdimm[0].n_ranks != 0) {
939 if (pdimm[0].primary_sdram_width == 64)
940 popts->data_bus_width = 0;
941 else if (pdimm[0].primary_sdram_width == 32)
942 popts->data_bus_width = 1;
943 else if (pdimm[0].primary_sdram_width == 16)
944 popts->data_bus_width = 2;
946 panic("Error: primary sdram width %u is invalid!\n",
947 pdimm[0].primary_sdram_width);
952 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
954 /* Choose burst length. */
955 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
956 #if defined(CONFIG_E500MC)
957 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
958 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
960 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
961 /* 32-bit or 16-bit bus */
962 popts->otf_burst_chop_en = 0;
963 popts->burst_length = DDR_BL8;
965 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
966 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
970 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
973 /* Choose ddr controller address mirror mode */
974 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
975 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
976 if (pdimm[i].n_ranks) {
977 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
983 /* Global Timing Parameters. */
984 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
986 /* Pick a caslat override. */
987 popts->cas_latency_override = 0;
988 popts->cas_latency_override_value = 3;
989 if (popts->cas_latency_override) {
990 debug("using caslat override value = %u\n",
991 popts->cas_latency_override_value);
994 /* Decide whether to use the computed derated latency */
995 popts->use_derated_caslat = 0;
997 /* Choose an additive latency. */
998 popts->additive_latency_override = 0;
999 popts->additive_latency_override_value = 3;
1000 if (popts->additive_latency_override) {
1001 debug("using additive latency override value = %u\n",
1002 popts->additive_latency_override_value);
1008 * Factors to consider for 2T_EN:
1009 * - number of DIMMs installed
1010 * - number of components, number of active ranks
1011 * - how much time you want to spend playing around
1014 popts->threet_en = 0;
1016 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1017 if (popts->registered_dimm_en)
1018 popts->ap_en = 1; /* 0 = disable, 1 = enable */
1020 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1022 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
1023 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
1024 if (popts->registered_dimm_en ||
1025 (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
1031 * BSTTOPRE precharge interval
1033 * Set this to 0 for global auto precharge
1034 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1035 * It is not wrong. Any value should be OK. The performance depends on
1036 * applications. There is no one good value for all. One way to set
1037 * is to use 1/4 of refint value.
1039 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1043 * Window for four activates -- tFAW
1045 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1046 * FIXME: varies depending upon number of column addresses or data
1047 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1049 #if defined(CONFIG_SYS_FSL_DDR1)
1050 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1052 #elif defined(CONFIG_SYS_FSL_DDR2)
1054 * x4/x8; some datasheets have 35000
1055 * x16 wide columns only? Use 50000?
1057 popts->tfaw_window_four_activates_ps = 37500;
1060 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1063 popts->wrlvl_en = 0;
1064 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1066 * due to ddr3 dimm is fly-by topology
1067 * we suggest to enable write leveling to
1068 * meet the tQDSS under different loading.
1070 popts->wrlvl_en = 1;
1072 popts->wrlvl_override = 0;
1076 * Check interleaving configuration from environment.
1077 * Please refer to doc/README.fsl-ddr for the detail.
1079 * If memory controller interleaving is enabled, then the data
1080 * bus widths must be programmed identically for all memory controllers.
1082 * Attempt to set all controllers to the same chip select
1083 * interleaving mode. It will do a best effort to get the
1084 * requested ranks interleaved together such that the result
1085 * should be a subset of the requested configuration.
1087 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1088 * with 256 Byte is enabled.
1090 #if (CONFIG_SYS_NUM_DDR_CTLRS > 1)
1091 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1092 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1097 if (pdimm[0].n_ranks == 0) {
1098 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1099 popts->memctl_interleaving = 0;
1102 popts->memctl_interleaving = 1;
1103 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1104 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1105 popts->memctl_interleaving = 1;
1106 debug("256 Byte interleaving\n");
1109 * test null first. if CONFIG_HWCONFIG is not defined
1110 * hwconfig_arg_cmp returns non-zero
1112 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1114 popts->memctl_interleaving = 0;
1115 debug("memory controller interleaving disabled.\n");
1116 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1118 "cacheline", buf)) {
1119 popts->memctl_interleaving_mode =
1120 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1121 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1122 popts->memctl_interleaving =
1123 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1125 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1128 popts->memctl_interleaving_mode =
1129 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1130 0 : FSL_DDR_PAGE_INTERLEAVING;
1131 popts->memctl_interleaving =
1132 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1134 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1137 popts->memctl_interleaving_mode =
1138 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1139 0 : FSL_DDR_BANK_INTERLEAVING;
1140 popts->memctl_interleaving =
1141 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1143 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1145 "superbank", buf)) {
1146 popts->memctl_interleaving_mode =
1147 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1148 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1149 popts->memctl_interleaving =
1150 ((CONFIG_SYS_NUM_DDR_CTLRS == 3) && ctrl_num == 2) ?
1152 #if (CONFIG_SYS_NUM_DDR_CTLRS == 3)
1153 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1156 popts->memctl_interleaving_mode =
1157 FSL_DDR_3WAY_1KB_INTERLEAVING;
1158 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1161 popts->memctl_interleaving_mode =
1162 FSL_DDR_3WAY_4KB_INTERLEAVING;
1163 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1166 popts->memctl_interleaving_mode =
1167 FSL_DDR_3WAY_8KB_INTERLEAVING;
1168 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 4)
1169 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1172 popts->memctl_interleaving_mode =
1173 FSL_DDR_4WAY_1KB_INTERLEAVING;
1174 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1177 popts->memctl_interleaving_mode =
1178 FSL_DDR_4WAY_4KB_INTERLEAVING;
1179 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1182 popts->memctl_interleaving_mode =
1183 FSL_DDR_4WAY_8KB_INTERLEAVING;
1186 popts->memctl_interleaving = 0;
1187 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1189 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1191 #endif /* CONFIG_SYS_NUM_DDR_CTLRS > 1 */
1192 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1193 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1194 /* test null first. if CONFIG_HWCONFIG is not defined,
1195 * hwconfig_subarg_cmp_f returns non-zero */
1196 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1198 debug("bank interleaving disabled.\n");
1199 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1201 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1202 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1204 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1205 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1206 "cs0_cs1_and_cs2_cs3", buf))
1207 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1208 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1209 "cs0_cs1_cs2_cs3", buf))
1210 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1211 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1213 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1215 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1216 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1217 case FSL_DDR_CS0_CS1_CS2_CS3:
1218 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1219 if (pdimm[0].n_ranks < 4) {
1220 popts->ba_intlv_ctl = 0;
1221 printf("Not enough bank(chip-select) for "
1222 "CS0+CS1+CS2+CS3 on controller %d, "
1223 "interleaving disabled!\n", ctrl_num);
1225 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1226 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1227 if (pdimm[0].n_ranks == 4)
1230 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1231 popts->ba_intlv_ctl = 0;
1232 printf("Not enough bank(chip-select) for "
1233 "CS0+CS1+CS2+CS3 on controller %d, "
1234 "interleaving disabled!\n", ctrl_num);
1236 if (pdimm[0].capacity != pdimm[1].capacity) {
1237 popts->ba_intlv_ctl = 0;
1238 printf("Not identical DIMM size for "
1239 "CS0+CS1+CS2+CS3 on controller %d, "
1240 "interleaving disabled!\n", ctrl_num);
1244 case FSL_DDR_CS0_CS1:
1245 if (pdimm[0].n_ranks < 2) {
1246 popts->ba_intlv_ctl = 0;
1247 printf("Not enough bank(chip-select) for "
1248 "CS0+CS1 on controller %d, "
1249 "interleaving disabled!\n", ctrl_num);
1252 case FSL_DDR_CS2_CS3:
1253 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1254 if (pdimm[0].n_ranks < 4) {
1255 popts->ba_intlv_ctl = 0;
1256 printf("Not enough bank(chip-select) for CS2+CS3 "
1257 "on controller %d, interleaving disabled!\n", ctrl_num);
1259 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1260 if (pdimm[1].n_ranks < 2) {
1261 popts->ba_intlv_ctl = 0;
1262 printf("Not enough bank(chip-select) for CS2+CS3 "
1263 "on controller %d, interleaving disabled!\n", ctrl_num);
1267 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1268 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1269 if (pdimm[0].n_ranks < 4) {
1270 popts->ba_intlv_ctl = 0;
1271 printf("Not enough bank(CS) for CS0+CS1 and "
1272 "CS2+CS3 on controller %d, "
1273 "interleaving disabled!\n", ctrl_num);
1275 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1276 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1277 popts->ba_intlv_ctl = 0;
1278 printf("Not enough bank(CS) for CS0+CS1 and "
1279 "CS2+CS3 on controller %d, "
1280 "interleaving disabled!\n", ctrl_num);
1285 popts->ba_intlv_ctl = 0;
1290 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1291 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1292 popts->addr_hash = 0;
1293 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1295 popts->addr_hash = 1;
1298 if (pdimm[0].n_ranks == 4)
1299 popts->quad_rank_present = 1;
1301 popts->package_3ds = pdimm->package_3ds;
1303 #if (CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4)
1304 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1305 if (popts->registered_dimm_en) {
1306 popts->rcw_override = 1;
1307 popts->rcw_1 = 0x000a5a00;
1308 if (ddr_freq <= 800)
1309 popts->rcw_2 = 0x00000000;
1310 else if (ddr_freq <= 1066)
1311 popts->rcw_2 = 0x00100000;
1312 else if (ddr_freq <= 1333)
1313 popts->rcw_2 = 0x00200000;
1315 popts->rcw_2 = 0x00300000;
1319 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1324 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1326 int i, j, k, check_n_ranks, intlv_invalid = 0;
1327 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1328 unsigned long long check_rank_density;
1329 struct dimm_params_s *dimm;
1330 int first_ctrl = pinfo->first_ctrl;
1331 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1334 * Check if all controllers are configured for memory
1335 * controller interleaving. Identical dimms are recommended. At least
1336 * the size, row and col address should be checked.
1339 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1340 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1341 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1342 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1343 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1344 for (i = first_ctrl; i <= last_ctrl; i++) {
1345 dimm = &pinfo->dimm_params[i][0];
1346 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1348 } else if (((check_rank_density != dimm->rank_density) ||
1349 (check_n_ranks != dimm->n_ranks) ||
1350 (check_n_row_addr != dimm->n_row_addr) ||
1351 (check_n_col_addr != dimm->n_col_addr) ||
1353 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1361 if (intlv_invalid) {
1362 for (i = first_ctrl; i <= last_ctrl; i++)
1363 pinfo->memctl_opts[i].memctl_interleaving = 0;
1364 printf("Not all DIMMs are identical. "
1365 "Memory controller interleaving disabled.\n");
1367 switch (check_intlv) {
1368 case FSL_DDR_256B_INTERLEAVING:
1369 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1370 case FSL_DDR_PAGE_INTERLEAVING:
1371 case FSL_DDR_BANK_INTERLEAVING:
1372 case FSL_DDR_SUPERBANK_INTERLEAVING:
1373 #if (3 == CONFIG_SYS_NUM_DDR_CTLRS)
1376 k = CONFIG_SYS_NUM_DDR_CTLRS;
1379 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1380 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1381 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1382 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1383 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1384 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1386 k = CONFIG_SYS_NUM_DDR_CTLRS;
1389 debug("%d of %d controllers are interleaving.\n", j, k);
1390 if (j && (j != k)) {
1391 for (i = first_ctrl; i <= last_ctrl; i++)
1392 pinfo->memctl_opts[i].memctl_interleaving = 0;
1393 if ((last_ctrl - first_ctrl) > 1)
1394 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1397 debug("Checking interleaving options completed\n");
1400 int fsl_use_spd(void)
1404 #ifdef CONFIG_DDR_SPD
1405 char buf[HWCONFIG_BUFFER_SIZE];
1408 * Extract hwconfig from environment since we have not properly setup
1409 * the environment but need it for ddr config params
1411 if (env_get_f("hwconfig", buf, sizeof(buf)) < 0)
1414 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1415 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1416 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1418 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",