drivers/ddr/fsl/mpc85xx_ddr_gen3.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18
  19 /*
  20  * regs has the to-be-set values for DDR controller registers
  21  * ctrl_num is the DDR controller number
  22  * step: 0 goes through the initialization in one pass
  23  *       1 sets registers and returns before enabling controller
  24  *       2 resumes from step 1 and continues to initialize
  25  * Dividing the initialization to two steps to deassert DDR reset signal
  26  * to comply with JEDEC specs for RDIMMs.
  27  */
  28 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  29                              unsigned int ctrl_num, int step)
  30 {
  31         unsigned int i, bus_width;
  32         struct ccsr_ddr __iomem *ddr;
  33         u32 temp_sdram_cfg;
  34         u32 total_gb_size_per_controller;
  35         int timeout;
  36 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  37         int timeout_save;
  38         volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
  39         unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
  40         int csn = -1;
  41 #endif
  42 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
  43         u32 save1, save2;
  44 #endif
  45
  46         switch (ctrl_num) {
  47         case 0:
  48                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  49                 break;
  50 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  51         case 1:
  52                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  53                 break;
  54 #endif
  55 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  56         case 2:
  57                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  58                 break;
  59 #endif
  60 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  61         case 3:
  62                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  63                 break;
  64 #endif
  65         default:
  66                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  67                 return;
  68         }
  69
  70         if (step == 2)
  71                 goto step2;
  72
  73         if (regs->ddr_eor)
  74                 out_be32(&ddr->eor, regs->ddr_eor);
  75 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  76         debug("Workaround for ERRATUM_DDR111_DDR134\n");
  77         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  78                 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
  79                 cs_ea = regs->cs[i].bnds & 0xfff;
  80                 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
  81                         csn = i;
  82                         csn_bnds_backup = regs->cs[i].bnds;
  83                         csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
  84                         if (cs_ea > 0xeff)
  85                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
  86                         else
  87                                 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
  88                         debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
  89                                 "change it to 0x%x\n",
  90                                 csn, csn_bnds_backup, regs->cs[i].bnds);
  91                         break;
  92                 }
  93         }
  94 #endif
  95         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  96                 if (i == 0) {
  97                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  98                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  99                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
 100
 101                 } else if (i == 1) {
 102                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
 103                         out_be32(&ddr->cs1_config, regs->cs[i].config);
 104                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
 105
 106                 } else if (i == 2) {
 107                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
 108                         out_be32(&ddr->cs2_config, regs->cs[i].config);
 109                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
 110
 111                 } else if (i == 3) {
 112                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
 113                         out_be32(&ddr->cs3_config, regs->cs[i].config);
 114                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
 115                 }
 116         }
 117
 118         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 119         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 120         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 121         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 122         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 123         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 124         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 125         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 126         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 127         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 128         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 129         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 130         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 131         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 132         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 133         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
 134         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 135         out_be32(&ddr->init_addr, regs->ddr_init_addr);
 136         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 137
 138         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 139         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 140         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 141         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 142 #ifndef CONFIG_SYS_FSL_DDR_EMU
 143         /*
 144          * Skip these two registers if running on emulator
 145          * because emulator doesn't have skew between bytes.
 146          */
 147
 148         if (regs->ddr_wrlvl_cntl_2)
 149                 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 150         if (regs->ddr_wrlvl_cntl_3)
 151                 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 152 #endif
 153
 154         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 155         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 156         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 157         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 158         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 159         out_be32(&ddr->err_disable, regs->err_disable);
 160         out_be32(&ddr->err_int_en, regs->err_int_en);
 161         for (i = 0; i < 32; i++) {
 162                 if (regs->debug[i]) {
 163                         debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
 164                         out_be32(&ddr->debug[i], regs->debug[i]);
 165                 }
 166         }
 167 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
 168         out_be32(&ddr->debug[28], 0x30003000);
 169 #endif
 170
 171 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 172         out_be32(&ddr->debug[12], 0x00000015);
 173         out_be32(&ddr->debug[21], 0x24000000);
 174 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
 175
 176         /*
 177          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 178          * deasserted. Clocks start when any chip select is enabled and clock
 179          * control register is set. Because all DDR components are connected to
 180          * one reset signal, this needs to be done in two steps. Step 1 is to
 181          * get the clocks started. Step 2 resumes after reset signal is
 182          * deasserted.
 183          */
 184         if (step == 1) {
 185                 udelay(200);
 186                 return;
 187         }
 188
 189 step2:
 190         /* Set, but do not enable the memory */
 191         temp_sdram_cfg = regs->ddr_sdram_cfg;
 192         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 193         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 194 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 195         debug("Workaround for ERRATUM_DDR_A003\n");
 196         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 197                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 198                 out_be32(&ddr->debug[2], 0x00000400);
 199                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 200                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 201                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 202                 out_be32(&ddr->mtcr, 0);
 203                 save1 = in_be32(&ddr->debug[12]);
 204                 save2 = in_be32(&ddr->debug[21]);
 205                 out_be32(&ddr->debug[12], 0x00000015);
 206                 out_be32(&ddr->debug[21], 0x24000000);
 207                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 208                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 209
 210                 asm volatile("sync;isync");
 211                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 212                         ;
 213
 214                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 215                 case 0x00000000:
 216                         out_be32(&ddr->sdram_md_cntl,
 217                                 MD_CNTL_MD_EN           |
 218                                 MD_CNTL_CS_SEL_CS0_CS1  |
 219                                 0x04000000              |
 220                                 MD_CNTL_WRCW            |
 221                                 MD_CNTL_MD_VALUE(0x02));
 222 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 223                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 224                                 break;
 225                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 226                                 ;
 227                         out_be32(&ddr->sdram_md_cntl,
 228                                  MD_CNTL_MD_EN          |
 229                                  MD_CNTL_CS_SEL_CS2_CS3 |
 230                                  0x04000000             |
 231                                  MD_CNTL_WRCW           |
 232                                  MD_CNTL_MD_VALUE(0x02));
 233 #endif
 234                         break;
 235                 case 0x00100000:
 236                         out_be32(&ddr->sdram_md_cntl,
 237                                 MD_CNTL_MD_EN           |
 238                                 MD_CNTL_CS_SEL_CS0_CS1  |
 239                                 0x04000000              |
 240                                 MD_CNTL_WRCW            |
 241                                 MD_CNTL_MD_VALUE(0x0a));
 242 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 243                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 244                                 break;
 245                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 246                                 ;
 247                         out_be32(&ddr->sdram_md_cntl,
 248                                  MD_CNTL_MD_EN          |
 249                                  MD_CNTL_CS_SEL_CS2_CS3 |
 250                                  0x04000000             |
 251                                  MD_CNTL_WRCW           |
 252                                  MD_CNTL_MD_VALUE(0x0a));
 253 #endif
 254                         break;
 255                 case 0x00200000:
 256                         out_be32(&ddr->sdram_md_cntl,
 257                                 MD_CNTL_MD_EN           |
 258                                 MD_CNTL_CS_SEL_CS0_CS1  |
 259                                 0x04000000              |
 260                                 MD_CNTL_WRCW            |
 261                                 MD_CNTL_MD_VALUE(0x12));
 262 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 263                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 264                                 break;
 265                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 266                                 ;
 267                         out_be32(&ddr->sdram_md_cntl,
 268                                  MD_CNTL_MD_EN          |
 269                                  MD_CNTL_CS_SEL_CS2_CS3 |
 270                                  0x04000000             |
 271                                  MD_CNTL_WRCW           |
 272                                  MD_CNTL_MD_VALUE(0x12));
 273 #endif
 274                         break;
 275                 case 0x00300000:
 276                         out_be32(&ddr->sdram_md_cntl,
 277                                 MD_CNTL_MD_EN           |
 278                                 MD_CNTL_CS_SEL_CS0_CS1  |
 279                                 0x04000000              |
 280                                 MD_CNTL_WRCW            |
 281                                 MD_CNTL_MD_VALUE(0x1a));
 282 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 283                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 284                                 break;
 285                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 286                                 ;
 287                         out_be32(&ddr->sdram_md_cntl,
 288                                  MD_CNTL_MD_EN          |
 289                                  MD_CNTL_CS_SEL_CS2_CS3 |
 290                                  0x04000000             |
 291                                  MD_CNTL_WRCW           |
 292                                  MD_CNTL_MD_VALUE(0x1a));
 293 #endif
 294                         break;
 295                 default:
 296                         out_be32(&ddr->sdram_md_cntl,
 297                                 MD_CNTL_MD_EN           |
 298                                 MD_CNTL_CS_SEL_CS0_CS1  |
 299                                 0x04000000              |
 300                                 MD_CNTL_WRCW            |
 301                                 MD_CNTL_MD_VALUE(0x02));
 302 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 303                         if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
 304                                 break;
 305                         while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
 306                                 ;
 307                         out_be32(&ddr->sdram_md_cntl,
 308                                  MD_CNTL_MD_EN          |
 309                                  MD_CNTL_CS_SEL_CS2_CS3 |
 310                                  0x04000000             |
 311                                  MD_CNTL_WRCW           |
 312                                  MD_CNTL_MD_VALUE(0x02));
 313 #endif
 314                         printf("Unsupported RC10\n");
 315                         break;
 316                 }
 317
 318                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 319                         ;
 320                 udelay(6);
 321                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 322                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 323                 out_be32(&ddr->debug[2], 0x0);
 324                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 325                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 326                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 327                 out_be32(&ddr->debug[12], save1);
 328                 out_be32(&ddr->debug[21], save2);
 329                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 330
 331         }
 332 #endif
 333         /*
 334          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 335          * when operatiing in 32-bit bus mode with 4-beat bursts,
 336          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 337          */
 338 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
 339         debug("Workaround for ERRATUM_DDR_115\n");
 340         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 341             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 342                 /* set DEBUG_1[31] */
 343                 setbits_be32(&ddr->debug[0], 1);
 344         }
 345 #endif
 346 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 347         debug("Workaround for ERRATUM_DDR111_DDR134\n");
 348         /*
 349          * This is the combined workaround for DDR111 and DDR134
 350          * following the published errata for MPC8572
 351          */
 352
 353         /* 1. Set EEBACR[3] */
 354         setbits_be32(&ecm->eebacr, 0x10000000);
 355         debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 356
 357         /* 2. Set DINIT in SDRAM_CFG_2*/
 358         setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
 359         debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
 360                 in_be32(&ddr->sdram_cfg_2));
 361
 362         /* 3. Set DEBUG_3[21] */
 363         setbits_be32(&ddr->debug[2], 0x400);
 364         debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 365
 366 #endif  /* part 1 of the workaound */
 367
 368         /*
 369          * 500 painful micro-seconds must elapse between
 370          * the DDR clock setup and the DDR config enable.
 371          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 372          * we choose the max, that is 500 us for all of case.
 373          */
 374         udelay(500);
 375         asm volatile("sync;isync");
 376
 377         /* Let the controller go */
 378         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 379         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 380         asm volatile("sync;isync");
 381
 382         total_gb_size_per_controller = 0;
 383         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 384                 if (!(regs->cs[i].config & 0x80000000))
 385                         continue;
 386                 total_gb_size_per_controller += 1 << (
 387                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 388                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 389                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 390                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 391                         26);                    /* minus 26 (count of 64M) */
 392         }
 393         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 394                 total_gb_size_per_controller *= 3;
 395         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 396                 total_gb_size_per_controller <<= 1;
 397         /*
 398          * total memory / bus width = transactions needed
 399          * transactions needed / data rate = seconds
 400          * to add plenty of buffer, double the time
 401          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 402          * Let's wait for 800ms
 403          */
 404         bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
 405                         >> SDRAM_CFG_DBW_SHIFT);
 406         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 407                 (get_ddr_freq(0) >> 20)) << 1;
 408 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 409         timeout_save = timeout;
 410 #endif
 411         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 412         debug("total %d GB\n", total_gb_size_per_controller);
 413         debug("Need to wait up to %d * 10ms\n", timeout);
 414
 415         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 416         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 417                 (timeout >= 0)) {
 418                 udelay(10000);          /* throttle polling rate */
 419                 timeout--;
 420         }
 421
 422         if (timeout <= 0)
 423                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 424
 425 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 426         /* continue this workaround */
 427
 428         /* 4. Clear DEBUG3[21] */
 429         clrbits_be32(&ddr->debug[2], 0x400);
 430         debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
 431
 432         /* DDR134 workaround starts */
 433         /* A: Clear sdram_cfg_2[odt_cfg] */
 434         clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
 435         debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
 436                 in_be32(&ddr->sdram_cfg_2));
 437
 438         /* B: Set DEBUG1[15] */
 439         setbits_be32(&ddr->debug[0], 0x10000);
 440         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 441
 442         /* C: Set timing_cfg_2[cpo] to 0b11111 */
 443         setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
 444         debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
 445                 in_be32(&ddr->timing_cfg_2));
 446
 447         /* D: Set D6 to 0x9f9f9f9f */
 448         out_be32(&ddr->debug[5], 0x9f9f9f9f);
 449         debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
 450
 451         /* E: Set D7 to 0x9f9f9f9f */
 452         out_be32(&ddr->debug[6], 0x9f9f9f9f);
 453         debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
 454
 455         /* F: Set D2[20] */
 456         setbits_be32(&ddr->debug[1], 0x800);
 457         debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
 458
 459         /* G: Poll on D2[20] until cleared */
 460         while (in_be32(&ddr->debug[1]) & 0x800)
 461                 udelay(10000);          /* throttle polling rate */
 462
 463         /* H: Clear D1[15] */
 464         clrbits_be32(&ddr->debug[0], 0x10000);
 465         debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
 466
 467         /* I: Set sdram_cfg_2[odt_cfg] */
 468         setbits_be32(&ddr->sdram_cfg_2,
 469                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
 470         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 471
 472         /* Continuing with the DDR111 workaround */
 473         /* 5. Set D2[21] */
 474         setbits_be32(&ddr->debug[1], 0x400);
 475         debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
 476
 477         /* 6. Poll D2[21] until its cleared */
 478         while (in_be32(&ddr->debug[1]) & 0x400)
 479                 udelay(10000);          /* throttle polling rate */
 480
 481         /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
 482         debug("Wait for %d * 10ms\n", timeout_save);
 483         udelay(timeout_save * 10000);
 484
 485         /* 8. Set sdram_cfg_2[dinit] if options requires */
 486         setbits_be32(&ddr->sdram_cfg_2,
 487                 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
 488         debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 489
 490         /* 9. Poll until dinit is cleared */
 491         timeout = timeout_save;
 492         debug("Need to wait up to %d * 10ms\n", timeout);
 493         while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 494                 (timeout >= 0)) {
 495                 udelay(10000);          /* throttle polling rate */
 496                 timeout--;
 497         }
 498
 499         if (timeout <= 0)
 500                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 501
 502         /* 10. Clear EEBACR[3] */
 503         clrbits_be32(&ecm->eebacr, 10000000);
 504         debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
 505
 506         if (csn != -1) {
 507                 csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;
 508                 *csn_bnds_t = csn_bnds_backup;
 509                 debug("Change cs%d_bnds back to 0x%08x\n",
 510                         csn, regs->cs[csn].bnds);
 511                 setbits_be32(&ddr->sdram_cfg, 0x2);     /* MEM_HALT */
 512                 switch (csn) {
 513                 case 0:
 514                         out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
 515                         break;
 516                 case 1:
 517                         out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
 518                         break;
 519                 case 2:
 520                         out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
 521                         break;
 522                 case 3:
 523                         out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
 524                         break;
 525                 }
 526                 clrbits_be32(&ddr->sdram_cfg, 0x2);
 527         }
 528 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 529 }