1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
9 #include <fsl_ddr_sdram.h>
10 #include <asm/processor.h>
11 #include <linux/delay.h>
13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
18 * regs has the to-be-set values for DDR controller registers
19 * ctrl_num is the DDR controller number
20 * step: 0 goes through the initialization in one pass
21 * 1 sets registers and returns before enabling controller
22 * 2 resumes from step 1 and continues to initialize
23 * Dividing the initialization to two steps to deassert DDR reset signal
24 * to comply with JEDEC specs for RDIMMs.
26 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
27 unsigned int ctrl_num, int step)
29 unsigned int i, bus_width;
30 struct ccsr_ddr __iomem *ddr;
32 u32 total_gb_size_per_controller;
34 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
36 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
37 unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
40 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
46 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
48 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
50 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
53 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
55 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
58 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
60 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
64 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
72 out_be32(&ddr->eor, regs->ddr_eor);
73 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
74 debug("Workaround for ERRATUM_DDR111_DDR134\n");
75 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
76 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;
77 cs_ea = regs->cs[i].bnds & 0xfff;
78 if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) {
80 csn_bnds_backup = regs->cs[i].bnds;
81 csn_bnds_t = (unsigned int *) ®s->cs[i].bnds;
83 *csn_bnds_t = regs->cs[i].bnds + 0x01000000;
85 *csn_bnds_t = regs->cs[i].bnds + 0x01000100;
86 debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
87 "change it to 0x%x\n",
88 csn, csn_bnds_backup, regs->cs[i].bnds);
93 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
95 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
96 out_be32(&ddr->cs0_config, regs->cs[i].config);
97 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
100 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
101 out_be32(&ddr->cs1_config, regs->cs[i].config);
102 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
105 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
106 out_be32(&ddr->cs2_config, regs->cs[i].config);
107 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
110 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
111 out_be32(&ddr->cs3_config, regs->cs[i].config);
112 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
116 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
117 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
118 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
119 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
120 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
121 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
122 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
123 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
124 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
125 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
126 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
127 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
128 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
129 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
130 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
131 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
132 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
133 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
134 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
135 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
136 #ifndef CONFIG_SYS_FSL_DDR_EMU
138 * Skip these two registers if running on emulator
139 * because emulator doesn't have skew between bytes.
142 if (regs->ddr_wrlvl_cntl_2)
143 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
144 if (regs->ddr_wrlvl_cntl_3)
145 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
148 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
149 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
150 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
151 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
152 #ifdef CONFIG_DEEP_SLEEP
153 if (is_warm_boot()) {
154 out_be32(&ddr->sdram_cfg_2,
155 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
156 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
157 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
159 /* DRAM VRef will not be trained */
160 out_be32(&ddr->ddr_cdr2,
161 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
165 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
166 out_be32(&ddr->init_addr, regs->ddr_init_addr);
167 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
168 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
170 out_be32(&ddr->err_disable, regs->err_disable);
171 out_be32(&ddr->err_int_en, regs->err_int_en);
172 for (i = 0; i < 32; i++) {
173 if (regs->debug[i]) {
174 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]);
175 out_be32(&ddr->debug[i], regs->debug[i]);
179 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
180 out_be32(&ddr->debug[12], 0x00000015);
181 out_be32(&ddr->debug[21], 0x24000000);
182 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
185 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
186 * deasserted. Clocks start when any chip select is enabled and clock
187 * control register is set. Because all DDR components are connected to
188 * one reset signal, this needs to be done in two steps. Step 1 is to
189 * get the clocks started. Step 2 resumes after reset signal is
198 /* Set, but do not enable the memory */
199 temp_sdram_cfg = regs->ddr_sdram_cfg;
200 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
201 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
202 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
203 debug("Workaround for ERRATUM_DDR_A003\n");
204 if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
205 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
206 out_be32(&ddr->debug[2], 0x00000400);
207 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
208 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
209 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
210 out_be32(&ddr->mtcr, 0);
211 save1 = in_be32(&ddr->debug[12]);
212 save2 = in_be32(&ddr->debug[21]);
213 out_be32(&ddr->debug[12], 0x00000015);
214 out_be32(&ddr->debug[21], 0x24000000);
215 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
216 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
218 asm volatile("sync;isync");
219 while (!(in_be32(&ddr->debug[1]) & 0x2))
222 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
224 out_be32(&ddr->sdram_md_cntl,
226 MD_CNTL_CS_SEL_CS0_CS1 |
229 MD_CNTL_MD_VALUE(0x02));
230 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
231 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
233 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
235 out_be32(&ddr->sdram_md_cntl,
237 MD_CNTL_CS_SEL_CS2_CS3 |
240 MD_CNTL_MD_VALUE(0x02));
244 out_be32(&ddr->sdram_md_cntl,
246 MD_CNTL_CS_SEL_CS0_CS1 |
249 MD_CNTL_MD_VALUE(0x0a));
250 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
251 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
253 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
255 out_be32(&ddr->sdram_md_cntl,
257 MD_CNTL_CS_SEL_CS2_CS3 |
260 MD_CNTL_MD_VALUE(0x0a));
264 out_be32(&ddr->sdram_md_cntl,
266 MD_CNTL_CS_SEL_CS0_CS1 |
269 MD_CNTL_MD_VALUE(0x12));
270 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
271 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
273 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
275 out_be32(&ddr->sdram_md_cntl,
277 MD_CNTL_CS_SEL_CS2_CS3 |
280 MD_CNTL_MD_VALUE(0x12));
284 out_be32(&ddr->sdram_md_cntl,
286 MD_CNTL_CS_SEL_CS0_CS1 |
289 MD_CNTL_MD_VALUE(0x1a));
290 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
291 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
293 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
295 out_be32(&ddr->sdram_md_cntl,
297 MD_CNTL_CS_SEL_CS2_CS3 |
300 MD_CNTL_MD_VALUE(0x1a));
304 out_be32(&ddr->sdram_md_cntl,
306 MD_CNTL_CS_SEL_CS0_CS1 |
309 MD_CNTL_MD_VALUE(0x02));
310 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
311 if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))
313 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)
315 out_be32(&ddr->sdram_md_cntl,
317 MD_CNTL_CS_SEL_CS2_CS3 |
320 MD_CNTL_MD_VALUE(0x02));
322 printf("Unsupported RC10\n");
326 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
329 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
330 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
331 out_be32(&ddr->debug[2], 0x0);
332 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
333 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
334 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
335 out_be32(&ddr->debug[12], save1);
336 out_be32(&ddr->debug[21], save2);
337 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
342 * For 8572 DDR1 erratum - DDR controller may enter illegal state
343 * when operatiing in 32-bit bus mode with 4-beat bursts,
344 * This erratum does not affect DDR3 mode, only for DDR2 mode.
346 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
347 debug("Workaround for ERRATUM_DDR_115\n");
348 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
349 && in_be32(&ddr->sdram_cfg) & 0x80000) {
350 /* set DEBUG_1[31] */
351 setbits_be32(&ddr->debug[0], 1);
354 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
355 debug("Workaround for ERRATUM_DDR111_DDR134\n");
357 * This is the combined workaround for DDR111 and DDR134
358 * following the published errata for MPC8572
361 /* 1. Set EEBACR[3] */
362 setbits_be32(&ecm->eebacr, 0x10000000);
363 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
365 /* 2. Set DINIT in SDRAM_CFG_2*/
366 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
367 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
368 in_be32(&ddr->sdram_cfg_2));
370 /* 3. Set DEBUG_3[21] */
371 setbits_be32(&ddr->debug[2], 0x400);
372 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
374 #endif /* part 1 of the workaound */
377 * 500 painful micro-seconds must elapse between
378 * the DDR clock setup and the DDR config enable.
379 * DDR2 need 200 us, and DDR3 need 500 us from spec,
380 * we choose the max, that is 500 us for all of case.
383 asm volatile("sync;isync");
385 #ifdef CONFIG_DEEP_SLEEP
386 if (is_warm_boot()) {
387 /* enter self-refresh */
388 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
389 /* do board specific memory setup */
390 board_mem_sleep_setup();
391 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
394 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
396 /* Let the controller go */
397 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
398 asm volatile("sync;isync");
400 total_gb_size_per_controller = 0;
401 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
402 if (!(regs->cs[i].config & 0x80000000))
404 total_gb_size_per_controller += 1 << (
405 ((regs->cs[i].config >> 14) & 0x3) + 2 +
406 ((regs->cs[i].config >> 8) & 0x7) + 12 +
407 ((regs->cs[i].config >> 0) & 0x7) + 8 +
408 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
409 26); /* minus 26 (count of 64M) */
411 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
412 total_gb_size_per_controller *= 3;
413 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
414 total_gb_size_per_controller <<= 1;
416 * total memory / bus width = transactions needed
417 * transactions needed / data rate = seconds
418 * to add plenty of buffer, double the time
419 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
420 * Let's wait for 800ms
422 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
423 >> SDRAM_CFG_DBW_SHIFT);
424 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
425 (get_ddr_freq(ctrl_num) >> 20)) << 1;
426 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
427 timeout_save = timeout;
429 total_gb_size_per_controller >>= 4; /* shift down to gb size */
430 debug("total %d GB\n", total_gb_size_per_controller);
431 debug("Need to wait up to %d * 10ms\n", timeout);
433 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
434 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
436 udelay(10000); /* throttle polling rate */
441 printf("Waiting for D_INIT timeout. Memory may not work.\n");
443 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
444 /* continue this workaround */
446 /* 4. Clear DEBUG3[21] */
447 clrbits_be32(&ddr->debug[2], 0x400);
448 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
450 /* DDR134 workaround starts */
451 /* A: Clear sdram_cfg_2[odt_cfg] */
452 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
453 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
454 in_be32(&ddr->sdram_cfg_2));
456 /* B: Set DEBUG1[15] */
457 setbits_be32(&ddr->debug[0], 0x10000);
458 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
460 /* C: Set timing_cfg_2[cpo] to 0b11111 */
461 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
462 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
463 in_be32(&ddr->timing_cfg_2));
465 /* D: Set D6 to 0x9f9f9f9f */
466 out_be32(&ddr->debug[5], 0x9f9f9f9f);
467 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
469 /* E: Set D7 to 0x9f9f9f9f */
470 out_be32(&ddr->debug[6], 0x9f9f9f9f);
471 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
474 setbits_be32(&ddr->debug[1], 0x800);
475 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
477 /* G: Poll on D2[20] until cleared */
478 while (in_be32(&ddr->debug[1]) & 0x800)
479 udelay(10000); /* throttle polling rate */
481 /* H: Clear D1[15] */
482 clrbits_be32(&ddr->debug[0], 0x10000);
483 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
485 /* I: Set sdram_cfg_2[odt_cfg] */
486 setbits_be32(&ddr->sdram_cfg_2,
487 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
488 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
490 /* Continuing with the DDR111 workaround */
492 setbits_be32(&ddr->debug[1], 0x400);
493 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
495 /* 6. Poll D2[21] until its cleared */
496 while (in_be32(&ddr->debug[1]) & 0x400)
497 udelay(10000); /* throttle polling rate */
499 /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
500 debug("Wait for %d * 10ms\n", timeout_save);
501 udelay(timeout_save * 10000);
503 /* 8. Set sdram_cfg_2[dinit] if options requires */
504 setbits_be32(&ddr->sdram_cfg_2,
505 regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
506 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
508 /* 9. Poll until dinit is cleared */
509 timeout = timeout_save;
510 debug("Need to wait up to %d * 10ms\n", timeout);
511 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
513 udelay(10000); /* throttle polling rate */
518 printf("Waiting for D_INIT timeout. Memory may not work.\n");
520 /* 10. Clear EEBACR[3] */
521 clrbits_be32(&ecm->eebacr, 10000000);
522 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
525 csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds;
526 *csn_bnds_t = csn_bnds_backup;
527 debug("Change cs%d_bnds back to 0x%08x\n",
528 csn, regs->cs[csn].bnds);
529 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */
532 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);
535 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);
537 #if CONFIG_CHIP_SELECTS_PER_CTRL > 2
539 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);
542 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);
546 clrbits_be32(&ddr->sdram_cfg, 0x2);
548 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
549 #ifdef CONFIG_DEEP_SLEEP
551 /* exit self-refresh */
552 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);