drivers/ddr/fsl/main.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <fsl_ddr_sdram.h>
  18 #include <fsl_ddr.h>
  19
  20 /*
  21  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  22  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  23  * all Power SoCs. But it could be different for ARM SoCs. For example,
  24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  25  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  26  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  27  */
  28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  29 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  30 #endif
  31
  32 #ifdef CONFIG_PPC
  33 #include <asm/fsl_law.h>
  34
  35 void fsl_ddr_set_lawbar(
  36                 const common_timing_params_t *memctl_common_params,
  37                 unsigned int memctl_interleaved,
  38                 unsigned int ctrl_num);
  39 #endif
  40
  41 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  42 #if defined(SPD_EEPROM_ADDRESS) || \
  43     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  44     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  45 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  47         [0][0] = SPD_EEPROM_ADDRESS,
  48 };
  49 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  50 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  52         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  53 };
  54 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  55 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  56         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  57         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  58 };
  59 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  60 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  61         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  62         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  63         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  64         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  65 };
  66 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  67 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  68         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  69         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  70         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  71 };
  72 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  73 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  74         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  75         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  76         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  77         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  78         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  79         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  80 };
  81
  82 #endif
  83
  84 #define SPD_SPA0_ADDRESS        0x36
  85 #define SPD_SPA1_ADDRESS        0x37
  86
  87 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  88 {
  89         int ret;
  90 #ifdef CONFIG_SYS_FSL_DDR4
  91         uint8_t dummy = 0;
  92 #endif
  93
  94         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  95
  96 #ifdef CONFIG_SYS_FSL_DDR4
  97         /*
  98          * DDR4 SPD has 384 to 512 bytes
  99          * To access the lower 256 bytes, we need to set EE page address to 0
 100          * To access the upper 256 bytes, we need to set EE page address to 1
 101          * See Jedec standar No. 21-C for detail
 102          */
 103         i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 104         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 105         if (!ret) {
 106                 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 107                 ret = i2c_read(i2c_address, 0, 1,
 108                                (uchar *)((ulong)spd + 256),
 109                                min(256,
 110                                    (int)sizeof(generic_spd_eeprom_t) - 256));
 111         }
 112 #else
 113         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 114                                 sizeof(generic_spd_eeprom_t));
 115 #endif
 116
 117         if (ret) {
 118                 if (i2c_address ==
 119 #ifdef SPD_EEPROM_ADDRESS
 120                                 SPD_EEPROM_ADDRESS
 121 #elif defined(SPD_EEPROM_ADDRESS1)
 122                                 SPD_EEPROM_ADDRESS1
 123 #endif
 124                                 ) {
 125                         printf("DDR: failed to read SPD from address %u\n",
 126                                 i2c_address);
 127                 } else {
 128                         debug("DDR: failed to read SPD from address %u\n",
 129                                 i2c_address);
 130                 }
 131                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 132         }
 133 }
 134
 135 __attribute__((weak, alias("__get_spd")))
 136 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 137
 138 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 139                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 140 {
 141         unsigned int i;
 142         unsigned int i2c_address = 0;
 143
 144         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 145                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 146                 return;
 147         }
 148
 149         for (i = 0; i < dimm_slots_per_ctrl; i++) {
 150                 i2c_address = spd_i2c_addr[ctrl_num][i];
 151                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 152         }
 153 }
 154 #else
 155 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 156                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 157 {
 158 }
 159 #endif /* SPD_EEPROM_ADDRESSx */
 160
 161 /*
 162  * ASSUMPTIONS:
 163  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 164  *    - Same memory data bus width on all controllers
 165  *
 166  * NOTES:
 167  *
 168  * The memory controller and associated documentation use confusing
 169  * terminology when referring to the orgranization of DRAM.
 170  *
 171  * Here is a terminology translation table:
 172  *
 173  * memory controller/documention  |industry   |this code  |signals
 174  * -------------------------------|-----------|-----------|-----------------
 175  * physical bank/bank             |rank       |rank       |chip select (CS)
 176  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 177  * page/row                       |row        |page       |row address
 178  * ???                            |column     |column     |column address
 179  *
 180  * The naming confusion is further exacerbated by the descriptions of the
 181  * memory controller interleaving feature, where accesses are interleaved
 182  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 183  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 184  *
 185  * memory controller documentation | number of chip selects
 186  *                                 | per memory controller supported
 187  * --------------------------------|-----------------------------------------
 188  * cache line interleaving         | 1 (CS0 only)
 189  * page interleaving               | 1 (CS0 only)
 190  * bank interleaving               | 1 (CS0 only)
 191  * superbank interleraving         | depends on bank (chip select)
 192  *                                 |   interleraving [rank interleaving]
 193  *                                 |   mode used on every memory controller
 194  *
 195  * Even further confusing is the existence of the interleaving feature
 196  * _WITHIN_ each memory controller.  The feature is referred to in
 197  * documentation as chip select interleaving or bank interleaving,
 198  * although it is configured in the DDR_SDRAM_CFG field.
 199  *
 200  * Name of field                | documentation name    | this code
 201  * -----------------------------|-----------------------|------------------
 202  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 203  *                              |  interleaving
 204  */
 205
 206 const char *step_string_tbl[] = {
 207         "STEP_GET_SPD",
 208         "STEP_COMPUTE_DIMM_PARMS",
 209         "STEP_COMPUTE_COMMON_PARMS",
 210         "STEP_GATHER_OPTS",
 211         "STEP_ASSIGN_ADDRESSES",
 212         "STEP_COMPUTE_REGS",
 213         "STEP_PROGRAM_REGS",
 214         "STEP_ALL"
 215 };
 216
 217 const char * step_to_string(unsigned int step) {
 218
 219         unsigned int s = __ilog2(step);
 220
 221         if ((1 << s) != step)
 222                 return step_string_tbl[7];
 223
 224         if (s >= ARRAY_SIZE(step_string_tbl)) {
 225                 printf("Error for the step in %s\n", __func__);
 226                 s = 0;
 227         }
 228
 229         return step_string_tbl[s];
 230 }
 231
 232 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 233                           unsigned int dbw_cap_adj[])
 234 {
 235         unsigned int i, j;
 236         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 237         unsigned long long rank_density, ctlr_density = 0;
 238         unsigned int first_ctrl = pinfo->first_ctrl;
 239         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 240
 241         /*
 242          * If a reduced data width is requested, but the SPD
 243          * specifies a physically wider device, adjust the
 244          * computed dimm capacities accordingly before
 245          * assigning addresses.
 246          */
 247         for (i = first_ctrl; i <= last_ctrl; i++) {
 248                 unsigned int found = 0;
 249
 250                 switch (pinfo->memctl_opts[i].data_bus_width) {
 251                 case 2:
 252                         /* 16-bit */
 253                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 254                                 unsigned int dw;
 255                                 if (!pinfo->dimm_params[i][j].n_ranks)
 256                                         continue;
 257                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 258                                 if ((dw == 72 || dw == 64)) {
 259                                         dbw_cap_adj[i] = 2;
 260                                         break;
 261                                 } else if ((dw == 40 || dw == 32)) {
 262                                         dbw_cap_adj[i] = 1;
 263                                         break;
 264                                 }
 265                         }
 266                         break;
 267
 268                 case 1:
 269                         /* 32-bit */
 270                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 271                                 unsigned int dw;
 272                                 dw = pinfo->dimm_params[i][j].data_width;
 273                                 if (pinfo->dimm_params[i][j].n_ranks
 274                                     && (dw == 72 || dw == 64)) {
 275                                         /*
 276                                          * FIXME: can't really do it
 277                                          * like this because this just
 278                                          * further reduces the memory
 279                                          */
 280                                         found = 1;
 281                                         break;
 282                                 }
 283                         }
 284                         if (found) {
 285                                 dbw_cap_adj[i] = 1;
 286                         }
 287                         break;
 288
 289                 case 0:
 290                         /* 64-bit */
 291                         break;
 292
 293                 default:
 294                         printf("unexpected data bus width "
 295                                 "specified controller %u\n", i);
 296                         return 1;
 297                 }
 298                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 299         }
 300
 301         current_mem_base = pinfo->mem_base;
 302         total_mem = 0;
 303         if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 304                 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 305                                         dbw_cap_adj[first_ctrl];
 306                 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 307                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 308                 case FSL_DDR_CS0_CS1_CS2_CS3:
 309                         ctlr_density = 4 * rank_density;
 310                         break;
 311                 case FSL_DDR_CS0_CS1:
 312                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 313                         ctlr_density = 2 * rank_density;
 314                         break;
 315                 case FSL_DDR_CS2_CS3:
 316                 default:
 317                         ctlr_density = rank_density;
 318                         break;
 319                 }
 320                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 321                         rank_density, ctlr_density);
 322                 for (i = first_ctrl; i <= last_ctrl; i++) {
 323                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 324                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 325                                 case FSL_DDR_256B_INTERLEAVING:
 326                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 327                                 case FSL_DDR_PAGE_INTERLEAVING:
 328                                 case FSL_DDR_BANK_INTERLEAVING:
 329                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 330                                         total_ctlr_mem = 2 * ctlr_density;
 331                                         break;
 332                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 333                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 334                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 335                                         total_ctlr_mem = 3 * ctlr_density;
 336                                         break;
 337                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 338                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 339                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 340                                         total_ctlr_mem = 4 * ctlr_density;
 341                                         break;
 342                                 default:
 343                                         panic("Unknown interleaving mode");
 344                                 }
 345                                 pinfo->common_timing_params[i].base_address =
 346                                                         current_mem_base;
 347                                 pinfo->common_timing_params[i].total_mem =
 348                                                         total_ctlr_mem;
 349                                 total_mem = current_mem_base + total_ctlr_mem;
 350                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 351                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 352                         } else {
 353                                 /* when 3rd controller not interleaved */
 354                                 current_mem_base = total_mem;
 355                                 total_ctlr_mem = 0;
 356                                 pinfo->common_timing_params[i].base_address =
 357                                                         current_mem_base;
 358                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 359                                         unsigned long long cap =
 360                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 361                                         pinfo->dimm_params[i][j].base_address =
 362                                                 current_mem_base;
 363                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 364                                         current_mem_base += cap;
 365                                         total_ctlr_mem += cap;
 366                                 }
 367                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 368                                 pinfo->common_timing_params[i].total_mem =
 369                                                         total_ctlr_mem;
 370                                 total_mem += total_ctlr_mem;
 371                         }
 372                 }
 373         } else {
 374                 /*
 375                  * Simple linear assignment if memory
 376                  * controllers are not interleaved.
 377                  */
 378                 for (i = first_ctrl; i <= last_ctrl; i++) {
 379                         total_ctlr_mem = 0;
 380                         pinfo->common_timing_params[i].base_address =
 381                                                 current_mem_base;
 382                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 383                                 /* Compute DIMM base addresses. */
 384                                 unsigned long long cap =
 385                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 386                                 pinfo->dimm_params[i][j].base_address =
 387                                         current_mem_base;
 388                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 389                                 current_mem_base += cap;
 390                                 total_ctlr_mem += cap;
 391                         }
 392                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 393                         pinfo->common_timing_params[i].total_mem =
 394                                                         total_ctlr_mem;
 395                         total_mem += total_ctlr_mem;
 396                 }
 397         }
 398         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 399
 400         return total_mem;
 401 }
 402
 403 /* Use weak function to allow board file to override the address assignment */
 404 __attribute__((weak, alias("__step_assign_addresses")))
 405 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 406                           unsigned int dbw_cap_adj[]);
 407
 408 unsigned long long
 409 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 410                                        unsigned int size_only)
 411 {
 412         unsigned int i, j;
 413         unsigned long long total_mem = 0;
 414         int assert_reset = 0;
 415         unsigned int first_ctrl =  pinfo->first_ctrl;
 416         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 417         __maybe_unused int retval;
 418         __maybe_unused bool goodspd = false;
 419         __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 420
 421         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 422         common_timing_params_t *timing_params = pinfo->common_timing_params;
 423         if (pinfo->board_need_mem_reset)
 424                 assert_reset = pinfo->board_need_mem_reset();
 425
 426         /* data bus width capacity adjust shift amount */
 427         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 428
 429         for (i = first_ctrl; i <= last_ctrl; i++)
 430                 dbw_capacity_adjust[i] = 0;
 431
 432         debug("starting at step %u (%s)\n",
 433               start_step, step_to_string(start_step));
 434
 435         switch (start_step) {
 436         case STEP_GET_SPD:
 437 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 438                 /* STEP 1:  Gather all DIMM SPD data */
 439                 for (i = first_ctrl; i <= last_ctrl; i++) {
 440                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 441                                         dimm_slots_per_ctrl);
 442                 }
 443
 444         case STEP_COMPUTE_DIMM_PARMS:
 445                 /* STEP 2:  Compute DIMM parameters from SPD data */
 446
 447                 for (i = first_ctrl; i <= last_ctrl; i++) {
 448                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 449                                 generic_spd_eeprom_t *spd =
 450                                         &(pinfo->spd_installed_dimms[i][j]);
 451                                 dimm_params_t *pdimm =
 452                                         &(pinfo->dimm_params[i][j]);
 453                                 retval = compute_dimm_parameters(
 454                                                         i, spd, pdimm, j);
 455 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 456                                 if (!i && !j && retval) {
 457                                         printf("SPD error on controller %d! "
 458                                         "Trying fallback to raw timing "
 459                                         "calculation\n", i);
 460                                         retval = fsl_ddr_get_dimm_params(pdimm,
 461                                                                          i, j);
 462                                 }
 463 #else
 464                                 if (retval == 2) {
 465                                         printf("Error: compute_dimm_parameters"
 466                                         " non-zero returned FATAL value "
 467                                         "for memctl=%u dimm=%u\n", i, j);
 468                                         return 0;
 469                                 }
 470 #endif
 471                                 if (retval) {
 472                                         debug("Warning: compute_dimm_parameters"
 473                                         " non-zero return value for memctl=%u "
 474                                         "dimm=%u\n", i, j);
 475                                 } else {
 476                                         goodspd = true;
 477                                 }
 478                         }
 479                 }
 480                 if (!goodspd) {
 481                         /*
 482                          * No valid SPD found
 483                          * Throw an error if this is for main memory, i.e.
 484                          * first_ctrl == 0. Otherwise, siliently return 0
 485                          * as the memory size.
 486                          */
 487                         if (first_ctrl == 0)
 488                                 printf("Error: No valid SPD detected.\n");
 489
 490                         return 0;
 491                 }
 492 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 493         case STEP_COMPUTE_DIMM_PARMS:
 494                 for (i = first_ctrl; i <= last_ctrl; i++) {
 495                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 496                                 dimm_params_t *pdimm =
 497                                         &(pinfo->dimm_params[i][j]);
 498                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 499                         }
 500                 }
 501                 debug("Filling dimm parameters from board specific file\n");
 502 #endif
 503         case STEP_COMPUTE_COMMON_PARMS:
 504                 /*
 505                  * STEP 3: Compute a common set of timing parameters
 506                  * suitable for all of the DIMMs on each memory controller
 507                  */
 508                 for (i = first_ctrl; i <= last_ctrl; i++) {
 509                         debug("Computing lowest common DIMM"
 510                                 " parameters for memctl=%u\n", i);
 511                         compute_lowest_common_dimm_parameters
 512                                 (i,
 513                                  pinfo->dimm_params[i],
 514                                  &timing_params[i],
 515                                  CONFIG_DIMM_SLOTS_PER_CTLR);
 516                 }
 517
 518         case STEP_GATHER_OPTS:
 519                 /* STEP 4:  Gather configuration requirements from user */
 520                 for (i = first_ctrl; i <= last_ctrl; i++) {
 521                         debug("Reloading memory controller "
 522                                 "configuration options for memctl=%u\n", i);
 523                         /*
 524                          * This "reloads" the memory controller options
 525                          * to defaults.  If the user "edits" an option,
 526                          * next_step points to the step after this,
 527                          * which is currently STEP_ASSIGN_ADDRESSES.
 528                          */
 529                         populate_memctl_options(
 530                                         timing_params[i].all_dimms_registered,
 531                                         &pinfo->memctl_opts[i],
 532                                         pinfo->dimm_params[i], i);
 533                         /*
 534                          * For RDIMMs, JEDEC spec requires clocks to be stable
 535                          * before reset signal is deasserted. For the boards
 536                          * using fixed parameters, this function should be
 537                          * be called from board init file.
 538                          */
 539                         if (timing_params[i].all_dimms_registered)
 540                                 assert_reset = 1;
 541                 }
 542                 if (assert_reset && !size_only) {
 543                         if (pinfo->board_mem_reset) {
 544                                 debug("Asserting mem reset\n");
 545                                 pinfo->board_mem_reset();
 546                         } else {
 547                                 debug("Asserting mem reset missing\n");
 548                         }
 549                 }
 550
 551         case STEP_ASSIGN_ADDRESSES:
 552                 /* STEP 5:  Assign addresses to chip selects */
 553                 check_interleaving_options(pinfo);
 554                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 555                 debug("Total mem %llu assigned\n", total_mem);
 556
 557         case STEP_COMPUTE_REGS:
 558                 /* STEP 6:  compute controller register values */
 559                 debug("FSL Memory ctrl register computation\n");
 560                 for (i = first_ctrl; i <= last_ctrl; i++) {
 561                         if (timing_params[i].ndimms_present == 0) {
 562                                 memset(&ddr_reg[i], 0,
 563                                         sizeof(fsl_ddr_cfg_regs_t));
 564                                 continue;
 565                         }
 566
 567                         compute_fsl_memctl_config_regs
 568                                 (i,
 569                                  &pinfo->memctl_opts[i],
 570                                  &ddr_reg[i], &timing_params[i],
 571                                  pinfo->dimm_params[i],
 572                                  dbw_capacity_adjust[i],
 573                                  size_only);
 574                 }
 575
 576         default:
 577                 break;
 578         }
 579
 580         {
 581                 /*
 582                  * Compute the amount of memory available just by
 583                  * looking for the highest valid CSn_BNDS value.
 584                  * This allows us to also experiment with using
 585                  * only CS0 when using dual-rank DIMMs.
 586                  */
 587                 unsigned int max_end = 0;
 588
 589                 for (i = first_ctrl; i <= last_ctrl; i++) {
 590                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 591                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 592                                 if (reg->cs[j].config & 0x80000000) {
 593                                         unsigned int end;
 594                                         /*
 595                                          * 0xfffffff is a special value we put
 596                                          * for unused bnds
 597                                          */
 598                                         if (reg->cs[j].bnds == 0xffffffff)
 599                                                 continue;
 600                                         end = reg->cs[j].bnds & 0xffff;
 601                                         if (end > max_end) {
 602                                                 max_end = end;
 603                                         }
 604                                 }
 605                         }
 606                 }
 607
 608                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 609                             0xFFFFFFULL) - pinfo->mem_base;
 610         }
 611
 612         return total_mem;
 613 }
 614
 615 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 616 {
 617         unsigned int i, first_ctrl, last_ctrl;
 618 #ifdef CONFIG_PPC
 619         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 620 #endif
 621         unsigned long long total_memory;
 622         int deassert_reset = 0;
 623
 624         first_ctrl = pinfo->first_ctrl;
 625         last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 626
 627         /* Compute it once normally. */
 628 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 629         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 630                 total_memory = fsl_ddr_interactive(pinfo, 0);
 631         } else if (fsl_ddr_interactive_env_var_exists()) {
 632                 total_memory = fsl_ddr_interactive(pinfo, 1);
 633         } else
 634 #endif
 635                 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 636
 637         /* setup 3-way interleaving before enabling DDRC */
 638         switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 639         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 640         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 641         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 642                 fsl_ddr_set_intl3r(
 643                         pinfo->memctl_opts[first_ctrl].
 644                         memctl_interleaving_mode);
 645                 break;
 646         default:
 647                 break;
 648         }
 649
 650         /*
 651          * Program configuration registers.
 652          * JEDEC specs requires clocks to be stable before deasserting reset
 653          * for RDIMMs. Clocks start after chip select is enabled and clock
 654          * control register is set. During step 1, all controllers have their
 655          * registers set but not enabled. Step 2 proceeds after deasserting
 656          * reset through board FPGA or GPIO.
 657          * For non-registered DIMMs, initialization can go through but it is
 658          * also OK to follow the same flow.
 659          */
 660         if (pinfo->board_need_mem_reset)
 661                 deassert_reset = pinfo->board_need_mem_reset();
 662         for (i = first_ctrl; i <= last_ctrl; i++) {
 663                 if (pinfo->common_timing_params[i].all_dimms_registered)
 664                         deassert_reset = 1;
 665         }
 666         for (i = first_ctrl; i <= last_ctrl; i++) {
 667                 debug("Programming controller %u\n", i);
 668                 if (pinfo->common_timing_params[i].ndimms_present == 0) {
 669                         debug("No dimms present on controller %u; "
 670                                         "skipping programming\n", i);
 671                         continue;
 672                 }
 673                 /*
 674                  * The following call with step = 1 returns before enabling
 675                  * the controller. It has to finish with step = 2 later.
 676                  */
 677                 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 678                                         deassert_reset ? 1 : 0);
 679         }
 680         if (deassert_reset) {
 681                 /* Use board FPGA or GPIO to deassert reset signal */
 682                 if (pinfo->board_mem_de_reset) {
 683                         debug("Deasserting mem reset\n");
 684                         pinfo->board_mem_de_reset();
 685                 } else {
 686                         debug("Deasserting mem reset missing\n");
 687                 }
 688                 for (i = first_ctrl; i <= last_ctrl; i++) {
 689                         /* Call with step = 2 to continue initialization */
 690                         fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 691                                                 i, 2);
 692                 }
 693         }
 694
 695 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 696         fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 697 #endif
 698
 699 #ifdef CONFIG_PPC
 700         /* program LAWs */
 701         for (i = first_ctrl; i <= last_ctrl; i++) {
 702                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 703                         switch (pinfo->memctl_opts[i].
 704                                 memctl_interleaving_mode) {
 705                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 706                         case FSL_DDR_PAGE_INTERLEAVING:
 707                         case FSL_DDR_BANK_INTERLEAVING:
 708                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 709                                 if (i % 2)
 710                                         break;
 711                                 if (i == 0) {
 712                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 713                                         fsl_ddr_set_lawbar(
 714                                                 &pinfo->common_timing_params[i],
 715                                                 law_memctl, i);
 716                                 }
 717 #if CONFIG_NUM_DDR_CONTROLLERS > 3
 718                                 else if (i == 2) {
 719                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 720                                         fsl_ddr_set_lawbar(
 721                                                 &pinfo->common_timing_params[i],
 722                                                 law_memctl, i);
 723                                 }
 724 #endif
 725                                 break;
 726                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 727                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 728                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 729                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 730                                 if (i == 0) {
 731                                         fsl_ddr_set_lawbar(
 732                                                 &pinfo->common_timing_params[i],
 733                                                 law_memctl, i);
 734                                 }
 735                                 break;
 736                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 737                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 738                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 739                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 740                                 if (i == 0)
 741                                         fsl_ddr_set_lawbar(
 742                                                 &pinfo->common_timing_params[i],
 743                                                 law_memctl, i);
 744                                 /* place holder for future 4-way interleaving */
 745                                 break;
 746                         default:
 747                                 break;
 748                         }
 749                 } else {
 750                         switch (i) {
 751                         case 0:
 752                                 law_memctl = LAW_TRGT_IF_DDR_1;
 753                                 break;
 754                         case 1:
 755                                 law_memctl = LAW_TRGT_IF_DDR_2;
 756                                 break;
 757                         case 2:
 758                                 law_memctl = LAW_TRGT_IF_DDR_3;
 759                                 break;
 760                         case 3:
 761                                 law_memctl = LAW_TRGT_IF_DDR_4;
 762                                 break;
 763                         default:
 764                                 break;
 765                         }
 766                         fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 767                                            law_memctl, i);
 768                 }
 769         }
 770 #endif
 771
 772         debug("total_memory by %s = %llu\n", __func__, total_memory);
 773
 774 #if !defined(CONFIG_PHYS_64BIT)
 775         /* Check for 4G or more.  Bad. */
 776         if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 777                 puts("Detected ");
 778                 print_size(total_memory, " of memory\n");
 779                 printf("       This U-Boot only supports < 4G of DDR\n");
 780                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 781                 printf("       "); /* re-align to match init_func_ram print */
 782                 total_memory = CONFIG_MAX_MEM_MAPPED;
 783         }
 784 #endif
 785
 786         return total_memory;
 787 }
 788
 789 /*
 790  * fsl_ddr_sdram(void) -- this is the main function to be
 791  * called by initdram() in the board file.
 792  *
 793  * It returns amount of memory configured in bytes.
 794  */
 795 phys_size_t fsl_ddr_sdram(void)
 796 {
 797         fsl_ddr_info_t info;
 798
 799         /* Reset info structure. */
 800         memset(&info, 0, sizeof(fsl_ddr_info_t));
 801         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 802         info.first_ctrl = 0;
 803         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 804         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 805         info.board_need_mem_reset = board_need_mem_reset;
 806         info.board_mem_reset = board_assert_mem_reset;
 807         info.board_mem_de_reset = board_deassert_mem_reset;
 808
 809         return __fsl_ddr_sdram(&info);
 810 }
 811
 812 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 813 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 814                                 unsigned int first_ctrl,
 815                                 unsigned int num_ctrls,
 816                                 unsigned int dimm_slots_per_ctrl,
 817                                 int (*board_need_reset)(void),
 818                                 void (*board_reset)(void),
 819                                 void (*board_de_reset)(void))
 820 {
 821         fsl_ddr_info_t info;
 822
 823         /* Reset info structure. */
 824         memset(&info, 0, sizeof(fsl_ddr_info_t));
 825         info.mem_base = base;
 826         info.first_ctrl = first_ctrl;
 827         info.num_ctrls = num_ctrls;
 828         info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 829         info.board_need_mem_reset = board_need_reset;
 830         info.board_mem_reset = board_reset;
 831         info.board_mem_de_reset = board_de_reset;
 832
 833         return __fsl_ddr_sdram(&info);
 834 }
 835 #endif
 836
 837 /*
 838  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 839  * size of the total memory without setting ddr control registers.
 840  */
 841 phys_size_t
 842 fsl_ddr_sdram_size(void)
 843 {
 844         fsl_ddr_info_t  info;
 845         unsigned long long total_memory = 0;
 846
 847         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 848         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 849         info.first_ctrl = 0;
 850         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 851         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 852         info.board_need_mem_reset = NULL;
 853
 854         /* Compute it once normally. */
 855         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 856
 857         return total_memory;
 858 }