drivers/ddr/fsl/main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   8  * Based on code from spd_sdram.c
   9  * Author: James Yang [at freescale.com]
  10  */
  11
  12 #include <common.h>
  13 #include <dm.h>
  14 #include <i2c.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <fsl_ddr.h>
  17 #include <init.h>
  18 #include <log.h>
  19
  20 /*
  21  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  22  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  23  * all Power SoCs. But it could be different for ARM SoCs. For example,
  24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  25  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  26  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  27  */
  28 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  29 #ifdef CONFIG_MPC83xx
  30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
  31 #else
  32 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  33 #endif
  34 #endif
  35
  36 #ifdef CONFIG_PPC
  37 #include <asm/fsl_law.h>
  38
  39 void fsl_ddr_set_lawbar(
  40                 const common_timing_params_t *memctl_common_params,
  41                 unsigned int memctl_interleaved,
  42                 unsigned int ctrl_num);
  43 #endif
  44
  45 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  46 #if defined(SPD_EEPROM_ADDRESS) || \
  47     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  48     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  49 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  50 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  51         [0][0] = SPD_EEPROM_ADDRESS,
  52 };
  53 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  54 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  55         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  56         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  57 };
  58 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  59 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  60         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  61         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  62 };
  63 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  64 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  65         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  66         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  67         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  68         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  69 };
  70 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  71 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  72         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  73         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  74         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  75 };
  76 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  77 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  78         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  79         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  80         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  81         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  82         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  83         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  84 };
  85
  86 #endif
  87
  88 #if defined(CONFIG_DM_I2C)
  89 #define DEV_TYPE struct udevice
  90 #else
  91 /* Local udevice */
  92 struct ludevice {
  93         u8 chip;
  94 };
  95
  96 #define DEV_TYPE struct ludevice
  97
  98 #endif
  99
 100 #define SPD_SPA0_ADDRESS        0x36
 101 #define SPD_SPA1_ADDRESS        0x37
 102
 103 static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
 104                         int alen, uint8_t *buf, int len)
 105 {
 106         int ret;
 107
 108 #ifdef CONFIG_DM_I2C
 109         ret = dm_i2c_read(dev, 0, buf, len);
 110 #else
 111         ret = i2c_read(dev->chip, addr, alen, buf, len);
 112 #endif
 113
 114         return ret;
 115 }
 116
 117 #ifdef CONFIG_SYS_FSL_DDR4
 118 static int ddr_i2c_dummy_write(unsigned int chip_addr)
 119 {
 120         uint8_t buf = 0;
 121
 122 #ifdef CONFIG_DM_I2C
 123         struct udevice *dev;
 124         int ret;
 125
 126         ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
 127                                       1, &dev);
 128         if (ret) {
 129                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 130                        CONFIG_SYS_SPD_BUS_NUM);
 131                 return ret;
 132         }
 133
 134         return dm_i2c_write(dev, 0, &buf, 1);
 135 #else
 136         return i2c_write(chip_addr, 0, 1, &buf, 1);
 137 #endif
 138
 139         return 0;
 140 }
 141 #endif
 142
 143 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
 144 {
 145         int ret;
 146         DEV_TYPE *dev;
 147
 148 #if defined(CONFIG_DM_I2C)
 149         ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
 150                                       1, &dev);
 151         if (ret) {
 152                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 153                        CONFIG_SYS_SPD_BUS_NUM);
 154                 return;
 155         }
 156 #else /* Non DM I2C support - will be removed */
 157         struct ludevice ldev = {
 158                 .chip = i2c_address,
 159         };
 160         dev = &ldev;
 161
 162         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 163 #endif
 164
 165 #ifdef CONFIG_SYS_FSL_DDR4
 166         /*
 167          * DDR4 SPD has 384 to 512 bytes
 168          * To access the lower 256 bytes, we need to set EE page address to 0
 169          * To access the upper 256 bytes, we need to set EE page address to 1
 170          * See Jedec standar No. 21-C for detail
 171          */
 172         ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
 173         ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
 174         if (!ret) {
 175                 ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
 176                 ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
 177                                    min(256,
 178                                        (int)sizeof(generic_spd_eeprom_t)
 179                                        - 256));
 180         }
 181
 182 #else
 183         ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
 184                            sizeof(generic_spd_eeprom_t));
 185 #endif
 186
 187         if (ret) {
 188                 if (i2c_address ==
 189 #ifdef SPD_EEPROM_ADDRESS
 190                                 SPD_EEPROM_ADDRESS
 191 #elif defined(SPD_EEPROM_ADDRESS1)
 192                                 SPD_EEPROM_ADDRESS1
 193 #endif
 194                                 ) {
 195                         printf("DDR: failed to read SPD from address %u\n",
 196                                 i2c_address);
 197                 } else {
 198                         debug("DDR: failed to read SPD from address %u\n",
 199                                 i2c_address);
 200                 }
 201                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 202         }
 203 }
 204
 205 __attribute__((weak, alias("__get_spd")))
 206 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 207
 208 /* This function allows boards to update SPD address */
 209 __weak void update_spd_address(unsigned int ctrl_num,
 210                                unsigned int slot,
 211                                unsigned int *addr)
 212 {
 213 }
 214
 215 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 216                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 217 {
 218         unsigned int i;
 219         unsigned int i2c_address = 0;
 220
 221         if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
 222                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 223                 return;
 224         }
 225
 226         for (i = 0; i < dimm_slots_per_ctrl; i++) {
 227                 i2c_address = spd_i2c_addr[ctrl_num][i];
 228                 update_spd_address(ctrl_num, i, &i2c_address);
 229                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 230         }
 231 }
 232 #else
 233 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 234                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 235 {
 236 }
 237 #endif /* SPD_EEPROM_ADDRESSx */
 238
 239 /*
 240  * ASSUMPTIONS:
 241  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 242  *    - Same memory data bus width on all controllers
 243  *
 244  * NOTES:
 245  *
 246  * The memory controller and associated documentation use confusing
 247  * terminology when referring to the orgranization of DRAM.
 248  *
 249  * Here is a terminology translation table:
 250  *
 251  * memory controller/documention  |industry   |this code  |signals
 252  * -------------------------------|-----------|-----------|-----------------
 253  * physical bank/bank             |rank       |rank       |chip select (CS)
 254  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 255  * page/row                       |row        |page       |row address
 256  * ???                            |column     |column     |column address
 257  *
 258  * The naming confusion is further exacerbated by the descriptions of the
 259  * memory controller interleaving feature, where accesses are interleaved
 260  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 261  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 262  *
 263  * memory controller documentation | number of chip selects
 264  *                                 | per memory controller supported
 265  * --------------------------------|-----------------------------------------
 266  * cache line interleaving         | 1 (CS0 only)
 267  * page interleaving               | 1 (CS0 only)
 268  * bank interleaving               | 1 (CS0 only)
 269  * superbank interleraving         | depends on bank (chip select)
 270  *                                 |   interleraving [rank interleaving]
 271  *                                 |   mode used on every memory controller
 272  *
 273  * Even further confusing is the existence of the interleaving feature
 274  * _WITHIN_ each memory controller.  The feature is referred to in
 275  * documentation as chip select interleaving or bank interleaving,
 276  * although it is configured in the DDR_SDRAM_CFG field.
 277  *
 278  * Name of field                | documentation name    | this code
 279  * -----------------------------|-----------------------|------------------
 280  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 281  *                              |  interleaving
 282  */
 283
 284 const char *step_string_tbl[] = {
 285         "STEP_GET_SPD",
 286         "STEP_COMPUTE_DIMM_PARMS",
 287         "STEP_COMPUTE_COMMON_PARMS",
 288         "STEP_GATHER_OPTS",
 289         "STEP_ASSIGN_ADDRESSES",
 290         "STEP_COMPUTE_REGS",
 291         "STEP_PROGRAM_REGS",
 292         "STEP_ALL"
 293 };
 294
 295 const char * step_to_string(unsigned int step) {
 296
 297         unsigned int s = __ilog2(step);
 298
 299         if ((1 << s) != step)
 300                 return step_string_tbl[7];
 301
 302         if (s >= ARRAY_SIZE(step_string_tbl)) {
 303                 printf("Error for the step in %s\n", __func__);
 304                 s = 0;
 305         }
 306
 307         return step_string_tbl[s];
 308 }
 309
 310 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 311                           unsigned int dbw_cap_adj[])
 312 {
 313         unsigned int i, j;
 314         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 315         unsigned long long rank_density, ctlr_density = 0;
 316         unsigned int first_ctrl = pinfo->first_ctrl;
 317         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 318
 319         /*
 320          * If a reduced data width is requested, but the SPD
 321          * specifies a physically wider device, adjust the
 322          * computed dimm capacities accordingly before
 323          * assigning addresses.
 324          */
 325         for (i = first_ctrl; i <= last_ctrl; i++) {
 326                 unsigned int found = 0;
 327
 328                 switch (pinfo->memctl_opts[i].data_bus_width) {
 329                 case 2:
 330                         /* 16-bit */
 331                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 332                                 unsigned int dw;
 333                                 if (!pinfo->dimm_params[i][j].n_ranks)
 334                                         continue;
 335                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 336                                 if ((dw == 72 || dw == 64)) {
 337                                         dbw_cap_adj[i] = 2;
 338                                         break;
 339                                 } else if ((dw == 40 || dw == 32)) {
 340                                         dbw_cap_adj[i] = 1;
 341                                         break;
 342                                 }
 343                         }
 344                         break;
 345
 346                 case 1:
 347                         /* 32-bit */
 348                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 349                                 unsigned int dw;
 350                                 dw = pinfo->dimm_params[i][j].data_width;
 351                                 if (pinfo->dimm_params[i][j].n_ranks
 352                                     && (dw == 72 || dw == 64)) {
 353                                         /*
 354                                          * FIXME: can't really do it
 355                                          * like this because this just
 356                                          * further reduces the memory
 357                                          */
 358                                         found = 1;
 359                                         break;
 360                                 }
 361                         }
 362                         if (found) {
 363                                 dbw_cap_adj[i] = 1;
 364                         }
 365                         break;
 366
 367                 case 0:
 368                         /* 64-bit */
 369                         break;
 370
 371                 default:
 372                         printf("unexpected data bus width "
 373                                 "specified controller %u\n", i);
 374                         return 1;
 375                 }
 376                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 377         }
 378
 379         current_mem_base = pinfo->mem_base;
 380         total_mem = 0;
 381         if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 382                 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 383                                         dbw_cap_adj[first_ctrl];
 384                 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 385                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 386                 case FSL_DDR_CS0_CS1_CS2_CS3:
 387                         ctlr_density = 4 * rank_density;
 388                         break;
 389                 case FSL_DDR_CS0_CS1:
 390                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 391                         ctlr_density = 2 * rank_density;
 392                         break;
 393                 case FSL_DDR_CS2_CS3:
 394                 default:
 395                         ctlr_density = rank_density;
 396                         break;
 397                 }
 398                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 399                         rank_density, ctlr_density);
 400                 for (i = first_ctrl; i <= last_ctrl; i++) {
 401                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 402                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 403                                 case FSL_DDR_256B_INTERLEAVING:
 404                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 405                                 case FSL_DDR_PAGE_INTERLEAVING:
 406                                 case FSL_DDR_BANK_INTERLEAVING:
 407                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 408                                         total_ctlr_mem = 2 * ctlr_density;
 409                                         break;
 410                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 411                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 412                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 413                                         total_ctlr_mem = 3 * ctlr_density;
 414                                         break;
 415                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 416                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 417                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 418                                         total_ctlr_mem = 4 * ctlr_density;
 419                                         break;
 420                                 default:
 421                                         panic("Unknown interleaving mode");
 422                                 }
 423                                 pinfo->common_timing_params[i].base_address =
 424                                                         current_mem_base;
 425                                 pinfo->common_timing_params[i].total_mem =
 426                                                         total_ctlr_mem;
 427                                 total_mem = current_mem_base + total_ctlr_mem;
 428                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 429                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 430                         } else {
 431                                 /* when 3rd controller not interleaved */
 432                                 current_mem_base = total_mem;
 433                                 total_ctlr_mem = 0;
 434                                 pinfo->common_timing_params[i].base_address =
 435                                                         current_mem_base;
 436                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 437                                         unsigned long long cap =
 438                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 439                                         pinfo->dimm_params[i][j].base_address =
 440                                                 current_mem_base;
 441                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 442                                         current_mem_base += cap;
 443                                         total_ctlr_mem += cap;
 444                                 }
 445                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 446                                 pinfo->common_timing_params[i].total_mem =
 447                                                         total_ctlr_mem;
 448                                 total_mem += total_ctlr_mem;
 449                         }
 450                 }
 451         } else {
 452                 /*
 453                  * Simple linear assignment if memory
 454                  * controllers are not interleaved.
 455                  */
 456                 for (i = first_ctrl; i <= last_ctrl; i++) {
 457                         total_ctlr_mem = 0;
 458                         pinfo->common_timing_params[i].base_address =
 459                                                 current_mem_base;
 460                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 461                                 /* Compute DIMM base addresses. */
 462                                 unsigned long long cap =
 463                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 464                                 pinfo->dimm_params[i][j].base_address =
 465                                         current_mem_base;
 466                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 467                                 current_mem_base += cap;
 468                                 total_ctlr_mem += cap;
 469                         }
 470                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 471                         pinfo->common_timing_params[i].total_mem =
 472                                                         total_ctlr_mem;
 473                         total_mem += total_ctlr_mem;
 474                 }
 475         }
 476         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 477
 478         return total_mem;
 479 }
 480
 481 /* Use weak function to allow board file to override the address assignment */
 482 __attribute__((weak, alias("__step_assign_addresses")))
 483 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 484                           unsigned int dbw_cap_adj[]);
 485
 486 unsigned long long
 487 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 488                                        unsigned int size_only)
 489 {
 490         unsigned int i, j;
 491         unsigned long long total_mem = 0;
 492         int assert_reset = 0;
 493         unsigned int first_ctrl =  pinfo->first_ctrl;
 494         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 495         __maybe_unused int retval;
 496         __maybe_unused bool goodspd = false;
 497         __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 498
 499         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 500         common_timing_params_t *timing_params = pinfo->common_timing_params;
 501         if (pinfo->board_need_mem_reset)
 502                 assert_reset = pinfo->board_need_mem_reset();
 503
 504         /* data bus width capacity adjust shift amount */
 505         unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
 506
 507         for (i = first_ctrl; i <= last_ctrl; i++)
 508                 dbw_capacity_adjust[i] = 0;
 509
 510         debug("starting at step %u (%s)\n",
 511               start_step, step_to_string(start_step));
 512
 513         switch (start_step) {
 514         case STEP_GET_SPD:
 515 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 516                 /* STEP 1:  Gather all DIMM SPD data */
 517                 for (i = first_ctrl; i <= last_ctrl; i++) {
 518                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 519                                         dimm_slots_per_ctrl);
 520                 }
 521
 522         case STEP_COMPUTE_DIMM_PARMS:
 523                 /* STEP 2:  Compute DIMM parameters from SPD data */
 524
 525                 for (i = first_ctrl; i <= last_ctrl; i++) {
 526                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 527                                 generic_spd_eeprom_t *spd =
 528                                         &(pinfo->spd_installed_dimms[i][j]);
 529                                 dimm_params_t *pdimm =
 530                                         &(pinfo->dimm_params[i][j]);
 531                                 retval = compute_dimm_parameters(
 532                                                         i, spd, pdimm, j);
 533 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 534                                 if (!j && retval) {
 535                                         printf("SPD error on controller %d! "
 536                                         "Trying fallback to raw timing "
 537                                         "calculation\n", i);
 538                                         retval = fsl_ddr_get_dimm_params(pdimm,
 539                                                                          i, j);
 540                                 }
 541 #else
 542                                 if (retval == 2) {
 543                                         printf("Error: compute_dimm_parameters"
 544                                         " non-zero returned FATAL value "
 545                                         "for memctl=%u dimm=%u\n", i, j);
 546                                         return 0;
 547                                 }
 548 #endif
 549                                 if (retval) {
 550                                         debug("Warning: compute_dimm_parameters"
 551                                         " non-zero return value for memctl=%u "
 552                                         "dimm=%u\n", i, j);
 553                                 } else {
 554                                         goodspd = true;
 555                                 }
 556                         }
 557                 }
 558                 if (!goodspd) {
 559                         /*
 560                          * No valid SPD found
 561                          * Throw an error if this is for main memory, i.e.
 562                          * first_ctrl == 0. Otherwise, siliently return 0
 563                          * as the memory size.
 564                          */
 565                         if (first_ctrl == 0)
 566                                 printf("Error: No valid SPD detected.\n");
 567
 568                         return 0;
 569                 }
 570 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 571         case STEP_COMPUTE_DIMM_PARMS:
 572                 for (i = first_ctrl; i <= last_ctrl; i++) {
 573                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 574                                 dimm_params_t *pdimm =
 575                                         &(pinfo->dimm_params[i][j]);
 576                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 577                         }
 578                 }
 579                 debug("Filling dimm parameters from board specific file\n");
 580 #endif
 581         case STEP_COMPUTE_COMMON_PARMS:
 582                 /*
 583                  * STEP 3: Compute a common set of timing parameters
 584                  * suitable for all of the DIMMs on each memory controller
 585                  */
 586                 for (i = first_ctrl; i <= last_ctrl; i++) {
 587                         debug("Computing lowest common DIMM"
 588                                 " parameters for memctl=%u\n", i);
 589                         compute_lowest_common_dimm_parameters
 590                                 (i,
 591                                  pinfo->dimm_params[i],
 592                                  &timing_params[i],
 593                                  CONFIG_DIMM_SLOTS_PER_CTLR);
 594                 }
 595
 596         case STEP_GATHER_OPTS:
 597                 /* STEP 4:  Gather configuration requirements from user */
 598                 for (i = first_ctrl; i <= last_ctrl; i++) {
 599                         debug("Reloading memory controller "
 600                                 "configuration options for memctl=%u\n", i);
 601                         /*
 602                          * This "reloads" the memory controller options
 603                          * to defaults.  If the user "edits" an option,
 604                          * next_step points to the step after this,
 605                          * which is currently STEP_ASSIGN_ADDRESSES.
 606                          */
 607                         populate_memctl_options(
 608                                         &timing_params[i],
 609                                         &pinfo->memctl_opts[i],
 610                                         pinfo->dimm_params[i], i);
 611                         /*
 612                          * For RDIMMs, JEDEC spec requires clocks to be stable
 613                          * before reset signal is deasserted. For the boards
 614                          * using fixed parameters, this function should be
 615                          * be called from board init file.
 616                          */
 617                         if (timing_params[i].all_dimms_registered)
 618                                 assert_reset = 1;
 619                 }
 620                 if (assert_reset && !size_only) {
 621                         if (pinfo->board_mem_reset) {
 622                                 debug("Asserting mem reset\n");
 623                                 pinfo->board_mem_reset();
 624                         } else {
 625                                 debug("Asserting mem reset missing\n");
 626                         }
 627                 }
 628
 629         case STEP_ASSIGN_ADDRESSES:
 630                 /* STEP 5:  Assign addresses to chip selects */
 631                 check_interleaving_options(pinfo);
 632                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 633                 debug("Total mem %llu assigned\n", total_mem);
 634
 635         case STEP_COMPUTE_REGS:
 636                 /* STEP 6:  compute controller register values */
 637                 debug("FSL Memory ctrl register computation\n");
 638                 for (i = first_ctrl; i <= last_ctrl; i++) {
 639                         if (timing_params[i].ndimms_present == 0) {
 640                                 memset(&ddr_reg[i], 0,
 641                                         sizeof(fsl_ddr_cfg_regs_t));
 642                                 continue;
 643                         }
 644
 645                         compute_fsl_memctl_config_regs
 646                                 (i,
 647                                  &pinfo->memctl_opts[i],
 648                                  &ddr_reg[i], &timing_params[i],
 649                                  pinfo->dimm_params[i],
 650                                  dbw_capacity_adjust[i],
 651                                  size_only);
 652                 }
 653
 654         default:
 655                 break;
 656         }
 657
 658         {
 659                 /*
 660                  * Compute the amount of memory available just by
 661                  * looking for the highest valid CSn_BNDS value.
 662                  * This allows us to also experiment with using
 663                  * only CS0 when using dual-rank DIMMs.
 664                  */
 665                 unsigned int max_end = 0;
 666
 667                 for (i = first_ctrl; i <= last_ctrl; i++) {
 668                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 669                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 670                                 if (reg->cs[j].config & 0x80000000) {
 671                                         unsigned int end;
 672                                         /*
 673                                          * 0xfffffff is a special value we put
 674                                          * for unused bnds
 675                                          */
 676                                         if (reg->cs[j].bnds == 0xffffffff)
 677                                                 continue;
 678                                         end = reg->cs[j].bnds & 0xffff;
 679                                         if (end > max_end) {
 680                                                 max_end = end;
 681                                         }
 682                                 }
 683                         }
 684                 }
 685
 686                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 687                             0xFFFFFFULL) - pinfo->mem_base;
 688         }
 689
 690         return total_mem;
 691 }
 692
 693 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 694 {
 695         unsigned int i, first_ctrl, last_ctrl;
 696 #ifdef CONFIG_PPC
 697         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 698 #endif
 699         unsigned long long total_memory;
 700         int deassert_reset = 0;
 701
 702         first_ctrl = pinfo->first_ctrl;
 703         last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 704
 705         /* Compute it once normally. */
 706 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 707         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 708                 total_memory = fsl_ddr_interactive(pinfo, 0);
 709         } else if (fsl_ddr_interactive_env_var_exists()) {
 710                 total_memory = fsl_ddr_interactive(pinfo, 1);
 711         } else
 712 #endif
 713                 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 714
 715         /* setup 3-way interleaving before enabling DDRC */
 716         switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 717         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 718         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 719         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 720                 fsl_ddr_set_intl3r(
 721                         pinfo->memctl_opts[first_ctrl].
 722                         memctl_interleaving_mode);
 723                 break;
 724         default:
 725                 break;
 726         }
 727
 728         /*
 729          * Program configuration registers.
 730          * JEDEC specs requires clocks to be stable before deasserting reset
 731          * for RDIMMs. Clocks start after chip select is enabled and clock
 732          * control register is set. During step 1, all controllers have their
 733          * registers set but not enabled. Step 2 proceeds after deasserting
 734          * reset through board FPGA or GPIO.
 735          * For non-registered DIMMs, initialization can go through but it is
 736          * also OK to follow the same flow.
 737          */
 738         if (pinfo->board_need_mem_reset)
 739                 deassert_reset = pinfo->board_need_mem_reset();
 740         for (i = first_ctrl; i <= last_ctrl; i++) {
 741                 if (pinfo->common_timing_params[i].all_dimms_registered)
 742                         deassert_reset = 1;
 743         }
 744         for (i = first_ctrl; i <= last_ctrl; i++) {
 745                 debug("Programming controller %u\n", i);
 746                 if (pinfo->common_timing_params[i].ndimms_present == 0) {
 747                         debug("No dimms present on controller %u; "
 748                                         "skipping programming\n", i);
 749                         continue;
 750                 }
 751                 /*
 752                  * The following call with step = 1 returns before enabling
 753                  * the controller. It has to finish with step = 2 later.
 754                  */
 755                 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 756                                         deassert_reset ? 1 : 0);
 757         }
 758         if (deassert_reset) {
 759                 /* Use board FPGA or GPIO to deassert reset signal */
 760                 if (pinfo->board_mem_de_reset) {
 761                         debug("Deasserting mem reset\n");
 762                         pinfo->board_mem_de_reset();
 763                 } else {
 764                         debug("Deasserting mem reset missing\n");
 765                 }
 766                 for (i = first_ctrl; i <= last_ctrl; i++) {
 767                         /* Call with step = 2 to continue initialization */
 768                         fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 769                                                 i, 2);
 770                 }
 771         }
 772
 773 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 774         fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 775 #endif
 776
 777 #ifdef CONFIG_PPC
 778         /* program LAWs */
 779         for (i = first_ctrl; i <= last_ctrl; i++) {
 780                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 781                         switch (pinfo->memctl_opts[i].
 782                                 memctl_interleaving_mode) {
 783                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 784                         case FSL_DDR_PAGE_INTERLEAVING:
 785                         case FSL_DDR_BANK_INTERLEAVING:
 786                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 787                                 if (i % 2)
 788                                         break;
 789                                 if (i == 0) {
 790                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 791                                         fsl_ddr_set_lawbar(
 792                                                 &pinfo->common_timing_params[i],
 793                                                 law_memctl, i);
 794                                 }
 795 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
 796                                 else if (i == 2) {
 797                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 798                                         fsl_ddr_set_lawbar(
 799                                                 &pinfo->common_timing_params[i],
 800                                                 law_memctl, i);
 801                                 }
 802 #endif
 803                                 break;
 804                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 805                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 806                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 807                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 808                                 if (i == 0) {
 809                                         fsl_ddr_set_lawbar(
 810                                                 &pinfo->common_timing_params[i],
 811                                                 law_memctl, i);
 812                                 }
 813                                 break;
 814                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 815                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 816                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 817                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 818                                 if (i == 0)
 819                                         fsl_ddr_set_lawbar(
 820                                                 &pinfo->common_timing_params[i],
 821                                                 law_memctl, i);
 822                                 /* place holder for future 4-way interleaving */
 823                                 break;
 824                         default:
 825                                 break;
 826                         }
 827                 } else {
 828                         switch (i) {
 829                         case 0:
 830                                 law_memctl = LAW_TRGT_IF_DDR_1;
 831                                 break;
 832                         case 1:
 833                                 law_memctl = LAW_TRGT_IF_DDR_2;
 834                                 break;
 835                         case 2:
 836                                 law_memctl = LAW_TRGT_IF_DDR_3;
 837                                 break;
 838                         case 3:
 839                                 law_memctl = LAW_TRGT_IF_DDR_4;
 840                                 break;
 841                         default:
 842                                 break;
 843                         }
 844                         fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 845                                            law_memctl, i);
 846                 }
 847         }
 848 #endif
 849
 850         debug("total_memory by %s = %llu\n", __func__, total_memory);
 851
 852 #if !defined(CONFIG_PHYS_64BIT)
 853         /* Check for 4G or more.  Bad. */
 854         if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 855                 puts("Detected ");
 856                 print_size(total_memory, " of memory\n");
 857                 printf("       This U-Boot only supports < 4G of DDR\n");
 858                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 859                 printf("       "); /* re-align to match init_dram print */
 860                 total_memory = CONFIG_MAX_MEM_MAPPED;
 861         }
 862 #endif
 863
 864         return total_memory;
 865 }
 866
 867 /*
 868  * fsl_ddr_sdram(void) -- this is the main function to be
 869  * called by dram_init() in the board file.
 870  *
 871  * It returns amount of memory configured in bytes.
 872  */
 873 phys_size_t fsl_ddr_sdram(void)
 874 {
 875         fsl_ddr_info_t info;
 876
 877         /* Reset info structure. */
 878         memset(&info, 0, sizeof(fsl_ddr_info_t));
 879         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 880         info.first_ctrl = 0;
 881         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 882         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 883         info.board_need_mem_reset = board_need_mem_reset;
 884         info.board_mem_reset = board_assert_mem_reset;
 885         info.board_mem_de_reset = board_deassert_mem_reset;
 886         remove_unused_controllers(&info);
 887
 888         return __fsl_ddr_sdram(&info);
 889 }
 890
 891 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 892 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 893                                 unsigned int first_ctrl,
 894                                 unsigned int num_ctrls,
 895                                 unsigned int dimm_slots_per_ctrl,
 896                                 int (*board_need_reset)(void),
 897                                 void (*board_reset)(void),
 898                                 void (*board_de_reset)(void))
 899 {
 900         fsl_ddr_info_t info;
 901
 902         /* Reset info structure. */
 903         memset(&info, 0, sizeof(fsl_ddr_info_t));
 904         info.mem_base = base;
 905         info.first_ctrl = first_ctrl;
 906         info.num_ctrls = num_ctrls;
 907         info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 908         info.board_need_mem_reset = board_need_reset;
 909         info.board_mem_reset = board_reset;
 910         info.board_mem_de_reset = board_de_reset;
 911
 912         return __fsl_ddr_sdram(&info);
 913 }
 914 #endif
 915
 916 /*
 917  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 918  * size of the total memory without setting ddr control registers.
 919  */
 920 phys_size_t
 921 fsl_ddr_sdram_size(void)
 922 {
 923         fsl_ddr_info_t  info;
 924         unsigned long long total_memory = 0;
 925
 926         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 927         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 928         info.first_ctrl = 0;
 929         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 930         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 931         info.board_need_mem_reset = NULL;
 932         remove_unused_controllers(&info);
 933
 934         /* Compute it once normally. */
 935         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 936
 937         return total_memory;
 938 }