drivers/ddr/fsl/lc_common_dimm_params.c

   1 /*
   2  * Copyright 2008-2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017-2018 NXP Semiconductor
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  */
   7
   8 #include <common.h>
   9 #include <fsl_ddr_sdram.h>
  10
  11 #include <fsl_ddr.h>
  12
  13 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
  14 static unsigned int
  15 compute_cas_latency(const unsigned int ctrl_num,
  16                     const dimm_params_t *dimm_params,
  17                     common_timing_params_t *outpdimm,
  18                     unsigned int number_of_dimms)
  19 {
  20         unsigned int i;
  21         unsigned int common_caslat;
  22         unsigned int caslat_actual;
  23         unsigned int retry = 16;
  24         unsigned int tmp = ~0;
  25         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  26 #ifdef CONFIG_SYS_FSL_DDR3
  27         const unsigned int taamax = 20000;
  28 #else
  29         const unsigned int taamax = 18000;
  30 #endif
  31
  32         /* compute the common CAS latency supported between slots */
  33         for (i = 0; i < number_of_dimms; i++) {
  34                 if (dimm_params[i].n_ranks)
  35                         tmp &= dimm_params[i].caslat_x;
  36         }
  37         common_caslat = tmp;
  38
  39         /* validate if the memory clk is in the range of dimms */
  40         if (mclk_ps < outpdimm->tckmin_x_ps) {
  41                 printf("DDR clock (MCLK cycle %u ps) is faster than "
  42                         "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
  43                         mclk_ps, outpdimm->tckmin_x_ps);
  44         }
  45 #ifdef CONFIG_SYS_FSL_DDR4
  46         if (mclk_ps > outpdimm->tckmax_ps) {
  47                 printf("DDR clock (MCLK cycle %u ps) is slower than DIMM(s) (tCKmax %u ps) can support.\n",
  48                        mclk_ps, outpdimm->tckmax_ps);
  49         }
  50 #endif
  51         /* determine the acutal cas latency */
  52         caslat_actual = (outpdimm->taamin_ps + mclk_ps - 1) / mclk_ps;
  53         /* check if the dimms support the CAS latency */
  54         while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
  55                 caslat_actual++;
  56                 retry--;
  57         }
  58         /* once the caculation of caslat_actual is completed
  59          * we must verify that this CAS latency value does not
  60          * exceed tAAmax, which is 20 ns for all DDR3 speed grades,
  61          * 18ns for all DDR4 speed grades.
  62          */
  63         if (caslat_actual * mclk_ps > taamax) {
  64                 printf("The chosen cas latency %d is too large\n",
  65                        caslat_actual);
  66         }
  67         outpdimm->lowest_common_spd_caslat = caslat_actual;
  68         debug("lowest_common_spd_caslat is 0x%x\n", caslat_actual);
  69
  70         return 0;
  71 }
  72 #else   /* for DDR1 and DDR2 */
  73 static unsigned int
  74 compute_cas_latency(const unsigned int ctrl_num,
  75                     const dimm_params_t *dimm_params,
  76                     common_timing_params_t *outpdimm,
  77                     unsigned int number_of_dimms)
  78 {
  79         int i;
  80         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  81         unsigned int lowest_good_caslat;
  82         unsigned int not_ok;
  83         unsigned int temp1, temp2;
  84
  85         debug("using mclk_ps = %u\n", mclk_ps);
  86         if (mclk_ps > outpdimm->tckmax_ps) {
  87                 printf("Warning: DDR clock (%u ps) is slower than DIMM(s) (tCKmax %u ps)\n",
  88                        mclk_ps, outpdimm->tckmax_ps);
  89         }
  90
  91         /*
  92          * Compute a CAS latency suitable for all DIMMs
  93          *
  94          * Strategy for SPD-defined latencies: compute only
  95          * CAS latency defined by all DIMMs.
  96          */
  97
  98         /*
  99          * Step 1: find CAS latency common to all DIMMs using bitwise
 100          * operation.
 101          */
 102         temp1 = 0xFF;
 103         for (i = 0; i < number_of_dimms; i++) {
 104                 if (dimm_params[i].n_ranks) {
 105                         temp2 = 0;
 106                         temp2 |= 1 << dimm_params[i].caslat_x;
 107                         temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
 108                         temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
 109                         /*
 110                          * If there was no entry for X-2 (X-1) in
 111                          * the SPD, then caslat_x_minus_2
 112                          * (caslat_x_minus_1) contains either 255 or
 113                          * 0xFFFFFFFF because that's what the glorious
 114                          * __ilog2 function returns for an input of 0.
 115                          * On 32-bit PowerPC, left shift counts with bit
 116                          * 26 set (that the value of 255 or 0xFFFFFFFF
 117                          * will have), cause the destination register to
 118                          * be 0.  That is why this works.
 119                          */
 120                         temp1 &= temp2;
 121                 }
 122         }
 123
 124         /*
 125          * Step 2: check each common CAS latency against tCK of each
 126          * DIMM's SPD.
 127          */
 128         lowest_good_caslat = 0;
 129         temp2 = 0;
 130         while (temp1) {
 131                 not_ok = 0;
 132                 temp2 =  __ilog2(temp1);
 133                 debug("checking common caslat = %u\n", temp2);
 134
 135                 /* Check if this CAS latency will work on all DIMMs at tCK. */
 136                 for (i = 0; i < number_of_dimms; i++) {
 137                         if (!dimm_params[i].n_ranks)
 138                                 continue;
 139
 140                         if (dimm_params[i].caslat_x == temp2) {
 141                                 if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
 142                                         debug("CL = %u ok on DIMM %u at tCK=%u ps with tCKmin_X_ps of %u\n",
 143                                               temp2, i, mclk_ps,
 144                                               dimm_params[i].tckmin_x_ps);
 145                                         continue;
 146                                 } else {
 147                                         not_ok++;
 148                                 }
 149                         }
 150
 151                         if (dimm_params[i].caslat_x_minus_1 == temp2) {
 152                                 unsigned int tckmin_x_minus_1_ps
 153                                         = dimm_params[i].tckmin_x_minus_1_ps;
 154                                 if (mclk_ps >= tckmin_x_minus_1_ps) {
 155                                         debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_1_ps of %u\n",
 156                                               temp2, i, mclk_ps,
 157                                               tckmin_x_minus_1_ps);
 158                                         continue;
 159                                 } else {
 160                                         not_ok++;
 161                                 }
 162                         }
 163
 164                         if (dimm_params[i].caslat_x_minus_2 == temp2) {
 165                                 unsigned int tckmin_x_minus_2_ps
 166                                         = dimm_params[i].tckmin_x_minus_2_ps;
 167                                 if (mclk_ps >= tckmin_x_minus_2_ps) {
 168                                         debug("CL = %u ok on DIMM %u at tCK=%u ps with tckmin_x_minus_2_ps of %u\n",
 169                                               temp2, i, mclk_ps,
 170                                               tckmin_x_minus_2_ps);
 171                                         continue;
 172                                 } else {
 173                                         not_ok++;
 174                                 }
 175                         }
 176                 }
 177
 178                 if (!not_ok)
 179                         lowest_good_caslat = temp2;
 180
 181                 temp1 &= ~(1 << temp2);
 182         }
 183
 184         debug("lowest common SPD-defined CAS latency = %u\n",
 185               lowest_good_caslat);
 186         outpdimm->lowest_common_spd_caslat = lowest_good_caslat;
 187
 188
 189         /*
 190          * Compute a common 'de-rated' CAS latency.
 191          *
 192          * The strategy here is to find the *highest* dereated cas latency
 193          * with the assumption that all of the DIMMs will support a dereated
 194          * CAS latency higher than or equal to their lowest dereated value.
 195          */
 196         temp1 = 0;
 197         for (i = 0; i < number_of_dimms; i++)
 198                 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
 199
 200         outpdimm->highest_common_derated_caslat = temp1;
 201         debug("highest common dereated CAS latency = %u\n", temp1);
 202
 203         return 0;
 204 }
 205 #endif
 206
 207 /*
 208  * compute_lowest_common_dimm_parameters()
 209  *
 210  * Determine the worst-case DIMM timing parameters from the set of DIMMs
 211  * whose parameters have been computed into the array pointed to
 212  * by dimm_params.
 213  */
 214 unsigned int
 215 compute_lowest_common_dimm_parameters(const unsigned int ctrl_num,
 216                                       const dimm_params_t *dimm_params,
 217                                       common_timing_params_t *outpdimm,
 218                                       const unsigned int number_of_dimms)
 219 {
 220         unsigned int i, j;
 221
 222         unsigned int tckmin_x_ps = 0;
 223         unsigned int tckmax_ps = 0xFFFFFFFF;
 224         unsigned int trcd_ps = 0;
 225         unsigned int trp_ps = 0;
 226         unsigned int tras_ps = 0;
 227 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 228         unsigned int taamin_ps = 0;
 229 #endif
 230 #ifdef CONFIG_SYS_FSL_DDR4
 231         unsigned int twr_ps = 15000;
 232         unsigned int trfc1_ps = 0;
 233         unsigned int trfc2_ps = 0;
 234         unsigned int trfc4_ps = 0;
 235         unsigned int trrds_ps = 0;
 236         unsigned int trrdl_ps = 0;
 237         unsigned int tccdl_ps = 0;
 238         unsigned int trfc_slr_ps = 0;
 239 #else
 240         unsigned int twr_ps = 0;
 241         unsigned int twtr_ps = 0;
 242         unsigned int trfc_ps = 0;
 243         unsigned int trrd_ps = 0;
 244         unsigned int trtp_ps = 0;
 245 #endif
 246         unsigned int trc_ps = 0;
 247         unsigned int refresh_rate_ps = 0;
 248         unsigned int extended_op_srt = 1;
 249 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 250         unsigned int tis_ps = 0;
 251         unsigned int tih_ps = 0;
 252         unsigned int tds_ps = 0;
 253         unsigned int tdh_ps = 0;
 254         unsigned int tdqsq_max_ps = 0;
 255         unsigned int tqhs_ps = 0;
 256 #endif
 257         unsigned int temp1, temp2;
 258         unsigned int additive_latency = 0;
 259
 260         temp1 = 0;
 261         for (i = 0; i < number_of_dimms; i++) {
 262                 /*
 263                  * If there are no ranks on this DIMM,
 264                  * it probably doesn't exist, so skip it.
 265                  */
 266                 if (dimm_params[i].n_ranks == 0) {
 267                         temp1++;
 268                         continue;
 269                 }
 270                 if (dimm_params[i].n_ranks == 4 && i != 0) {
 271                         printf("Found Quad-rank DIMM in wrong bank, ignored."
 272                                 " Software may not run as expected.\n");
 273                         temp1++;
 274                         continue;
 275                 }
 276
 277                 /*
 278                  * check if quad-rank DIMM is plugged if
 279                  * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
 280                  * Only the board with proper design is capable
 281                  */
 282 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 283                 if (dimm_params[i].n_ranks == 4 && \
 284                   CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 285                         printf("Found Quad-rank DIMM, not able to support.");
 286                         temp1++;
 287                         continue;
 288                 }
 289 #endif
 290                 /*
 291                  * Find minimum tckmax_ps to find fastest slow speed,
 292                  * i.e., this is the slowest the whole system can go.
 293                  */
 294                 tckmax_ps = min(tckmax_ps,
 295                                 (unsigned int)dimm_params[i].tckmax_ps);
 296 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 297                 taamin_ps = max(taamin_ps,
 298                                 (unsigned int)dimm_params[i].taa_ps);
 299 #endif
 300                 tckmin_x_ps = max(tckmin_x_ps,
 301                                   (unsigned int)dimm_params[i].tckmin_x_ps);
 302                 trcd_ps = max(trcd_ps, (unsigned int)dimm_params[i].trcd_ps);
 303                 trp_ps = max(trp_ps, (unsigned int)dimm_params[i].trp_ps);
 304                 tras_ps = max(tras_ps, (unsigned int)dimm_params[i].tras_ps);
 305 #ifdef CONFIG_SYS_FSL_DDR4
 306                 trfc1_ps = max(trfc1_ps,
 307                                (unsigned int)dimm_params[i].trfc1_ps);
 308                 trfc2_ps = max(trfc2_ps,
 309                                (unsigned int)dimm_params[i].trfc2_ps);
 310                 trfc4_ps = max(trfc4_ps,
 311                                (unsigned int)dimm_params[i].trfc4_ps);
 312                 trrds_ps = max(trrds_ps,
 313                                (unsigned int)dimm_params[i].trrds_ps);
 314                 trrdl_ps = max(trrdl_ps,
 315                                (unsigned int)dimm_params[i].trrdl_ps);
 316                 tccdl_ps = max(tccdl_ps,
 317                                (unsigned int)dimm_params[i].tccdl_ps);
 318                 trfc_slr_ps = max(trfc_slr_ps,
 319                                   (unsigned int)dimm_params[i].trfc_slr_ps);
 320 #else
 321                 twr_ps = max(twr_ps, (unsigned int)dimm_params[i].twr_ps);
 322                 twtr_ps = max(twtr_ps, (unsigned int)dimm_params[i].twtr_ps);
 323                 trfc_ps = max(trfc_ps, (unsigned int)dimm_params[i].trfc_ps);
 324                 trrd_ps = max(trrd_ps, (unsigned int)dimm_params[i].trrd_ps);
 325                 trtp_ps = max(trtp_ps, (unsigned int)dimm_params[i].trtp_ps);
 326 #endif
 327                 trc_ps = max(trc_ps, (unsigned int)dimm_params[i].trc_ps);
 328 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 329                 tis_ps = max(tis_ps, (unsigned int)dimm_params[i].tis_ps);
 330                 tih_ps = max(tih_ps, (unsigned int)dimm_params[i].tih_ps);
 331                 tds_ps = max(tds_ps, (unsigned int)dimm_params[i].tds_ps);
 332                 tdh_ps = max(tdh_ps, (unsigned int)dimm_params[i].tdh_ps);
 333                 tqhs_ps = max(tqhs_ps, (unsigned int)dimm_params[i].tqhs_ps);
 334                 /*
 335                  * Find maximum tdqsq_max_ps to find slowest.
 336                  *
 337                  * FIXME: is finding the slowest value the correct
 338                  * strategy for this parameter?
 339                  */
 340                 tdqsq_max_ps = max(tdqsq_max_ps,
 341                                    (unsigned int)dimm_params[i].tdqsq_max_ps);
 342 #endif
 343                 refresh_rate_ps = max(refresh_rate_ps,
 344                                       (unsigned int)dimm_params[i].refresh_rate_ps);
 345                 /* extended_op_srt is either 0 or 1, 0 having priority */
 346                 extended_op_srt = min(extended_op_srt,
 347                                       (unsigned int)dimm_params[i].extended_op_srt);
 348         }
 349
 350         outpdimm->ndimms_present = number_of_dimms - temp1;
 351
 352         if (temp1 == number_of_dimms) {
 353                 debug("no dimms this memory controller\n");
 354                 return 0;
 355         }
 356
 357         outpdimm->tckmin_x_ps = tckmin_x_ps;
 358         outpdimm->tckmax_ps = tckmax_ps;
 359 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 360         outpdimm->taamin_ps = taamin_ps;
 361 #endif
 362         outpdimm->trcd_ps = trcd_ps;
 363         outpdimm->trp_ps = trp_ps;
 364         outpdimm->tras_ps = tras_ps;
 365 #ifdef CONFIG_SYS_FSL_DDR4
 366         outpdimm->trfc1_ps = trfc1_ps;
 367         outpdimm->trfc2_ps = trfc2_ps;
 368         outpdimm->trfc4_ps = trfc4_ps;
 369         outpdimm->trrds_ps = trrds_ps;
 370         outpdimm->trrdl_ps = trrdl_ps;
 371         outpdimm->tccdl_ps = tccdl_ps;
 372         outpdimm->trfc_slr_ps = trfc_slr_ps;
 373 #else
 374         outpdimm->twtr_ps = twtr_ps;
 375         outpdimm->trfc_ps = trfc_ps;
 376         outpdimm->trrd_ps = trrd_ps;
 377         outpdimm->trtp_ps = trtp_ps;
 378 #endif
 379         outpdimm->twr_ps = twr_ps;
 380         outpdimm->trc_ps = trc_ps;
 381         outpdimm->refresh_rate_ps = refresh_rate_ps;
 382         outpdimm->extended_op_srt = extended_op_srt;
 383 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 384         outpdimm->tis_ps = tis_ps;
 385         outpdimm->tih_ps = tih_ps;
 386         outpdimm->tds_ps = tds_ps;
 387         outpdimm->tdh_ps = tdh_ps;
 388         outpdimm->tdqsq_max_ps = tdqsq_max_ps;
 389         outpdimm->tqhs_ps = tqhs_ps;
 390 #endif
 391
 392         /* Determine common burst length for all DIMMs. */
 393         temp1 = 0xff;
 394         for (i = 0; i < number_of_dimms; i++) {
 395                 if (dimm_params[i].n_ranks) {
 396                         temp1 &= dimm_params[i].burst_lengths_bitmask;
 397                 }
 398         }
 399         outpdimm->all_dimms_burst_lengths_bitmask = temp1;
 400
 401         /* Determine if all DIMMs registered buffered. */
 402         temp1 = temp2 = 0;
 403         for (i = 0; i < number_of_dimms; i++) {
 404                 if (dimm_params[i].n_ranks) {
 405                         if (dimm_params[i].registered_dimm) {
 406                                 temp1 = 1;
 407 #ifndef CONFIG_SPL_BUILD
 408                                 printf("Detected RDIMM %s\n",
 409                                         dimm_params[i].mpart);
 410 #endif
 411                         } else {
 412                                 temp2 = 1;
 413 #ifndef CONFIG_SPL_BUILD
 414                                 printf("Detected UDIMM %s\n",
 415                                         dimm_params[i].mpart);
 416 #endif
 417                         }
 418                 }
 419         }
 420
 421         outpdimm->all_dimms_registered = 0;
 422         outpdimm->all_dimms_unbuffered = 0;
 423         if (temp1 && !temp2) {
 424                 outpdimm->all_dimms_registered = 1;
 425         } else if (!temp1 && temp2) {
 426                 outpdimm->all_dimms_unbuffered = 1;
 427         } else {
 428                 printf("ERROR:  Mix of registered buffered and unbuffered "
 429                                 "DIMMs detected!\n");
 430         }
 431
 432         temp1 = 0;
 433         if (outpdimm->all_dimms_registered)
 434                 for (j = 0; j < 16; j++) {
 435                         outpdimm->rcw[j] = dimm_params[0].rcw[j];
 436                         for (i = 1; i < number_of_dimms; i++) {
 437                                 if (!dimm_params[i].n_ranks)
 438                                         continue;
 439                                 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 440                                         temp1 = 1;
 441                                         break;
 442                                 }
 443                         }
 444                 }
 445
 446         if (temp1 != 0)
 447                 printf("ERROR: Mix different RDIMM detected!\n");
 448
 449         /* calculate cas latency for all DDR types */
 450         if (compute_cas_latency(ctrl_num, dimm_params,
 451                                 outpdimm, number_of_dimms))
 452                 return 1;
 453
 454         /* Determine if all DIMMs ECC capable. */
 455         temp1 = 1;
 456         for (i = 0; i < number_of_dimms; i++) {
 457                 if (dimm_params[i].n_ranks &&
 458                         !(dimm_params[i].edc_config & EDC_ECC)) {
 459                         temp1 = 0;
 460                         break;
 461                 }
 462         }
 463         if (temp1) {
 464                 debug("all DIMMs ECC capable\n");
 465         } else {
 466                 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 467         }
 468         outpdimm->all_dimms_ecc_capable = temp1;
 469
 470         /*
 471          * Compute additive latency.
 472          *
 473          * For DDR1, additive latency should be 0.
 474          *
 475          * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
 476          *      which comes from Trcd, and also note that:
 477          *          add_lat + caslat must be >= 4
 478          *
 479          * For DDR3, we use the AL=0
 480          *
 481          * When to use additive latency for DDR2:
 482          *
 483          * I. Because you are using CL=3 and need to do ODT on writes and
 484          *    want functionality.
 485          *    1. Are you going to use ODT? (Does your board not have
 486          *      additional termination circuitry for DQ, DQS, DQS_,
 487          *      DM, RDQS, RDQS_ for x4/x8 configs?)
 488          *    2. If so, is your lowest supported CL going to be 3?
 489          *    3. If so, then you must set AL=1 because
 490          *
 491          *       WL >= 3 for ODT on writes
 492          *       RL = AL + CL
 493          *       WL = RL - 1
 494          *       ->
 495          *       WL = AL + CL - 1
 496          *       AL + CL - 1 >= 3
 497          *       AL + CL >= 4
 498          *  QED
 499          *
 500          *  RL >= 3 for ODT on reads
 501          *  RL = AL + CL
 502          *
 503          *  Since CL aren't usually less than 2, AL=0 is a minimum,
 504          *  so the WL-derived AL should be the  -- FIXME?
 505          *
 506          * II. Because you are using auto-precharge globally and want to
 507          *     use additive latency (posted CAS) to get more bandwidth.
 508          *     1. Are you going to use auto-precharge mode globally?
 509          *
 510          *        Use addtivie latency and compute AL to be 1 cycle less than
 511          *        tRCD, i.e. the READ or WRITE command is in the cycle
 512          *        immediately following the ACTIVATE command..
 513          *
 514          * III. Because you feel like it or want to do some sort of
 515          *      degraded-performance experiment.
 516          *     1.  Do you just want to use additive latency because you feel
 517          *         like it?
 518          *
 519          * Validation:  AL is less than tRCD, and within the other
 520          * read-to-precharge constraints.
 521          */
 522
 523         additive_latency = 0;
 524
 525 #if defined(CONFIG_SYS_FSL_DDR2)
 526         if ((outpdimm->lowest_common_spd_caslat < 4) &&
 527             (picos_to_mclk(ctrl_num, trcd_ps) >
 528              outpdimm->lowest_common_spd_caslat)) {
 529                 additive_latency = picos_to_mclk(ctrl_num, trcd_ps) -
 530                                    outpdimm->lowest_common_spd_caslat;
 531                 if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
 532                         additive_latency = picos_to_mclk(ctrl_num, trcd_ps);
 533                         debug("setting additive_latency to %u because it was "
 534                                 " greater than tRCD_ps\n", additive_latency);
 535                 }
 536         }
 537 #endif
 538
 539         /*
 540          * Validate additive latency
 541          *
 542          * AL <= tRCD(min)
 543          */
 544         if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) {
 545                 printf("Error: invalid additive latency exceeds tRCD(min).\n");
 546                 return 1;
 547         }
 548
 549         /*
 550          * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
 551          * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
 552          * ADD_LAT (the register) must be set to a value less
 553          * than ACTTORW if WL = 1, then AL must be set to 1
 554          * RD_TO_PRE (the register) must be set to a minimum
 555          * tRTP + AL if AL is nonzero
 556          */
 557
 558         /*
 559          * Additive latency will be applied only if the memctl option to
 560          * use it.
 561          */
 562         outpdimm->additive_latency = additive_latency;
 563
 564         debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
 565         debug("trcd_ps   = %u\n", outpdimm->trcd_ps);
 566         debug("trp_ps    = %u\n", outpdimm->trp_ps);
 567         debug("tras_ps   = %u\n", outpdimm->tras_ps);
 568 #ifdef CONFIG_SYS_FSL_DDR4
 569         debug("trfc1_ps = %u\n", trfc1_ps);
 570         debug("trfc2_ps = %u\n", trfc2_ps);
 571         debug("trfc4_ps = %u\n", trfc4_ps);
 572         debug("trrds_ps = %u\n", trrds_ps);
 573         debug("trrdl_ps = %u\n", trrdl_ps);
 574         debug("tccdl_ps = %u\n", tccdl_ps);
 575         debug("trfc_slr_ps = %u\n", trfc_slr_ps);
 576 #else
 577         debug("twtr_ps   = %u\n", outpdimm->twtr_ps);
 578         debug("trfc_ps   = %u\n", outpdimm->trfc_ps);
 579         debug("trrd_ps   = %u\n", outpdimm->trrd_ps);
 580 #endif
 581         debug("twr_ps    = %u\n", outpdimm->twr_ps);
 582         debug("trc_ps    = %u\n", outpdimm->trc_ps);
 583
 584         return 0;
 585 }