drivers/ddr/fsl/interactive.c

   1 /*
   2  * Copyright 2010-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  *         York Sun [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <cli.h>
  16 #include <linux/ctype.h>
  17 #include <asm/types.h>
  18 #include <asm/io.h>
  19
  20 #include <fsl_ddr_sdram.h>
  21 #include <fsl_ddr.h>
  22
  23 /* Option parameter Structures */
  24 struct options_string {
  25         const char *option_name;
  26         size_t offset;
  27         unsigned int size;
  28         const char printhex;
  29 };
  30
  31 static unsigned int picos_to_mhz(unsigned int picos)
  32 {
  33         return 1000000 / picos;
  34 }
  35
  36 static void print_option_table(const struct options_string *table,
  37                          int table_size,
  38                          const void *base)
  39 {
  40         unsigned int i;
  41         unsigned int *ptr;
  42         unsigned long long *ptr_l;
  43
  44         for (i = 0; i < table_size; i++) {
  45                 switch (table[i].size) {
  46                 case 4:
  47                         ptr = (unsigned int *) (base + table[i].offset);
  48                         if (table[i].printhex) {
  49                                 printf("%s = 0x%08X\n",
  50                                         table[i].option_name, *ptr);
  51                         } else {
  52                                 printf("%s = %u\n",
  53                                         table[i].option_name, *ptr);
  54                         }
  55                         break;
  56                 case 8:
  57                         ptr_l = (unsigned long long *) (base + table[i].offset);
  58                         printf("%s = %llu\n",
  59                                 table[i].option_name, *ptr_l);
  60                         break;
  61                 default:
  62                         printf("Unrecognized size!\n");
  63                         break;
  64                 }
  65         }
  66 }
  67
  68 static int handle_option_table(const struct options_string *table,
  69                          int table_size,
  70                          void *base,
  71                          const char *opt,
  72                          const char *val)
  73 {
  74         unsigned int i;
  75         unsigned int value, *ptr;
  76         unsigned long long value_l, *ptr_l;
  77
  78         for (i = 0; i < table_size; i++) {
  79                 if (strcmp(table[i].option_name, opt) != 0)
  80                         continue;
  81                 switch (table[i].size) {
  82                 case 4:
  83                         value = simple_strtoul(val, NULL, 0);
  84                         ptr = base + table[i].offset;
  85                         *ptr = value;
  86                         break;
  87                 case 8:
  88                         value_l = simple_strtoull(val, NULL, 0);
  89                         ptr_l = base + table[i].offset;
  90                         *ptr_l = value_l;
  91                         break;
  92                 default:
  93                         printf("Unrecognized size!\n");
  94                         break;
  95                 }
  96                 return 1;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void fsl_ddr_generic_edit(void *pdata,
 103                            void *pend,
 104                            unsigned int element_size,
 105                            unsigned int element_num,
 106                            unsigned int value)
 107 {
 108         char *pcdata = (char *)pdata;           /* BIG ENDIAN ONLY */
 109
 110         pcdata += element_num * element_size;
 111         if ((pcdata + element_size) > (char *) pend) {
 112                 printf("trying to write past end of data\n");
 113                 return;
 114         }
 115
 116         switch (element_size) {
 117         case 1:
 118                 __raw_writeb(value, pcdata);
 119                 break;
 120         case 2:
 121                 __raw_writew(value, pcdata);
 122                 break;
 123         case 4:
 124                 __raw_writel(value, pcdata);
 125                 break;
 126         default:
 127                 printf("unexpected element size %u\n", element_size);
 128                 break;
 129         }
 130 }
 131
 132 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
 133                        unsigned int ctrl_num,
 134                        unsigned int dimm_num,
 135                        unsigned int element_num,
 136                        unsigned int value)
 137 {
 138         generic_spd_eeprom_t *pspd;
 139
 140         pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
 141         fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
 142 }
 143
 144 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
 145         sizeof((common_timing_params_t *)0)->x, 0}
 146
 147 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 148                                         unsigned int ctrl_num,
 149                                         const char *optname_str,
 150                                         const char *value_str)
 151 {
 152         common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 153
 154         static const struct options_string options[] = {
 155                 COMMON_TIMING(tckmin_x_ps),
 156                 COMMON_TIMING(tckmax_ps),
 157 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 158                 COMMON_TIMING(taamin_ps),
 159 #endif
 160                 COMMON_TIMING(trcd_ps),
 161                 COMMON_TIMING(trp_ps),
 162                 COMMON_TIMING(tras_ps),
 163
 164 #ifdef CONFIG_SYS_FSL_DDR4
 165                 COMMON_TIMING(trfc1_ps),
 166                 COMMON_TIMING(trfc2_ps),
 167                 COMMON_TIMING(trfc4_ps),
 168                 COMMON_TIMING(trrds_ps),
 169                 COMMON_TIMING(trrdl_ps),
 170                 COMMON_TIMING(tccdl_ps),
 171 #else
 172                 COMMON_TIMING(twtr_ps),
 173                 COMMON_TIMING(trfc_ps),
 174                 COMMON_TIMING(trrd_ps),
 175                 COMMON_TIMING(trtp_ps),
 176 #endif
 177                 COMMON_TIMING(twr_ps),
 178                 COMMON_TIMING(trc_ps),
 179                 COMMON_TIMING(refresh_rate_ps),
 180                 COMMON_TIMING(extended_op_srt),
 181 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 182                 COMMON_TIMING(tis_ps),
 183                 COMMON_TIMING(tih_ps),
 184                 COMMON_TIMING(tds_ps),
 185                 COMMON_TIMING(tdh_ps),
 186                 COMMON_TIMING(tdqsq_max_ps),
 187                 COMMON_TIMING(tqhs_ps),
 188 #endif
 189                 COMMON_TIMING(ndimms_present),
 190                 COMMON_TIMING(lowest_common_spd_caslat),
 191                 COMMON_TIMING(highest_common_derated_caslat),
 192                 COMMON_TIMING(additive_latency),
 193                 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
 194                 COMMON_TIMING(all_dimms_registered),
 195                 COMMON_TIMING(all_dimms_unbuffered),
 196                 COMMON_TIMING(all_dimms_ecc_capable),
 197                 COMMON_TIMING(total_mem),
 198                 COMMON_TIMING(base_address),
 199         };
 200         static const unsigned int n_opts = ARRAY_SIZE(options);
 201
 202         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 203                 return;
 204
 205         printf("Error: couldn't find option string %s\n", optname_str);
 206 }
 207
 208 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
 209         sizeof((dimm_params_t *)0)->x, 0}
 210 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
 211         sizeof((dimm_params_t *)0)->x, 1}
 212
 213 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 214                                    unsigned int ctrl_num,
 215                                    unsigned int dimm_num,
 216                                    const char *optname_str,
 217                                    const char *value_str)
 218 {
 219         dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
 220
 221         static const struct options_string options[] = {
 222                 DIMM_PARM(n_ranks),
 223                 DIMM_PARM(data_width),
 224                 DIMM_PARM(primary_sdram_width),
 225                 DIMM_PARM(ec_sdram_width),
 226                 DIMM_PARM(registered_dimm),
 227                 DIMM_PARM(mirrored_dimm),
 228                 DIMM_PARM(device_width),
 229
 230                 DIMM_PARM(n_row_addr),
 231                 DIMM_PARM(n_col_addr),
 232                 DIMM_PARM(edc_config),
 233 #ifdef CONFIG_SYS_FSL_DDR4
 234                 DIMM_PARM(bank_addr_bits),
 235                 DIMM_PARM(bank_group_bits),
 236 #else
 237                 DIMM_PARM(n_banks_per_sdram_device),
 238 #endif
 239                 DIMM_PARM(burst_lengths_bitmask),
 240                 DIMM_PARM(row_density),
 241
 242                 DIMM_PARM(tckmin_x_ps),
 243                 DIMM_PARM(tckmin_x_minus_1_ps),
 244                 DIMM_PARM(tckmin_x_minus_2_ps),
 245                 DIMM_PARM(tckmax_ps),
 246
 247                 DIMM_PARM(caslat_x),
 248                 DIMM_PARM(caslat_x_minus_1),
 249                 DIMM_PARM(caslat_x_minus_2),
 250
 251                 DIMM_PARM(caslat_lowest_derated),
 252
 253                 DIMM_PARM(trcd_ps),
 254                 DIMM_PARM(trp_ps),
 255                 DIMM_PARM(tras_ps),
 256 #ifdef CONFIG_SYS_FSL_DDR4
 257                 DIMM_PARM(trfc1_ps),
 258                 DIMM_PARM(trfc2_ps),
 259                 DIMM_PARM(trfc4_ps),
 260                 DIMM_PARM(trrds_ps),
 261                 DIMM_PARM(trrdl_ps),
 262                 DIMM_PARM(tccdl_ps),
 263 #else
 264                 DIMM_PARM(twr_ps),
 265                 DIMM_PARM(twtr_ps),
 266                 DIMM_PARM(trfc_ps),
 267                 DIMM_PARM(trrd_ps),
 268                 DIMM_PARM(trtp_ps),
 269 #endif
 270                 DIMM_PARM(trc_ps),
 271                 DIMM_PARM(refresh_rate_ps),
 272                 DIMM_PARM(extended_op_srt),
 273
 274 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 275                 DIMM_PARM(tis_ps),
 276                 DIMM_PARM(tih_ps),
 277                 DIMM_PARM(tds_ps),
 278                 DIMM_PARM(tdh_ps),
 279                 DIMM_PARM(tdqsq_max_ps),
 280                 DIMM_PARM(tqhs_ps),
 281 #endif
 282 #ifdef CONFIG_SYS_FSL_DDR4
 283                 DIMM_PARM_HEX(dq_mapping[0]),
 284                 DIMM_PARM_HEX(dq_mapping[1]),
 285                 DIMM_PARM_HEX(dq_mapping[2]),
 286                 DIMM_PARM_HEX(dq_mapping[3]),
 287                 DIMM_PARM_HEX(dq_mapping[4]),
 288                 DIMM_PARM_HEX(dq_mapping[5]),
 289                 DIMM_PARM_HEX(dq_mapping[6]),
 290                 DIMM_PARM_HEX(dq_mapping[7]),
 291                 DIMM_PARM_HEX(dq_mapping[8]),
 292                 DIMM_PARM_HEX(dq_mapping[9]),
 293                 DIMM_PARM_HEX(dq_mapping[10]),
 294                 DIMM_PARM_HEX(dq_mapping[11]),
 295                 DIMM_PARM_HEX(dq_mapping[12]),
 296                 DIMM_PARM_HEX(dq_mapping[13]),
 297                 DIMM_PARM_HEX(dq_mapping[14]),
 298                 DIMM_PARM_HEX(dq_mapping[15]),
 299                 DIMM_PARM_HEX(dq_mapping[16]),
 300                 DIMM_PARM_HEX(dq_mapping[17]),
 301                 DIMM_PARM(dq_mapping_ors),
 302 #endif
 303                 DIMM_PARM(rank_density),
 304                 DIMM_PARM(capacity),
 305                 DIMM_PARM(base_address),
 306         };
 307
 308         static const unsigned int n_opts = ARRAY_SIZE(options);
 309
 310         if (handle_option_table(options, n_opts, p, optname_str, value_str))
 311                 return;
 312
 313         printf("couldn't find option string %s\n", optname_str);
 314 }
 315
 316 static void print_dimm_parameters(const dimm_params_t *pdimm)
 317 {
 318         static const struct options_string options[] = {
 319                 DIMM_PARM(n_ranks),
 320                 DIMM_PARM(data_width),
 321                 DIMM_PARM(primary_sdram_width),
 322                 DIMM_PARM(ec_sdram_width),
 323                 DIMM_PARM(registered_dimm),
 324                 DIMM_PARM(mirrored_dimm),
 325                 DIMM_PARM(device_width),
 326
 327                 DIMM_PARM(n_row_addr),
 328                 DIMM_PARM(n_col_addr),
 329                 DIMM_PARM(edc_config),
 330 #ifdef CONFIG_SYS_FSL_DDR4
 331                 DIMM_PARM(bank_addr_bits),
 332                 DIMM_PARM(bank_group_bits),
 333 #else
 334                 DIMM_PARM(n_banks_per_sdram_device),
 335 #endif
 336
 337                 DIMM_PARM(tckmin_x_ps),
 338                 DIMM_PARM(tckmin_x_minus_1_ps),
 339                 DIMM_PARM(tckmin_x_minus_2_ps),
 340                 DIMM_PARM(tckmax_ps),
 341
 342                 DIMM_PARM(caslat_x),
 343                 DIMM_PARM_HEX(caslat_x),
 344                 DIMM_PARM(taa_ps),
 345                 DIMM_PARM(caslat_x_minus_1),
 346                 DIMM_PARM(caslat_x_minus_2),
 347                 DIMM_PARM(caslat_lowest_derated),
 348
 349                 DIMM_PARM(trcd_ps),
 350                 DIMM_PARM(trp_ps),
 351                 DIMM_PARM(tras_ps),
 352 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 353                 DIMM_PARM(tfaw_ps),
 354 #endif
 355 #ifdef CONFIG_SYS_FSL_DDR4
 356                 DIMM_PARM(trfc1_ps),
 357                 DIMM_PARM(trfc2_ps),
 358                 DIMM_PARM(trfc4_ps),
 359                 DIMM_PARM(trrds_ps),
 360                 DIMM_PARM(trrdl_ps),
 361                 DIMM_PARM(tccdl_ps),
 362 #else
 363                 DIMM_PARM(twr_ps),
 364                 DIMM_PARM(twtr_ps),
 365                 DIMM_PARM(trfc_ps),
 366                 DIMM_PARM(trrd_ps),
 367                 DIMM_PARM(trtp_ps),
 368 #endif
 369                 DIMM_PARM(trc_ps),
 370                 DIMM_PARM(refresh_rate_ps),
 371
 372 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 373                 DIMM_PARM(tis_ps),
 374                 DIMM_PARM(tih_ps),
 375                 DIMM_PARM(tds_ps),
 376                 DIMM_PARM(tdh_ps),
 377                 DIMM_PARM(tdqsq_max_ps),
 378                 DIMM_PARM(tqhs_ps),
 379 #endif
 380 #ifdef CONFIG_SYS_FSL_DDR4
 381                 DIMM_PARM_HEX(dq_mapping[0]),
 382                 DIMM_PARM_HEX(dq_mapping[1]),
 383                 DIMM_PARM_HEX(dq_mapping[2]),
 384                 DIMM_PARM_HEX(dq_mapping[3]),
 385                 DIMM_PARM_HEX(dq_mapping[4]),
 386                 DIMM_PARM_HEX(dq_mapping[5]),
 387                 DIMM_PARM_HEX(dq_mapping[6]),
 388                 DIMM_PARM_HEX(dq_mapping[7]),
 389                 DIMM_PARM_HEX(dq_mapping[8]),
 390                 DIMM_PARM_HEX(dq_mapping[9]),
 391                 DIMM_PARM_HEX(dq_mapping[10]),
 392                 DIMM_PARM_HEX(dq_mapping[11]),
 393                 DIMM_PARM_HEX(dq_mapping[12]),
 394                 DIMM_PARM_HEX(dq_mapping[13]),
 395                 DIMM_PARM_HEX(dq_mapping[14]),
 396                 DIMM_PARM_HEX(dq_mapping[15]),
 397                 DIMM_PARM_HEX(dq_mapping[16]),
 398                 DIMM_PARM_HEX(dq_mapping[17]),
 399                 DIMM_PARM(dq_mapping_ors),
 400 #endif
 401         };
 402         static const unsigned int n_opts = ARRAY_SIZE(options);
 403
 404         if (pdimm->n_ranks == 0) {
 405                 printf("DIMM not present\n");
 406                 return;
 407         }
 408         printf("DIMM organization parameters:\n");
 409         printf("module part name = %s\n", pdimm->mpart);
 410         printf("rank_density = %llu bytes (%llu megabytes)\n",
 411                pdimm->rank_density, pdimm->rank_density / 0x100000);
 412         printf("capacity = %llu bytes (%llu megabytes)\n",
 413                pdimm->capacity, pdimm->capacity / 0x100000);
 414         printf("burst_lengths_bitmask = %02X\n",
 415                pdimm->burst_lengths_bitmask);
 416         printf("base_addresss = %llu (%08llX %08llX)\n",
 417                pdimm->base_address,
 418                (pdimm->base_address >> 32),
 419                pdimm->base_address & 0xFFFFFFFF);
 420         print_option_table(options, n_opts, pdimm);
 421 }
 422
 423 static void print_lowest_common_dimm_parameters(
 424                 const common_timing_params_t *plcd_dimm_params)
 425 {
 426         static const struct options_string options[] = {
 427 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 428                 COMMON_TIMING(taamin_ps),
 429 #endif
 430                 COMMON_TIMING(trcd_ps),
 431                 COMMON_TIMING(trp_ps),
 432                 COMMON_TIMING(tras_ps),
 433 #ifdef CONFIG_SYS_FSL_DDR4
 434                 COMMON_TIMING(trfc1_ps),
 435                 COMMON_TIMING(trfc2_ps),
 436                 COMMON_TIMING(trfc4_ps),
 437                 COMMON_TIMING(trrds_ps),
 438                 COMMON_TIMING(trrdl_ps),
 439                 COMMON_TIMING(tccdl_ps),
 440 #else
 441                 COMMON_TIMING(twtr_ps),
 442                 COMMON_TIMING(trfc_ps),
 443                 COMMON_TIMING(trrd_ps),
 444                 COMMON_TIMING(trtp_ps),
 445 #endif
 446                 COMMON_TIMING(twr_ps),
 447                 COMMON_TIMING(trc_ps),
 448                 COMMON_TIMING(refresh_rate_ps),
 449                 COMMON_TIMING(extended_op_srt),
 450 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
 451                 COMMON_TIMING(tis_ps),
 452                 COMMON_TIMING(tih_ps),
 453                 COMMON_TIMING(tds_ps),
 454                 COMMON_TIMING(tdh_ps),
 455                 COMMON_TIMING(tdqsq_max_ps),
 456                 COMMON_TIMING(tqhs_ps),
 457 #endif
 458                 COMMON_TIMING(lowest_common_spd_caslat),
 459                 COMMON_TIMING(highest_common_derated_caslat),
 460                 COMMON_TIMING(additive_latency),
 461                 COMMON_TIMING(ndimms_present),
 462                 COMMON_TIMING(all_dimms_registered),
 463                 COMMON_TIMING(all_dimms_unbuffered),
 464                 COMMON_TIMING(all_dimms_ecc_capable),
 465         };
 466         static const unsigned int n_opts = ARRAY_SIZE(options);
 467
 468         /* Clock frequencies */
 469         printf("tckmin_x_ps = %u (%u MHz)\n",
 470                plcd_dimm_params->tckmin_x_ps,
 471                picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
 472         printf("tckmax_ps = %u (%u MHz)\n",
 473                plcd_dimm_params->tckmax_ps,
 474                picos_to_mhz(plcd_dimm_params->tckmax_ps));
 475         printf("all_dimms_burst_lengths_bitmask = %02X\n",
 476                plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 477
 478         print_option_table(options, n_opts, plcd_dimm_params);
 479
 480         printf("total_mem = %llu (%llu megabytes)\n",
 481                plcd_dimm_params->total_mem,
 482                plcd_dimm_params->total_mem / 0x100000);
 483         printf("base_address = %llu (%llu megabytes)\n",
 484                plcd_dimm_params->base_address,
 485                plcd_dimm_params->base_address / 0x100000);
 486 }
 487
 488 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
 489         sizeof((memctl_options_t *)0)->x, 0}
 490 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
 491         offsetof(memctl_options_t, cs_local_opts[x].y), \
 492         sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
 493
 494 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 495                            unsigned int ctl_num,
 496                            const char *optname_str,
 497                            const char *value_str)
 498 {
 499         memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
 500         /*
 501          * This array all on the stack and *computed* each time this
 502          * function is rung.
 503          */
 504         static const struct options_string options[] = {
 505                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 506                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 507 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 508                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 509                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 510 #endif
 511 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 512                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 513                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 514 #endif
 515 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 516                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 517                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 518 #endif
 519 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 520                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 521                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 522 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 523                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 524                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 525 #endif
 526 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 527                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 528                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 529 #endif
 530 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 531                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 532                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 533 #endif
 534 #endif
 535                 CTRL_OPTIONS(memctl_interleaving),
 536                 CTRL_OPTIONS(memctl_interleaving_mode),
 537                 CTRL_OPTIONS(ba_intlv_ctl),
 538                 CTRL_OPTIONS(ecc_mode),
 539                 CTRL_OPTIONS(ecc_init_using_memctl),
 540                 CTRL_OPTIONS(dqs_config),
 541                 CTRL_OPTIONS(self_refresh_in_sleep),
 542                 CTRL_OPTIONS(dynamic_power),
 543                 CTRL_OPTIONS(data_bus_width),
 544                 CTRL_OPTIONS(burst_length),
 545                 CTRL_OPTIONS(cas_latency_override),
 546                 CTRL_OPTIONS(cas_latency_override_value),
 547                 CTRL_OPTIONS(use_derated_caslat),
 548                 CTRL_OPTIONS(additive_latency_override),
 549                 CTRL_OPTIONS(additive_latency_override_value),
 550                 CTRL_OPTIONS(clk_adjust),
 551                 CTRL_OPTIONS(cpo_override),
 552                 CTRL_OPTIONS(write_data_delay),
 553                 CTRL_OPTIONS(half_strength_driver_enable),
 554
 555                 /*
 556                  * These can probably be changed to 2T_EN and 3T_EN
 557                  * (using a leading numerical character) without problem
 558                  */
 559                 CTRL_OPTIONS(twot_en),
 560                 CTRL_OPTIONS(threet_en),
 561                 CTRL_OPTIONS(ap_en),
 562                 CTRL_OPTIONS(x4_en),
 563                 CTRL_OPTIONS(bstopre),
 564                 CTRL_OPTIONS(wrlvl_override),
 565                 CTRL_OPTIONS(wrlvl_sample),
 566                 CTRL_OPTIONS(wrlvl_start),
 567                 CTRL_OPTIONS(cswl_override),
 568                 CTRL_OPTIONS(rcw_override),
 569                 CTRL_OPTIONS(rcw_1),
 570                 CTRL_OPTIONS(rcw_2),
 571                 CTRL_OPTIONS(ddr_cdr1),
 572                 CTRL_OPTIONS(ddr_cdr2),
 573                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 574                 CTRL_OPTIONS(trwt_override),
 575                 CTRL_OPTIONS(trwt),
 576                 CTRL_OPTIONS(rtt_override),
 577                 CTRL_OPTIONS(rtt_override_value),
 578                 CTRL_OPTIONS(rtt_wr_override_value),
 579         };
 580
 581         static const unsigned int n_opts = ARRAY_SIZE(options);
 582
 583         if (handle_option_table(options, n_opts, p,
 584                                         optname_str, value_str))
 585                 return;
 586
 587         printf("couldn't find option string %s\n", optname_str);
 588 }
 589
 590 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
 591         sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
 592 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
 593         offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
 594         sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
 595
 596 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 597 {
 598         unsigned int i;
 599         static const struct options_string options[] = {
 600                 CFG_REGS_CS(0, bnds),
 601                 CFG_REGS_CS(0, config),
 602                 CFG_REGS_CS(0, config_2),
 603 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 604                 CFG_REGS_CS(1, bnds),
 605                 CFG_REGS_CS(1, config),
 606                 CFG_REGS_CS(1, config_2),
 607 #endif
 608 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 609                 CFG_REGS_CS(2, bnds),
 610                 CFG_REGS_CS(2, config),
 611                 CFG_REGS_CS(2, config_2),
 612 #endif
 613 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 614                 CFG_REGS_CS(3, bnds),
 615                 CFG_REGS_CS(3, config),
 616                 CFG_REGS_CS(3, config_2),
 617 #endif
 618                 CFG_REGS(timing_cfg_3),
 619                 CFG_REGS(timing_cfg_0),
 620                 CFG_REGS(timing_cfg_1),
 621                 CFG_REGS(timing_cfg_2),
 622                 CFG_REGS(ddr_sdram_cfg),
 623                 CFG_REGS(ddr_sdram_cfg_2),
 624                 CFG_REGS(ddr_sdram_cfg_3),
 625                 CFG_REGS(ddr_sdram_mode),
 626                 CFG_REGS(ddr_sdram_mode_2),
 627                 CFG_REGS(ddr_sdram_mode_3),
 628                 CFG_REGS(ddr_sdram_mode_4),
 629                 CFG_REGS(ddr_sdram_mode_5),
 630                 CFG_REGS(ddr_sdram_mode_6),
 631                 CFG_REGS(ddr_sdram_mode_7),
 632                 CFG_REGS(ddr_sdram_mode_8),
 633 #ifdef CONFIG_SYS_FSL_DDR4
 634                 CFG_REGS(ddr_sdram_mode_9),
 635                 CFG_REGS(ddr_sdram_mode_10),
 636                 CFG_REGS(ddr_sdram_mode_11),
 637                 CFG_REGS(ddr_sdram_mode_12),
 638                 CFG_REGS(ddr_sdram_mode_13),
 639                 CFG_REGS(ddr_sdram_mode_14),
 640                 CFG_REGS(ddr_sdram_mode_15),
 641                 CFG_REGS(ddr_sdram_mode_16),
 642 #endif
 643                 CFG_REGS(ddr_sdram_interval),
 644                 CFG_REGS(ddr_data_init),
 645                 CFG_REGS(ddr_sdram_clk_cntl),
 646                 CFG_REGS(ddr_init_addr),
 647                 CFG_REGS(ddr_init_ext_addr),
 648                 CFG_REGS(timing_cfg_4),
 649                 CFG_REGS(timing_cfg_5),
 650 #ifdef CONFIG_SYS_FSL_DDR4
 651                 CFG_REGS(timing_cfg_6),
 652                 CFG_REGS(timing_cfg_7),
 653                 CFG_REGS(timing_cfg_8),
 654                 CFG_REGS(timing_cfg_9),
 655 #endif
 656                 CFG_REGS(ddr_zq_cntl),
 657                 CFG_REGS(ddr_wrlvl_cntl),
 658                 CFG_REGS(ddr_wrlvl_cntl_2),
 659                 CFG_REGS(ddr_wrlvl_cntl_3),
 660                 CFG_REGS(ddr_sr_cntr),
 661                 CFG_REGS(ddr_sdram_rcw_1),
 662                 CFG_REGS(ddr_sdram_rcw_2),
 663                 CFG_REGS(ddr_cdr1),
 664                 CFG_REGS(ddr_cdr2),
 665                 CFG_REGS(dq_map_0),
 666                 CFG_REGS(dq_map_1),
 667                 CFG_REGS(dq_map_2),
 668                 CFG_REGS(dq_map_3),
 669                 CFG_REGS(err_disable),
 670                 CFG_REGS(err_int_en),
 671                 CFG_REGS(ddr_eor),
 672         };
 673         static const unsigned int n_opts = ARRAY_SIZE(options);
 674
 675         print_option_table(options, n_opts, ddr);
 676
 677         for (i = 0; i < 64; i++)
 678                 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
 679 }
 680
 681 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 682                         unsigned int ctrl_num,
 683                         const char *regname,
 684                         const char *value_str)
 685 {
 686         unsigned int i;
 687         fsl_ddr_cfg_regs_t *ddr;
 688         char buf[20];
 689         static const struct options_string options[] = {
 690                 CFG_REGS_CS(0, bnds),
 691                 CFG_REGS_CS(0, config),
 692                 CFG_REGS_CS(0, config_2),
 693 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 694                 CFG_REGS_CS(1, bnds),
 695                 CFG_REGS_CS(1, config),
 696                 CFG_REGS_CS(1, config_2),
 697 #endif
 698 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 699                 CFG_REGS_CS(2, bnds),
 700                 CFG_REGS_CS(2, config),
 701                 CFG_REGS_CS(2, config_2),
 702 #endif
 703 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 704                 CFG_REGS_CS(3, bnds),
 705                 CFG_REGS_CS(3, config),
 706                 CFG_REGS_CS(3, config_2),
 707 #endif
 708                 CFG_REGS(timing_cfg_3),
 709                 CFG_REGS(timing_cfg_0),
 710                 CFG_REGS(timing_cfg_1),
 711                 CFG_REGS(timing_cfg_2),
 712                 CFG_REGS(ddr_sdram_cfg),
 713                 CFG_REGS(ddr_sdram_cfg_2),
 714                 CFG_REGS(ddr_sdram_cfg_3),
 715                 CFG_REGS(ddr_sdram_mode),
 716                 CFG_REGS(ddr_sdram_mode_2),
 717                 CFG_REGS(ddr_sdram_mode_3),
 718                 CFG_REGS(ddr_sdram_mode_4),
 719                 CFG_REGS(ddr_sdram_mode_5),
 720                 CFG_REGS(ddr_sdram_mode_6),
 721                 CFG_REGS(ddr_sdram_mode_7),
 722                 CFG_REGS(ddr_sdram_mode_8),
 723 #ifdef CONFIG_SYS_FSL_DDR4
 724                 CFG_REGS(ddr_sdram_mode_9),
 725                 CFG_REGS(ddr_sdram_mode_10),
 726                 CFG_REGS(ddr_sdram_mode_11),
 727                 CFG_REGS(ddr_sdram_mode_12),
 728                 CFG_REGS(ddr_sdram_mode_13),
 729                 CFG_REGS(ddr_sdram_mode_14),
 730                 CFG_REGS(ddr_sdram_mode_15),
 731                 CFG_REGS(ddr_sdram_mode_16),
 732 #endif
 733                 CFG_REGS(ddr_sdram_interval),
 734                 CFG_REGS(ddr_data_init),
 735                 CFG_REGS(ddr_sdram_clk_cntl),
 736                 CFG_REGS(ddr_init_addr),
 737                 CFG_REGS(ddr_init_ext_addr),
 738                 CFG_REGS(timing_cfg_4),
 739                 CFG_REGS(timing_cfg_5),
 740 #ifdef CONFIG_SYS_FSL_DDR4
 741                 CFG_REGS(timing_cfg_6),
 742                 CFG_REGS(timing_cfg_7),
 743                 CFG_REGS(timing_cfg_8),
 744                 CFG_REGS(timing_cfg_9),
 745 #endif
 746                 CFG_REGS(ddr_zq_cntl),
 747                 CFG_REGS(ddr_wrlvl_cntl),
 748                 CFG_REGS(ddr_wrlvl_cntl_2),
 749                 CFG_REGS(ddr_wrlvl_cntl_3),
 750                 CFG_REGS(ddr_sr_cntr),
 751                 CFG_REGS(ddr_sdram_rcw_1),
 752                 CFG_REGS(ddr_sdram_rcw_2),
 753                 CFG_REGS(ddr_cdr1),
 754                 CFG_REGS(ddr_cdr2),
 755                 CFG_REGS(dq_map_0),
 756                 CFG_REGS(dq_map_1),
 757                 CFG_REGS(dq_map_2),
 758                 CFG_REGS(dq_map_3),
 759                 CFG_REGS(err_disable),
 760                 CFG_REGS(err_int_en),
 761                 CFG_REGS(ddr_sdram_rcw_2),
 762                 CFG_REGS(ddr_sdram_rcw_2),
 763                 CFG_REGS(ddr_eor),
 764         };
 765         static const unsigned int n_opts = ARRAY_SIZE(options);
 766
 767         debug("fsl_ddr_regs_edit: ctrl_num = %u, "
 768                 "regname = %s, value = %s\n",
 769                 ctrl_num, regname, value_str);
 770         if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
 771                 return;
 772
 773         ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
 774
 775         if (handle_option_table(options, n_opts, ddr, regname, value_str))
 776                 return;
 777
 778         for (i = 0; i < 64; i++) {
 779                 unsigned int value = simple_strtoul(value_str, NULL, 0);
 780                 sprintf(buf, "debug_%u", i + 1);
 781                 if (strcmp(buf, regname) == 0) {
 782                         ddr->debug[i] = value;
 783                         return;
 784                 }
 785         }
 786         printf("Error: couldn't find register string %s\n", regname);
 787 }
 788
 789 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
 790         sizeof((memctl_options_t *)0)->x, 1}
 791
 792 static void print_memctl_options(const memctl_options_t *popts)
 793 {
 794         static const struct options_string options[] = {
 795                 CTRL_OPTIONS_CS(0, odt_rd_cfg),
 796                 CTRL_OPTIONS_CS(0, odt_wr_cfg),
 797 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 798                 CTRL_OPTIONS_CS(1, odt_rd_cfg),
 799                 CTRL_OPTIONS_CS(1, odt_wr_cfg),
 800 #endif
 801 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 802                 CTRL_OPTIONS_CS(2, odt_rd_cfg),
 803                 CTRL_OPTIONS_CS(2, odt_wr_cfg),
 804 #endif
 805 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 806                 CTRL_OPTIONS_CS(3, odt_rd_cfg),
 807                 CTRL_OPTIONS_CS(3, odt_wr_cfg),
 808 #endif
 809 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 810                 CTRL_OPTIONS_CS(0, odt_rtt_norm),
 811                 CTRL_OPTIONS_CS(0, odt_rtt_wr),
 812 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 813                 CTRL_OPTIONS_CS(1, odt_rtt_norm),
 814                 CTRL_OPTIONS_CS(1, odt_rtt_wr),
 815 #endif
 816 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 817                 CTRL_OPTIONS_CS(2, odt_rtt_norm),
 818                 CTRL_OPTIONS_CS(2, odt_rtt_wr),
 819 #endif
 820 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 821                 CTRL_OPTIONS_CS(3, odt_rtt_norm),
 822                 CTRL_OPTIONS_CS(3, odt_rtt_wr),
 823 #endif
 824 #endif
 825                 CTRL_OPTIONS(memctl_interleaving),
 826                 CTRL_OPTIONS(memctl_interleaving_mode),
 827                 CTRL_OPTIONS_HEX(ba_intlv_ctl),
 828                 CTRL_OPTIONS(ecc_mode),
 829                 CTRL_OPTIONS(ecc_init_using_memctl),
 830                 CTRL_OPTIONS(dqs_config),
 831                 CTRL_OPTIONS(self_refresh_in_sleep),
 832                 CTRL_OPTIONS(dynamic_power),
 833                 CTRL_OPTIONS(data_bus_width),
 834                 CTRL_OPTIONS(burst_length),
 835                 CTRL_OPTIONS(cas_latency_override),
 836                 CTRL_OPTIONS(cas_latency_override_value),
 837                 CTRL_OPTIONS(use_derated_caslat),
 838                 CTRL_OPTIONS(additive_latency_override),
 839                 CTRL_OPTIONS(additive_latency_override_value),
 840                 CTRL_OPTIONS(clk_adjust),
 841                 CTRL_OPTIONS(cpo_override),
 842                 CTRL_OPTIONS(write_data_delay),
 843                 CTRL_OPTIONS(half_strength_driver_enable),
 844                 /*
 845                  * These can probably be changed to 2T_EN and 3T_EN
 846                  * (using a leading numerical character) without problem
 847                  */
 848                 CTRL_OPTIONS(twot_en),
 849                 CTRL_OPTIONS(threet_en),
 850                 CTRL_OPTIONS(registered_dimm_en),
 851                 CTRL_OPTIONS(mirrored_dimm),
 852                 CTRL_OPTIONS(ap_en),
 853                 CTRL_OPTIONS(x4_en),
 854                 CTRL_OPTIONS(bstopre),
 855                 CTRL_OPTIONS(wrlvl_override),
 856                 CTRL_OPTIONS(wrlvl_sample),
 857                 CTRL_OPTIONS(wrlvl_start),
 858                 CTRL_OPTIONS_HEX(cswl_override),
 859                 CTRL_OPTIONS(rcw_override),
 860                 CTRL_OPTIONS(rcw_1),
 861                 CTRL_OPTIONS(rcw_2),
 862                 CTRL_OPTIONS_HEX(ddr_cdr1),
 863                 CTRL_OPTIONS_HEX(ddr_cdr2),
 864                 CTRL_OPTIONS(tfaw_window_four_activates_ps),
 865                 CTRL_OPTIONS(trwt_override),
 866                 CTRL_OPTIONS(trwt),
 867                 CTRL_OPTIONS(rtt_override),
 868                 CTRL_OPTIONS(rtt_override_value),
 869                 CTRL_OPTIONS(rtt_wr_override_value),
 870         };
 871         static const unsigned int n_opts = ARRAY_SIZE(options);
 872
 873         print_option_table(options, n_opts, popts);
 874 }
 875
 876 #ifdef CONFIG_SYS_FSL_DDR1
 877 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
 878 {
 879         unsigned int i;
 880
 881         printf("%-3d    : %02x %s\n", 0, spd->info_size,
 882                " spd->info_size,   *  0 # bytes written into serial memory *");
 883         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
 884                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
 885         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
 886                " spd->mem_type,    *  2 Fundamental memory type *");
 887         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
 888                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
 889         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
 890                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
 891         printf("%-3d    : %02x %s\n", 5, spd->nrows,
 892                " spd->nrows        *  5 # of DIMM Banks *");
 893         printf("%-3d    : %02x %s\n", 6, spd->dataw_lsb,
 894                " spd->dataw_lsb,   *  6 Data Width lsb of this assembly *");
 895         printf("%-3d    : %02x %s\n", 7, spd->dataw_msb,
 896                " spd->dataw_msb,   *  7 Data Width msb of this assembly *");
 897         printf("%-3d    : %02x %s\n", 8, spd->voltage,
 898                " spd->voltage,     *  8 Voltage intf std of this assembly *");
 899         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
 900                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
 901         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
 902                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
 903         printf("%-3d    : %02x %s\n", 11, spd->config,
 904                " spd->config,      * 11 DIMM Configuration type *");
 905         printf("%-3d    : %02x %s\n", 12, spd->refresh,
 906                " spd->refresh,     * 12 Refresh Rate/Type *");
 907         printf("%-3d    : %02x %s\n", 13, spd->primw,
 908                " spd->primw,       * 13 Primary SDRAM Width *");
 909         printf("%-3d    : %02x %s\n", 14, spd->ecw,
 910                " spd->ecw,         * 14 Error Checking SDRAM width *");
 911         printf("%-3d    : %02x %s\n", 15, spd->min_delay,
 912                " spd->min_delay,   * 15 Back to Back Random Access *");
 913         printf("%-3d    : %02x %s\n", 16, spd->burstl,
 914                " spd->burstl,      * 16 Burst Lengths Supported *");
 915         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
 916                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
 917         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
 918                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
 919         printf("%-3d    : %02x %s\n", 19, spd->cs_lat,
 920                " spd->cs_lat,      * 19 Chip Select Latency *");
 921         printf("%-3d    : %02x %s\n", 20, spd->write_lat,
 922                " spd->write_lat,   * 20 Write Latency/Recovery *");
 923         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
 924                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
 925         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
 926                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
 927         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
 928                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
 929         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
 930                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
 931         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
 932                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
 933         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
 934                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
 935         printf("%-3d    : %02x %s\n", 27, spd->trp,
 936                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
 937         printf("%-3d    : %02x %s\n", 28, spd->trrd,
 938                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
 939         printf("%-3d    : %02x %s\n", 29, spd->trcd,
 940                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
 941         printf("%-3d    : %02x %s\n", 30, spd->tras,
 942                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
 943         printf("%-3d    : %02x %s\n", 31, spd->bank_dens,
 944                " spd->bank_dens,   * 31 Density of each bank on module *");
 945         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
 946                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
 947         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
 948                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
 949         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
 950                " spd->data_setup,  * 34 Data signal input setup time *");
 951         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
 952                " spd->data_hold,   * 35 Data signal input hold time *");
 953         printf("%-3d    : %02x %s\n", 36, spd->res_36_40[0],
 954                " spd->res_36_40[0], * 36 Reserved / tWR *");
 955         printf("%-3d    : %02x %s\n", 37, spd->res_36_40[1],
 956                " spd->res_36_40[1], * 37 Reserved / tWTR *");
 957         printf("%-3d    : %02x %s\n", 38, spd->res_36_40[2],
 958                " spd->res_36_40[2], * 38 Reserved / tRTP *");
 959         printf("%-3d    : %02x %s\n", 39, spd->res_36_40[3],
 960                " spd->res_36_40[3], * 39 Reserved / mem_probe *");
 961         printf("%-3d    : %02x %s\n", 40, spd->res_36_40[4],
 962                " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
 963         printf("%-3d    : %02x %s\n", 41, spd->trc,
 964                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
 965         printf("%-3d    : %02x %s\n", 42, spd->trfc,
 966                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
 967         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
 968                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
 969         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
 970                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
 971         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
 972                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 973         printf("%-3d    : %02x %s\n", 46, spd->res_46,
 974                " spd->res_46,  * 46 Reserved/ PLL Relock time *");
 975         printf("%-3d    : %02x %s\n", 47, spd->dimm_height,
 976                " spd->dimm_height  * 47 SDRAM DIMM Height *");
 977
 978         printf("%-3d-%3d: ",  48, 61);
 979
 980         for (i = 0; i < 14; i++)
 981                 printf("%02x", spd->res_48_61[i]);
 982
 983         printf(" * 48-61 IDD in SPD and Reserved space *\n");
 984
 985         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
 986                " spd->spd_rev,     * 62 SPD Data Revision Code *");
 987         printf("%-3d    : %02x %s\n", 63, spd->cksum,
 988                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
 989         printf("%-3d-%3d: ",  64, 71);
 990
 991         for (i = 0; i < 8; i++)
 992                 printf("%02x", spd->mid[i]);
 993
 994         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
 995         printf("%-3d    : %02x %s\n", 72, spd->mloc,
 996                " spd->mloc,        * 72 Manufacturing Location *");
 997
 998         printf("%-3d-%3d: >>",  73, 90);
 999
1000         for (i = 0; i < 18; i++)
1001                 printf("%c", spd->mpart[i]);
1002
1003         printf("<<* 73 Manufacturer's Part Number *\n");
1004
1005         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1006                "* 91 Revision Code *");
1007         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1008                "* 93 Manufacturing Date *");
1009         printf("%-3d-%3d: ", 95, 98);
1010
1011         for (i = 0; i < 4; i++)
1012                 printf("%02x", spd->sernum[i]);
1013
1014         printf("* 95 Assembly Serial Number *\n");
1015
1016         printf("%-3d-%3d: ", 99, 127);
1017
1018         for (i = 0; i < 27; i++)
1019                 printf("%02x", spd->mspec[i]);
1020
1021         printf("* 99 Manufacturer Specific Data *\n");
1022 }
1023 #endif
1024
1025 #ifdef CONFIG_SYS_FSL_DDR2
1026 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1027 {
1028         unsigned int i;
1029
1030         printf("%-3d    : %02x %s\n", 0, spd->info_size,
1031                " spd->info_size,   *  0 # bytes written into serial memory *");
1032         printf("%-3d    : %02x %s\n", 1, spd->chip_size,
1033                " spd->chip_size,   *  1 Total # bytes of SPD memory device *");
1034         printf("%-3d    : %02x %s\n", 2, spd->mem_type,
1035                " spd->mem_type,    *  2 Fundamental memory type *");
1036         printf("%-3d    : %02x %s\n", 3, spd->nrow_addr,
1037                " spd->nrow_addr,   *  3 # of Row Addresses on this assembly *");
1038         printf("%-3d    : %02x %s\n", 4, spd->ncol_addr,
1039                " spd->ncol_addr,   *  4 # of Column Addrs on this assembly *");
1040         printf("%-3d    : %02x %s\n", 5, spd->mod_ranks,
1041                " spd->mod_ranks    *  5 # of Module Rows on this assembly *");
1042         printf("%-3d    : %02x %s\n", 6, spd->dataw,
1043                " spd->dataw,       *  6 Data Width of this assembly *");
1044         printf("%-3d    : %02x %s\n", 7, spd->res_7,
1045                " spd->res_7,       *  7 Reserved *");
1046         printf("%-3d    : %02x %s\n", 8, spd->voltage,
1047                " spd->voltage,     *  8 Voltage intf std of this assembly *");
1048         printf("%-3d    : %02x %s\n", 9, spd->clk_cycle,
1049                " spd->clk_cycle,   *  9 SDRAM Cycle time at CL=X *");
1050         printf("%-3d    : %02x %s\n", 10, spd->clk_access,
1051                " spd->clk_access,  * 10 SDRAM Access from Clock at CL=X *");
1052         printf("%-3d    : %02x %s\n", 11, spd->config,
1053                " spd->config,      * 11 DIMM Configuration type *");
1054         printf("%-3d    : %02x %s\n", 12, spd->refresh,
1055                " spd->refresh,     * 12 Refresh Rate/Type *");
1056         printf("%-3d    : %02x %s\n", 13, spd->primw,
1057                " spd->primw,       * 13 Primary SDRAM Width *");
1058         printf("%-3d    : %02x %s\n", 14, spd->ecw,
1059                " spd->ecw,         * 14 Error Checking SDRAM width *");
1060         printf("%-3d    : %02x %s\n", 15, spd->res_15,
1061                " spd->res_15,      * 15 Reserved *");
1062         printf("%-3d    : %02x %s\n", 16, spd->burstl,
1063                " spd->burstl,      * 16 Burst Lengths Supported *");
1064         printf("%-3d    : %02x %s\n", 17, spd->nbanks,
1065                " spd->nbanks,      * 17 # of Banks on Each SDRAM Device *");
1066         printf("%-3d    : %02x %s\n", 18, spd->cas_lat,
1067                " spd->cas_lat,     * 18 CAS# Latencies Supported *");
1068         printf("%-3d    : %02x %s\n", 19, spd->mech_char,
1069                " spd->mech_char,   * 19 Mechanical Characteristics *");
1070         printf("%-3d    : %02x %s\n", 20, spd->dimm_type,
1071                " spd->dimm_type,   * 20 DIMM type *");
1072         printf("%-3d    : %02x %s\n", 21, spd->mod_attr,
1073                " spd->mod_attr,    * 21 SDRAM Module Attributes *");
1074         printf("%-3d    : %02x %s\n", 22, spd->dev_attr,
1075                " spd->dev_attr,    * 22 SDRAM Device Attributes *");
1076         printf("%-3d    : %02x %s\n", 23, spd->clk_cycle2,
1077                " spd->clk_cycle2,  * 23 Min SDRAM Cycle time at CL=X-1 *");
1078         printf("%-3d    : %02x %s\n", 24, spd->clk_access2,
1079                " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1080         printf("%-3d    : %02x %s\n", 25, spd->clk_cycle3,
1081                " spd->clk_cycle3,  * 25 Min SDRAM Cycle time at CL=X-2 *");
1082         printf("%-3d    : %02x %s\n", 26, spd->clk_access3,
1083                " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1084         printf("%-3d    : %02x %s\n", 27, spd->trp,
1085                " spd->trp,         * 27 Min Row Precharge Time (tRP)*");
1086         printf("%-3d    : %02x %s\n", 28, spd->trrd,
1087                " spd->trrd,        * 28 Min Row Active to Row Active (tRRD) *");
1088         printf("%-3d    : %02x %s\n", 29, spd->trcd,
1089                " spd->trcd,        * 29 Min RAS to CAS Delay (tRCD) *");
1090         printf("%-3d    : %02x %s\n", 30, spd->tras,
1091                " spd->tras,        * 30 Minimum RAS Pulse Width (tRAS) *");
1092         printf("%-3d    : %02x %s\n", 31, spd->rank_dens,
1093                " spd->rank_dens,   * 31 Density of each rank on module *");
1094         printf("%-3d    : %02x %s\n", 32, spd->ca_setup,
1095                " spd->ca_setup,    * 32 Cmd + Addr signal input setup time *");
1096         printf("%-3d    : %02x %s\n", 33, spd->ca_hold,
1097                " spd->ca_hold,     * 33 Cmd and Addr signal input hold time *");
1098         printf("%-3d    : %02x %s\n", 34, spd->data_setup,
1099                " spd->data_setup,  * 34 Data signal input setup time *");
1100         printf("%-3d    : %02x %s\n", 35, spd->data_hold,
1101                " spd->data_hold,   * 35 Data signal input hold time *");
1102         printf("%-3d    : %02x %s\n", 36, spd->twr,
1103                " spd->twr,         * 36 Write Recovery time tWR *");
1104         printf("%-3d    : %02x %s\n", 37, spd->twtr,
1105                " spd->twtr,        * 37 Int write to read delay tWTR *");
1106         printf("%-3d    : %02x %s\n", 38, spd->trtp,
1107                " spd->trtp,        * 38 Int read to precharge delay tRTP *");
1108         printf("%-3d    : %02x %s\n", 39, spd->mem_probe,
1109                " spd->mem_probe,   * 39 Mem analysis probe characteristics *");
1110         printf("%-3d    : %02x %s\n", 40, spd->trctrfc_ext,
1111                " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1112         printf("%-3d    : %02x %s\n", 41, spd->trc,
1113                " spd->trc,         * 41 Min Active to Auto refresh time tRC *");
1114         printf("%-3d    : %02x %s\n", 42, spd->trfc,
1115                " spd->trfc,        * 42 Min Auto to Active period tRFC *");
1116         printf("%-3d    : %02x %s\n", 43, spd->tckmax,
1117                " spd->tckmax,      * 43 Max device cycle time tCKmax *");
1118         printf("%-3d    : %02x %s\n", 44, spd->tdqsq,
1119                " spd->tdqsq,       * 44 Max DQS to DQ skew *");
1120         printf("%-3d    : %02x %s\n", 45, spd->tqhs,
1121                " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
1122         printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
1123                " spd->pll_relock,  * 46 PLL Relock time *");
1124         printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
1125                " spd->t_casemax,    * 47 t_casemax *");
1126         printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
1127                " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
1128                "from Top (Case) to Ambient (Psi T-A DRAM) *");
1129         printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
1130                " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
1131                "Ambient due to Activate-Precharge/Mode Bits "
1132                "(DT0/Mode Bits) *)");
1133         printf("%-3d    : %02x %s\n", 50, spd->dt2n_dt2q,
1134                " spd->dt2n_dt2q,   * 50 DRAM Case Temperature Rise from "
1135                "Ambient due to Precharge/Quiet Standby "
1136                "(DT2N/DT2Q) *");
1137         printf("%-3d    : %02x %s\n", 51, spd->dt2p,
1138                " spd->dt2p,        * 51 DRAM Case Temperature Rise from "
1139                "Ambient due to Precharge Power-Down (DT2P) *");
1140         printf("%-3d    : %02x %s\n", 52, spd->dt3n,
1141                " spd->dt3n,        * 52 DRAM Case Temperature Rise from "
1142                "Ambient due to Active Standby (DT3N) *");
1143         printf("%-3d    : %02x %s\n", 53, spd->dt3pfast,
1144                " spd->dt3pfast,    * 53 DRAM Case Temperature Rise from "
1145                "Ambient due to Active Power-Down with Fast PDN Exit "
1146                "(DT3Pfast) *");
1147         printf("%-3d    : %02x %s\n", 54, spd->dt3pslow,
1148                " spd->dt3pslow,    * 54 DRAM Case Temperature Rise from "
1149                "Ambient due to Active Power-Down with Slow PDN Exit "
1150                "(DT3Pslow) *");
1151         printf("%-3d    : %02x %s\n", 55, spd->dt4r_dt4r4w,
1152                " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1153                "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1154                "(DT4R/DT4R4W Mode Bit) *");
1155         printf("%-3d    : %02x %s\n", 56, spd->dt5b,
1156                " spd->dt5b,        * 56 DRAM Case Temperature Rise from "
1157                "Ambient due to Burst Refresh (DT5B) *");
1158         printf("%-3d    : %02x %s\n", 57, spd->dt7,
1159                " spd->dt7,         * 57 DRAM Case Temperature Rise from "
1160                "Ambient due to Bank Interleave Reads with "
1161                "Auto-Precharge (DT7) *");
1162         printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
1163                " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
1164                " Top (Case) to Ambient (Psi T-A PLL) *");
1165         printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
1166                " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
1167                " from Top (Case) to Ambient (Psi T-A Register) *");
1168         printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
1169                " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1170                "Ambient due to PLL Active (DT PLL Active) *");
1171         printf("%-3d    : %02x %s\n", 61, spd->dtregact,
1172                " spd->dtregact,    "
1173                "* 61 Register Case Temperature Rise from Ambient due to "
1174                "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1175         printf("%-3d    : %02x %s\n", 62, spd->spd_rev,
1176                " spd->spd_rev,     * 62 SPD Data Revision Code *");
1177         printf("%-3d    : %02x %s\n", 63, spd->cksum,
1178                " spd->cksum,       * 63 Checksum for bytes 0-62 *");
1179
1180         printf("%-3d-%3d: ",  64, 71);
1181
1182         for (i = 0; i < 8; i++)
1183                 printf("%02x", spd->mid[i]);
1184
1185         printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1186
1187         printf("%-3d    : %02x %s\n", 72, spd->mloc,
1188                " spd->mloc,        * 72 Manufacturing Location *");
1189
1190         printf("%-3d-%3d: >>",  73, 90);
1191         for (i = 0; i < 18; i++)
1192                 printf("%c", spd->mpart[i]);
1193
1194
1195         printf("<<* 73 Manufacturer's Part Number *\n");
1196
1197         printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1198                "* 91 Revision Code *");
1199         printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1200                "* 93 Manufacturing Date *");
1201         printf("%-3d-%3d: ", 95, 98);
1202
1203         for (i = 0; i < 4; i++)
1204                 printf("%02x", spd->sernum[i]);
1205
1206         printf("* 95 Assembly Serial Number *\n");
1207
1208         printf("%-3d-%3d: ", 99, 127);
1209         for (i = 0; i < 27; i++)
1210                 printf("%02x", spd->mspec[i]);
1211
1212
1213         printf("* 99 Manufacturer Specific Data *\n");
1214 }
1215 #endif
1216
1217 #ifdef CONFIG_SYS_FSL_DDR3
1218 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1219 {
1220         unsigned int i;
1221
1222         /* General Section: Bytes 0-59 */
1223
1224 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1225 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1226         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1227
1228         PRINT_NXS(0, spd->info_size_crc,
1229                 "info_size_crc  bytes written into serial memory, "
1230                 "CRC coverage");
1231         PRINT_NXS(1, spd->spd_rev,
1232                 "spd_rev        SPD Revision");
1233         PRINT_NXS(2, spd->mem_type,
1234                 "mem_type       Key Byte / DRAM Device Type");
1235         PRINT_NXS(3, spd->module_type,
1236                 "module_type    Key Byte / Module Type");
1237         PRINT_NXS(4, spd->density_banks,
1238                 "density_banks  SDRAM Density and Banks");
1239         PRINT_NXS(5, spd->addressing,
1240                 "addressing     SDRAM Addressing");
1241         PRINT_NXS(6, spd->module_vdd,
1242                 "module_vdd     Module Nominal Voltage, VDD");
1243         PRINT_NXS(7, spd->organization,
1244                 "organization   Module Organization");
1245         PRINT_NXS(8, spd->bus_width,
1246                 "bus_width      Module Memory Bus Width");
1247         PRINT_NXS(9, spd->ftb_div,
1248                 "ftb_div        Fine Timebase (FTB) Dividend / Divisor");
1249         PRINT_NXS(10, spd->mtb_dividend,
1250                 "mtb_dividend   Medium Timebase (MTB) Dividend");
1251         PRINT_NXS(11, spd->mtb_divisor,
1252                 "mtb_divisor    Medium Timebase (MTB) Divisor");
1253         PRINT_NXS(12, spd->tck_min,
1254                   "tck_min        SDRAM Minimum Cycle Time");
1255         PRINT_NXS(13, spd->res_13,
1256                 "res_13         Reserved");
1257         PRINT_NXS(14, spd->caslat_lsb,
1258                 "caslat_lsb     CAS Latencies Supported, LSB");
1259         PRINT_NXS(15, spd->caslat_msb,
1260                 "caslat_msb     CAS Latencies Supported, MSB");
1261         PRINT_NXS(16, spd->taa_min,
1262                   "taa_min        Min CAS Latency Time");
1263         PRINT_NXS(17, spd->twr_min,
1264                   "twr_min        Min Write REcovery Time");
1265         PRINT_NXS(18, spd->trcd_min,
1266                   "trcd_min       Min RAS# to CAS# Delay Time");
1267         PRINT_NXS(19, spd->trrd_min,
1268                   "trrd_min       Min Row Active to Row Active Delay Time");
1269         PRINT_NXS(20, spd->trp_min,
1270                   "trp_min        Min Row Precharge Delay Time");
1271         PRINT_NXS(21, spd->tras_trc_ext,
1272                   "tras_trc_ext   Upper Nibbles for tRAS and tRC");
1273         PRINT_NXS(22, spd->tras_min_lsb,
1274                   "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
1275         PRINT_NXS(23, spd->trc_min_lsb,
1276                   "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1277         PRINT_NXS(24, spd->trfc_min_lsb,
1278                   "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
1279         PRINT_NXS(25, spd->trfc_min_msb,
1280                   "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
1281         PRINT_NXS(26, spd->twtr_min,
1282                   "twtr_min Min Internal Write to Read Command Delay Time");
1283         PRINT_NXS(27, spd->trtp_min,
1284                   "trtp_min "
1285                   "Min Internal Read to Precharge Command Delay Time");
1286         PRINT_NXS(28, spd->tfaw_msb,
1287                   "tfaw_msb       Upper Nibble for tFAW");
1288         PRINT_NXS(29, spd->tfaw_min,
1289                   "tfaw_min       Min Four Activate Window Delay Time");
1290         PRINT_NXS(30, spd->opt_features,
1291                 "opt_features   SDRAM Optional Features");
1292         PRINT_NXS(31, spd->therm_ref_opt,
1293                 "therm_ref_opt  SDRAM Thermal and Refresh Opts");
1294         PRINT_NXS(32, spd->therm_sensor,
1295                 "therm_sensor  SDRAM Thermal Sensor");
1296         PRINT_NXS(33, spd->device_type,
1297                 "device_type  SDRAM Device Type");
1298         PRINT_NXS(34, spd->fine_tck_min,
1299                   "fine_tck_min  Fine offset for tCKmin");
1300         PRINT_NXS(35, spd->fine_taa_min,
1301                   "fine_taa_min  Fine offset for tAAmin");
1302         PRINT_NXS(36, spd->fine_trcd_min,
1303                   "fine_trcd_min Fine offset for tRCDmin");
1304         PRINT_NXS(37, spd->fine_trp_min,
1305                   "fine_trp_min  Fine offset for tRPmin");
1306         PRINT_NXS(38, spd->fine_trc_min,
1307                   "fine_trc_min  Fine offset for tRCmin");
1308
1309         printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
1310
1311         for (i = 39; i <= 59; i++)
1312                 printf("%02x ", spd->res_39_59[i - 39]);
1313
1314         puts("\n");
1315
1316         switch (spd->module_type) {
1317         case 0x02:  /* UDIMM */
1318         case 0x03:  /* SO-DIMM */
1319         case 0x04:  /* Micro-DIMM */
1320         case 0x06:  /* Mini-UDIMM */
1321                 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1322                         "mod_height    (Unbuffered) Module Nominal Height");
1323                 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1324                         "mod_thickness (Unbuffered) Module Maximum Thickness");
1325                 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1326                         "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1327                 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1328                         "addr_mapping  (Unbuffered) Address mapping from "
1329                         "Edge Connector to DRAM");
1330                 break;
1331         case 0x01:  /* RDIMM */
1332         case 0x05:  /* Mini-RDIMM */
1333                 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1334                         "mod_height    (Registered) Module Nominal Height");
1335                 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1336                         "mod_thickness (Registered) Module Maximum Thickness");
1337                 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1338                         "ref_raw_card  (Registered) Reference Raw Card Used");
1339                 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1340                         "modu_attr     (Registered) DIMM Module Attributes");
1341                 PRINT_NXS(64, spd->mod_section.registered.thermal,
1342                         "thermal       (Registered) Thermal Heat "
1343                         "Spreader Solution");
1344                 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1345                         "reg_id_lo     (Registered) Register Manufacturer ID "
1346                         "Code, LSB");
1347                 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1348                         "reg_id_hi     (Registered) Register Manufacturer ID "
1349                         "Code, MSB");
1350                 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1351                         "reg_rev       (Registered) Register "
1352                         "Revision Number");
1353                 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1354                         "reg_type      (Registered) Register Type");
1355                 for (i = 69; i <= 76; i++) {
1356                         printf("%-3d    : %02x rcw[%d]\n", i,
1357                                 spd->mod_section.registered.rcw[i-69], i-69);
1358                 }
1359                 break;
1360         default:
1361                 /* Module-specific Section, Unsupported Module Type */
1362                 printf("%-3d-%3d: ", 60, 116);
1363
1364                 for (i = 60; i <= 116; i++)
1365                         printf("%02x", spd->mod_section.uc[i - 60]);
1366
1367                 break;
1368         }
1369
1370         /* Unique Module ID: Bytes 117-125 */
1371         PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1372         PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1373         PRINT_NXS(119, spd->mloc,     "Mfg Location");
1374         PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1375
1376         printf("%-3d-%3d: ", 122, 125);
1377
1378         for (i = 122; i <= 125; i++)
1379                 printf("%02x ", spd->sernum[i - 122]);
1380         printf("   Module Serial Number\n");
1381
1382         /* CRC: Bytes 126-127 */
1383         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1384
1385         /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1386         printf("%-3d-%3d: ", 128, 145);
1387         for (i = 128; i <= 145; i++)
1388                 printf("%02x ", spd->mpart[i - 128]);
1389         printf("   Mfg's Module Part Number\n");
1390
1391         PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1392                 "Module Revision code");
1393
1394         PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1395         PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1396
1397         printf("%-3d-%3d: ", 150, 175);
1398         for (i = 150; i <= 175; i++)
1399                 printf("%02x ", spd->msd[i - 150]);
1400         printf("   Mfg's Specific Data\n");
1401
1402         printf("%-3d-%3d: ", 176, 255);
1403         for (i = 176; i <= 255; i++)
1404                 printf("%02x", spd->cust[i - 176]);
1405         printf("   Mfg's Specific Data\n");
1406
1407 }
1408 #endif
1409
1410 #ifdef CONFIG_SYS_FSL_DDR4
1411 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1412 {
1413         unsigned int i;
1414
1415         /* General Section: Bytes 0-127 */
1416
1417 #define PRINT_NXS(x, y, z...) printf("%-3d    : %02x " z "\n", x, (u8)y);
1418 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1419         printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1420
1421         PRINT_NXS(0, spd->info_size_crc,
1422                   "info_size_crc  bytes written into serial memory, CRC coverage");
1423         PRINT_NXS(1, spd->spd_rev,
1424                   "spd_rev        SPD Revision");
1425         PRINT_NXS(2, spd->mem_type,
1426                   "mem_type       Key Byte / DRAM Device Type");
1427         PRINT_NXS(3, spd->module_type,
1428                   "module_type    Key Byte / Module Type");
1429         PRINT_NXS(4, spd->density_banks,
1430                   "density_banks  SDRAM Density and Banks");
1431         PRINT_NXS(5, spd->addressing,
1432                   "addressing     SDRAM Addressing");
1433         PRINT_NXS(6, spd->package_type,
1434                   "package_type   Package type");
1435         PRINT_NXS(7, spd->opt_feature,
1436                   "opt_feature    Optional features");
1437         PRINT_NXS(8, spd->thermal_ref,
1438                   "thermal_ref    Thermal and Refresh options");
1439         PRINT_NXS(9, spd->oth_opt_features,
1440                   "oth_opt_features Other SDRAM optional features");
1441         PRINT_NXS(10, spd->res_10,
1442                   "res_10         Reserved");
1443         PRINT_NXS(11, spd->module_vdd,
1444                   "module_vdd     Module Nominal Voltage, VDD");
1445         PRINT_NXS(12, spd->organization,
1446                   "organization Module Organization");
1447         PRINT_NXS(13, spd->bus_width,
1448                   "bus_width      Module Memory Bus Width");
1449         PRINT_NXS(14, spd->therm_sensor,
1450                   "therm_sensor   Module Thermal Sensor");
1451         PRINT_NXS(15, spd->ext_type,
1452                   "ext_type       Extended module type");
1453         PRINT_NXS(16, spd->res_16,
1454                   "res_16       Reserved");
1455         PRINT_NXS(17, spd->timebases,
1456                   "timebases    MTb and FTB");
1457         PRINT_NXS(18, spd->tck_min,
1458                   "tck_min      tCKAVGmin");
1459         PRINT_NXS(19, spd->tck_max,
1460                   "tck_max      TCKAVGmax");
1461         PRINT_NXS(20, spd->caslat_b1,
1462                   "caslat_b1    CAS latencies, 1st byte");
1463         PRINT_NXS(21, spd->caslat_b2,
1464                   "caslat_b2    CAS latencies, 2nd byte");
1465         PRINT_NXS(22, spd->caslat_b3,
1466                   "caslat_b3    CAS latencies, 3rd byte ");
1467         PRINT_NXS(23, spd->caslat_b4,
1468                   "caslat_b4    CAS latencies, 4th byte");
1469         PRINT_NXS(24, spd->taa_min,
1470                   "taa_min      Min CAS Latency Time");
1471         PRINT_NXS(25, spd->trcd_min,
1472                   "trcd_min     Min RAS# to CAS# Delay Time");
1473         PRINT_NXS(26, spd->trp_min,
1474                   "trp_min      Min Row Precharge Delay Time");
1475         PRINT_NXS(27, spd->tras_trc_ext,
1476                   "tras_trc_ext Upper Nibbles for tRAS and tRC");
1477         PRINT_NXS(28, spd->tras_min_lsb,
1478                   "tras_min_lsb tRASmin, lsb");
1479         PRINT_NXS(29, spd->trc_min_lsb,
1480                   "trc_min_lsb  tRCmin, lsb");
1481         PRINT_NXS(30, spd->trfc1_min_lsb,
1482                   "trfc1_min_lsb  Min Refresh Recovery Delay Time, LSB");
1483         PRINT_NXS(31, spd->trfc1_min_msb,
1484                   "trfc1_min_msb  Min Refresh Recovery Delay Time, MSB ");
1485         PRINT_NXS(32, spd->trfc2_min_lsb,
1486                   "trfc2_min_lsb  Min Refresh Recovery Delay Time, LSB");
1487         PRINT_NXS(33, spd->trfc2_min_msb,
1488                   "trfc2_min_msb  Min Refresh Recovery Delay Time, MSB");
1489         PRINT_NXS(34, spd->trfc4_min_lsb,
1490                   "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1491         PRINT_NXS(35, spd->trfc4_min_msb,
1492                   "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1493         PRINT_NXS(36, spd->tfaw_msb,
1494                   "tfaw_msb      Upper Nibble for tFAW");
1495         PRINT_NXS(37, spd->tfaw_min,
1496                   "tfaw_min      tFAW, lsb");
1497         PRINT_NXS(38, spd->trrds_min,
1498                   "trrds_min     tRRD_Smin, MTB");
1499         PRINT_NXS(39, spd->trrdl_min,
1500                   "trrdl_min     tRRD_Lmin, MTB");
1501         PRINT_NXS(40, spd->tccdl_min,
1502                   "tccdl_min     tCCS_Lmin, MTB");
1503
1504         printf("%-3d-%3d: ", 41, 59);  /* Reserved, General Section */
1505         for (i = 41; i <= 59; i++)
1506                 printf("%02x ", spd->res_41[i - 41]);
1507
1508         puts("\n");
1509         printf("%-3d-%3d: ", 60, 77);
1510         for (i = 60; i <= 77; i++)
1511                 printf("%02x ", spd->mapping[i - 60]);
1512         puts("   mapping[] Connector to SDRAM bit map\n");
1513
1514         PRINT_NXS(117, spd->fine_tccdl_min,
1515                   "fine_tccdl_min Fine offset for tCCD_Lmin");
1516         PRINT_NXS(118, spd->fine_trrdl_min,
1517                   "fine_trrdl_min Fine offset for tRRD_Lmin");
1518         PRINT_NXS(119, spd->fine_trrds_min,
1519                   "fine_trrds_min Fine offset for tRRD_Smin");
1520         PRINT_NXS(120, spd->fine_trc_min,
1521                   "fine_trc_min   Fine offset for tRCmin");
1522         PRINT_NXS(121, spd->fine_trp_min,
1523                   "fine_trp_min   Fine offset for tRPmin");
1524         PRINT_NXS(122, spd->fine_trcd_min,
1525                   "fine_trcd_min  Fine offset for tRCDmin");
1526         PRINT_NXS(123, spd->fine_taa_min,
1527                   "fine_taa_min   Fine offset for tAAmin");
1528         PRINT_NXS(124, spd->fine_tck_max,
1529                   "fine_tck_max   Fine offset for tCKAVGmax");
1530         PRINT_NXS(125, spd->fine_tck_min,
1531                   "fine_tck_min   Fine offset for tCKAVGmin");
1532
1533         /* CRC: Bytes 126-127 */
1534         PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], "  SPD CRC");
1535
1536         switch (spd->module_type) {
1537         case 0x02:  /* UDIMM */
1538         case 0x03:  /* SO-DIMM */
1539                 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1540                           "mod_height    (Unbuffered) Module Nominal Height");
1541                 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1542                           "mod_thickness (Unbuffered) Module Maximum Thickness");
1543                 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1544                           "ref_raw_card  (Unbuffered) Reference Raw Card Used");
1545                 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1546                           "addr_mapping  (Unbuffered) Address mapping from Edge Connector to DRAM");
1547                 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1548                             spd->mod_section.unbuffered.crc[1], "  Module CRC");
1549                 break;
1550         case 0x01:  /* RDIMM */
1551                 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1552                           "mod_height    (Registered) Module Nominal Height");
1553                 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1554                           "mod_thickness (Registered) Module Maximum Thickness");
1555                 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1556                           "ref_raw_card  (Registered) Reference Raw Card Used");
1557                 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1558                           "modu_attr     (Registered) DIMM Module Attributes");
1559                 PRINT_NXS(132, spd->mod_section.registered.thermal,
1560                           "thermal       (Registered) Thermal Heat Spreader Solution");
1561                 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1562                           "reg_id_lo     (Registered) Register Manufacturer ID Code, LSB");
1563                 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1564                           "reg_id_hi     (Registered) Register Manufacturer ID Code, MSB");
1565                 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1566                           "reg_rev       (Registered) Register Revision Number");
1567                 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1568                           "reg_map       (Registered) Address mapping");
1569                 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1570                             spd->mod_section.registered.crc[1], "  Module CRC");
1571                 break;
1572         case 0x04:  /* LRDIMM */
1573                 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1574                           "mod_height    (Loadreduced) Module Nominal Height");
1575                 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1576                           "mod_thickness (Loadreduced) Module Maximum Thickness");
1577                 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1578                           "ref_raw_card  (Loadreduced) Reference Raw Card Used");
1579                 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1580                           "modu_attr     (Loadreduced) DIMM Module Attributes");
1581                 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1582                           "thermal       (Loadreduced) Thermal Heat Spreader Solution");
1583                 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1584                           "reg_id_lo     (Loadreduced) Register Manufacturer ID Code, LSB");
1585                 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1586                           "reg_id_hi     (Loadreduced) Register Manufacturer ID Code, MSB");
1587                 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1588                           "reg_rev       (Loadreduced) Register Revision Number");
1589                 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1590                           "reg_map       (Loadreduced) Address mapping");
1591                 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1592                           "reg_drv       (Loadreduced) Reg output drive strength");
1593                 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1594                           "reg_drv_ck    (Loadreduced) Reg output drive strength for CK");
1595                 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1596                           "data_buf_rev  (Loadreduced) Data Buffer Revision Numbe");
1597                 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1598                           "vrefqe_r0     (Loadreduced) DRAM VrefDQ for Package Rank 0");
1599                 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1600                           "vrefqe_r1     (Loadreduced) DRAM VrefDQ for Package Rank 1");
1601                 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1602                           "vrefqe_r2     (Loadreduced) DRAM VrefDQ for Package Rank 2");
1603                 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1604                           "vrefqe_r3     (Loadreduced) DRAM VrefDQ for Package Rank 3");
1605                 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1606                           "data_intf     (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1607                 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1608                           "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1609                 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1610                           "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1611                 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1612                           "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1613                 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1614                           "dram_drv      (Loadreduced) DRAM Drive Strength");
1615                 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1616                           "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1617                 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1618                           "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1619                 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1620                           "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1621                 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1622                           "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1623                 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1624                           "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1625                 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1626                           "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1627                 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1628                             spd->mod_section.loadreduced.crc[1],
1629                             "  Module CRC");
1630                 break;
1631         default:
1632                 /* Module-specific Section, Unsupported Module Type */
1633                 printf("%-3d-%3d: ", 128, 255);
1634
1635                 for (i = 128; i <= 255; i++)
1636                         printf("%02x", spd->mod_section.uc[i - 128]);
1637
1638                 break;
1639         }
1640
1641         /* Unique Module ID: Bytes 320-383 */
1642         PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1643         PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1644         PRINT_NXS(322, spd->mloc,     "Mfg Location");
1645         PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1646
1647         printf("%-3d-%3d: ", 325, 328);
1648
1649         for (i = 325; i <= 328; i++)
1650                 printf("%02x ", spd->sernum[i - 325]);
1651         printf("   Module Serial Number\n");
1652
1653         printf("%-3d-%3d: ", 329, 348);
1654         for (i = 329; i <= 348; i++)
1655                 printf("%02x ", spd->mpart[i - 329]);
1656         printf("   Mfg's Module Part Number\n");
1657
1658         PRINT_NXS(349, spd->mrev, "Module Revision code");
1659         PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1660         PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1661         PRINT_NXS(352, spd->stepping, "DRAM stepping");
1662
1663         printf("%-3d-%3d: ", 353, 381);
1664         for (i = 353; i <= 381; i++)
1665                 printf("%02x ", spd->msd[i - 353]);
1666         printf("   Mfg's Specific Data\n");
1667 }
1668 #endif
1669
1670 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1671 {
1672 #if defined(CONFIG_SYS_FSL_DDR1)
1673         ddr1_spd_dump(spd);
1674 #elif defined(CONFIG_SYS_FSL_DDR2)
1675         ddr2_spd_dump(spd);
1676 #elif defined(CONFIG_SYS_FSL_DDR3)
1677         ddr3_spd_dump(spd);
1678 #elif defined(CONFIG_SYS_FSL_DDR4)
1679         ddr4_spd_dump(spd);
1680 #endif
1681 }
1682
1683 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1684                         unsigned int ctrl_mask,
1685                         unsigned int dimm_mask,
1686                         unsigned int do_mask)
1687 {
1688         unsigned int i, j, retval;
1689
1690         /* STEP 1:  DIMM SPD data */
1691         if (do_mask & STEP_GET_SPD) {
1692                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1693                         if (!(ctrl_mask & (1 << i)))
1694                                 continue;
1695
1696                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1697                                 if (!(dimm_mask & (1 << j)))
1698                                         continue;
1699
1700                                 printf("SPD info:  Controller=%u "
1701                                                 "DIMM=%u\n", i, j);
1702                                 generic_spd_dump(
1703                                         &(pinfo->spd_installed_dimms[i][j]));
1704                                 printf("\n");
1705                         }
1706                         printf("\n");
1707                 }
1708                 printf("\n");
1709         }
1710
1711         /* STEP 2:  DIMM Parameters */
1712         if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1713                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1714                         if (!(ctrl_mask & (1 << i)))
1715                                 continue;
1716                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1717                                 if (!(dimm_mask & (1 << j)))
1718                                         continue;
1719                                 printf("DIMM parameters:  Controller=%u "
1720                                                 "DIMM=%u\n", i, j);
1721                                 print_dimm_parameters(
1722                                         &(pinfo->dimm_params[i][j]));
1723                                 printf("\n");
1724                         }
1725                         printf("\n");
1726                 }
1727                 printf("\n");
1728         }
1729
1730         /* STEP 3:  Common Parameters */
1731         if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1732                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1733                         if (!(ctrl_mask & (1 << i)))
1734                                 continue;
1735                         printf("\"lowest common\" DIMM parameters:  "
1736                                         "Controller=%u\n", i);
1737                         print_lowest_common_dimm_parameters(
1738                                 &pinfo->common_timing_params[i]);
1739                         printf("\n");
1740                 }
1741                 printf("\n");
1742         }
1743
1744         /* STEP 4:  User Configuration Options */
1745         if (do_mask & STEP_GATHER_OPTS) {
1746                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1747                         if (!(ctrl_mask & (1 << i)))
1748                                 continue;
1749                         printf("User Config Options: Controller=%u\n", i);
1750                         print_memctl_options(&pinfo->memctl_opts[i]);
1751                         printf("\n");
1752                 }
1753                 printf("\n");
1754         }
1755
1756         /* STEP 5:  Address assignment */
1757         if (do_mask & STEP_ASSIGN_ADDRESSES) {
1758                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1759                         if (!(ctrl_mask & (1 << i)))
1760                                 continue;
1761                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1762                                 printf("Address Assignment: Controller=%u "
1763                                                 "DIMM=%u\n", i, j);
1764                                 printf("Don't have this functionality yet\n");
1765                         }
1766                         printf("\n");
1767                 }
1768                 printf("\n");
1769         }
1770
1771         /* STEP 6:  computed controller register values */
1772         if (do_mask & STEP_COMPUTE_REGS) {
1773                 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1774                         if (!(ctrl_mask & (1 << i)))
1775                                 continue;
1776                         printf("Computed Register Values: Controller=%u\n", i);
1777                         print_fsl_memctl_config_regs(
1778                                 &pinfo->fsl_ddr_config_reg[i]);
1779                         retval = check_fsl_memctl_config_regs(
1780                                 &pinfo->fsl_ddr_config_reg[i]);
1781                         if (retval) {
1782                                 printf("check_fsl_memctl_config_regs "
1783                                         "result = %u\n", retval);
1784                         }
1785                         printf("\n");
1786                 }
1787                 printf("\n");
1788         }
1789 }
1790
1791 struct data_strings {
1792         const char *data_name;
1793         unsigned int step_mask;
1794         unsigned int dimm_number_required;
1795 };
1796
1797 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1798
1799 static unsigned int fsl_ddr_parse_interactive_cmd(
1800         char **argv,
1801         int argc,
1802         unsigned int *pstep_mask,
1803         unsigned int *pctlr_mask,
1804         unsigned int *pdimm_mask,
1805         unsigned int *pdimm_number_required
1806          ) {
1807
1808         static const struct data_strings options[] = {
1809                 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1810                 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1811                 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1812                 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1813                 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1814                 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1815         };
1816         static const unsigned int n_opts = ARRAY_SIZE(options);
1817
1818         unsigned int i, j;
1819         unsigned int error = 0;
1820
1821         for (i = 1; i < argc; i++) {
1822                 unsigned int matched = 0;
1823
1824                 for (j = 0; j < n_opts; j++) {
1825                         if (strcmp(options[j].data_name, argv[i]) != 0)
1826                                 continue;
1827                         *pstep_mask |= options[j].step_mask;
1828                         *pdimm_number_required =
1829                                 options[j].dimm_number_required;
1830                         matched = 1;
1831                         break;
1832                 }
1833
1834                 if (matched)
1835                         continue;
1836
1837                 if (argv[i][0] == 'c') {
1838                         char c = argv[i][1];
1839                         if (isdigit(c))
1840                                 *pctlr_mask |= 1 << (c - '0');
1841                         continue;
1842                 }
1843
1844                 if (argv[i][0] == 'd') {
1845                         char c = argv[i][1];
1846                         if (isdigit(c))
1847                                 *pdimm_mask |= 1 << (c - '0');
1848                         continue;
1849                 }
1850
1851                 printf("unknown arg %s\n", argv[i]);
1852                 *pstep_mask = 0;
1853                 error = 1;
1854                 break;
1855         }
1856
1857         return error;
1858 }
1859
1860 int fsl_ddr_interactive_env_var_exists(void)
1861 {
1862         char buffer[CONFIG_SYS_CBSIZE];
1863
1864         if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1865                 return 1;
1866
1867         return 0;
1868 }
1869
1870 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1871 {
1872         unsigned long long ddrsize;
1873         const char *prompt = "FSL DDR>";
1874         char buffer[CONFIG_SYS_CBSIZE];
1875         char buffer2[CONFIG_SYS_CBSIZE];
1876         char *p = NULL;
1877         char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
1878         int argc;
1879         unsigned int next_step = STEP_GET_SPD;
1880         const char *usage = {
1881                 "commands:\n"
1882                 "print      print SPD and intermediate computed data\n"
1883                 "reset      reboot machine\n"
1884                 "recompute  reload SPD and options to default and recompute regs\n"
1885                 "edit       modify spd, parameter, or option\n"
1886                 "compute    recompute registers from current next_step to end\n"
1887                 "copy       copy parameters\n"
1888                 "next_step  shows current next_step\n"
1889                 "help       this message\n"
1890                 "go         program the memory controller and continue with u-boot\n"
1891         };
1892
1893         if (var_is_set) {
1894                 if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
1895                         p = buffer2;
1896                 } else {
1897                         var_is_set = 0;
1898                 }
1899         }
1900
1901         /*
1902          * The strategy for next_step is that it points to the next
1903          * step in the computation process that needs to be done.
1904          */
1905         while (1) {
1906                 if (var_is_set) {
1907                         char *pend = strchr(p, ';');
1908                         if (pend) {
1909                                 /* found command separator, copy sub-command */
1910                                 *pend = '\0';
1911                                 strcpy(buffer, p);
1912                                 p = pend + 1;
1913                         } else {
1914                                 /* separator not found, copy whole string */
1915                                 strcpy(buffer, p);
1916                                 p = NULL;
1917                                 var_is_set = 0;
1918                         }
1919                 } else {
1920                         /*
1921                          * No need to worry for buffer overflow here in
1922                          * this function;  cli_readline() maxes out at
1923                          * CFG_CBSIZE
1924                          */
1925                         cli_readline_into_buffer(prompt, buffer, 0);
1926                 }
1927                 argc = cli_simple_parse_line(buffer, argv);
1928                 if (argc == 0)
1929                         continue;
1930
1931
1932                 if (strcmp(argv[0], "help") == 0) {
1933                         puts(usage);
1934                         continue;
1935                 }
1936
1937                 if (strcmp(argv[0], "next_step") == 0) {
1938                         printf("next_step = 0x%02X (%s)\n",
1939                                next_step,
1940                                step_to_string(next_step));
1941                         continue;
1942                 }
1943
1944                 if (strcmp(argv[0], "copy") == 0) {
1945                         unsigned int error = 0;
1946                         unsigned int step_mask = 0;
1947                         unsigned int src_ctlr_mask = 0;
1948                         unsigned int src_dimm_mask = 0;
1949                         unsigned int dimm_number_required = 0;
1950                         unsigned int src_ctlr_num = 0;
1951                         unsigned int src_dimm_num = 0;
1952                         unsigned int dst_ctlr_num = -1;
1953                         unsigned int dst_dimm_num = -1;
1954                         unsigned int i, num_dest_parms;
1955
1956                         if (argc == 1) {
1957                                 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1958                                 continue;
1959                         }
1960
1961                         error = fsl_ddr_parse_interactive_cmd(
1962                                 argv, argc,
1963                                 &step_mask,
1964                                 &src_ctlr_mask,
1965                                 &src_dimm_mask,
1966                                 &dimm_number_required
1967                         );
1968
1969                         /* XXX: only dimm_number_required and step_mask will
1970                            be used by this function.  Parse the controller and
1971                            DIMM number separately because it is easier.  */
1972
1973                         if (error)
1974                                 continue;
1975
1976                         /* parse source destination controller / DIMM */
1977
1978                         num_dest_parms = dimm_number_required ? 2 : 1;
1979
1980                         for (i = 0; i < argc; i++) {
1981                                 if (argv[i][0] == 'c') {
1982                                         char c = argv[i][1];
1983                                         if (isdigit(c)) {
1984                                                 src_ctlr_num = (c - '0');
1985                                                 break;
1986                                         }
1987                                 }
1988                         }
1989
1990                         for (i = 0; i < argc; i++) {
1991                                 if (argv[i][0] == 'd') {
1992                                         char c = argv[i][1];
1993                                         if (isdigit(c)) {
1994                                                 src_dimm_num = (c - '0');
1995                                                 break;
1996                                         }
1997                                 }
1998                         }
1999
2000                         /* parse destination controller / DIMM */
2001
2002                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2003                                 if (argv[i][0] == 'c') {
2004                                         char c = argv[i][1];
2005                                         if (isdigit(c)) {
2006                                                 dst_ctlr_num = (c - '0');
2007                                                 break;
2008                                         }
2009                                 }
2010                         }
2011
2012                         for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2013                                 if (argv[i][0] == 'd') {
2014                                         char c = argv[i][1];
2015                                         if (isdigit(c)) {
2016                                                 dst_dimm_num = (c - '0');
2017                                                 break;
2018                                         }
2019                                 }
2020                         }
2021
2022                         /* TODO: validate inputs */
2023
2024                         debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2025                                 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2026
2027
2028                         switch (step_mask) {
2029
2030                         case STEP_GET_SPD:
2031                                 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2032                                         &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2033                                         sizeof(pinfo->spd_installed_dimms[0][0]));
2034                                 break;
2035
2036                         case STEP_COMPUTE_DIMM_PARMS:
2037                                 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2038                                         &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2039                                         sizeof(pinfo->dimm_params[0][0]));
2040                                 break;
2041
2042                         case STEP_COMPUTE_COMMON_PARMS:
2043                                 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2044                                         &(pinfo->common_timing_params[src_ctlr_num]),
2045                                         sizeof(pinfo->common_timing_params[0]));
2046                                 break;
2047
2048                         case STEP_GATHER_OPTS:
2049                                 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2050                                         &(pinfo->memctl_opts[src_ctlr_num]),
2051                                         sizeof(pinfo->memctl_opts[0]));
2052                                 break;
2053
2054                         /* someday be able to have addresses to copy addresses... */
2055
2056                         case STEP_COMPUTE_REGS:
2057                                 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2058                                         &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2059                                         sizeof(pinfo->memctl_opts[0]));
2060                                 break;
2061
2062                         default:
2063                                 printf("unexpected step_mask value\n");
2064                         }
2065
2066                         continue;
2067
2068                 }
2069
2070                 if (strcmp(argv[0], "edit") == 0) {
2071                         unsigned int error = 0;
2072                         unsigned int step_mask = 0;
2073                         unsigned int ctlr_mask = 0;
2074                         unsigned int dimm_mask = 0;
2075                         char *p_element = NULL;
2076                         char *p_value = NULL;
2077                         unsigned int dimm_number_required = 0;
2078                         unsigned int ctrl_num;
2079                         unsigned int dimm_num;
2080
2081                         if (argc == 1) {
2082                                 /* Only the element and value must be last */
2083                                 printf("edit <c#> <d#> "
2084                                         "<spd|dimmparms|commonparms|opts|"
2085                                         "addresses|regs> <element> <value>\n");
2086                                 printf("for spd, specify byte number for "
2087                                         "element\n");
2088                                 continue;
2089                         }
2090
2091                         error = fsl_ddr_parse_interactive_cmd(
2092                                 argv, argc - 2,
2093                                 &step_mask,
2094                                 &ctlr_mask,
2095                                 &dimm_mask,
2096                                 &dimm_number_required
2097                         );
2098
2099                         if (error)
2100                                 continue;
2101
2102
2103                         /* Check arguments */
2104
2105                         /* ERROR: If no steps were found */
2106                         if (step_mask == 0) {
2107                                 printf("Error: No valid steps were specified "
2108                                                 "in argument.\n");
2109                                 continue;
2110                         }
2111
2112                         /* ERROR: If multiple steps were found */
2113                         if (step_mask & (step_mask - 1)) {
2114                                 printf("Error: Multiple steps specified in "
2115                                                 "argument.\n");
2116                                 continue;
2117                         }
2118
2119                         /* ERROR: Controller not specified */
2120                         if (ctlr_mask == 0) {
2121                                 printf("Error: controller number not "
2122                                         "specified or no element and "
2123                                         "value specified\n");
2124                                 continue;
2125                         }
2126
2127                         if (ctlr_mask & (ctlr_mask - 1)) {
2128                                 printf("Error: multiple controllers "
2129                                                 "specified, %X\n", ctlr_mask);
2130                                 continue;
2131                         }
2132
2133                         /* ERROR: DIMM number not specified */
2134                         if (dimm_number_required && dimm_mask == 0) {
2135                                 printf("Error: DIMM number number not "
2136                                         "specified or no element and "
2137                                         "value specified\n");
2138                                 continue;
2139                         }
2140
2141                         if (dimm_mask & (dimm_mask - 1)) {
2142                                 printf("Error: multipled DIMMs specified\n");
2143                                 continue;
2144                         }
2145
2146                         p_element = argv[argc - 2];
2147                         p_value = argv[argc - 1];
2148
2149                         ctrl_num = __ilog2(ctlr_mask);
2150                         dimm_num = __ilog2(dimm_mask);
2151
2152                         switch (step_mask) {
2153                         case STEP_GET_SPD:
2154                                 {
2155                                         unsigned int element_num;
2156                                         unsigned int value;
2157
2158                                         element_num = simple_strtoul(p_element,
2159                                                                      NULL, 0);
2160                                         value = simple_strtoul(p_value,
2161                                                                NULL, 0);
2162                                         fsl_ddr_spd_edit(pinfo,
2163                                                                ctrl_num,
2164                                                                dimm_num,
2165                                                                element_num,
2166                                                                value);
2167                                         next_step = STEP_COMPUTE_DIMM_PARMS;
2168                                 }
2169                                 break;
2170
2171                         case STEP_COMPUTE_DIMM_PARMS:
2172                                 fsl_ddr_dimm_parameters_edit(
2173                                                  pinfo, ctrl_num, dimm_num,
2174                                                  p_element, p_value);
2175                                 next_step = STEP_COMPUTE_COMMON_PARMS;
2176                                 break;
2177
2178                         case STEP_COMPUTE_COMMON_PARMS:
2179                                 lowest_common_dimm_parameters_edit(pinfo,
2180                                                 ctrl_num, p_element, p_value);
2181                                 next_step = STEP_GATHER_OPTS;
2182                                 break;
2183
2184                         case STEP_GATHER_OPTS:
2185                                 fsl_ddr_options_edit(pinfo, ctrl_num,
2186                                                            p_element, p_value);
2187                                 next_step = STEP_ASSIGN_ADDRESSES;
2188                                 break;
2189
2190                         case STEP_ASSIGN_ADDRESSES:
2191                                 printf("editing of address assignment "
2192                                                 "not yet implemented\n");
2193                                 break;
2194
2195                         case STEP_COMPUTE_REGS:
2196                                 {
2197                                         fsl_ddr_regs_edit(pinfo,
2198                                                                 ctrl_num,
2199                                                                 p_element,
2200                                                                 p_value);
2201                                         next_step = STEP_PROGRAM_REGS;
2202                                 }
2203                                 break;
2204
2205                         default:
2206                                 printf("programming error\n");
2207                                 while (1)
2208                                         ;
2209                                 break;
2210                         }
2211                         continue;
2212                 }
2213
2214                 if (strcmp(argv[0], "reset") == 0) {
2215                         /*
2216                          * Reboot machine.
2217                          * Args don't seem to matter because this
2218                          * doesn't return
2219                          */
2220                         do_reset(NULL, 0, 0, NULL);
2221                         printf("Reset didn't work\n");
2222                 }
2223
2224                 if (strcmp(argv[0], "recompute") == 0) {
2225                         /*
2226                          * Recalculate everything, starting with
2227                          * loading SPD EEPROM from DIMMs
2228                          */
2229                         next_step = STEP_GET_SPD;
2230                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2231                         continue;
2232                 }
2233
2234                 if (strcmp(argv[0], "compute") == 0) {
2235                         /*
2236                          * Compute rest of steps starting at
2237                          * the current next_step/
2238                          */
2239                         ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2240                         continue;
2241                 }
2242
2243                 if (strcmp(argv[0], "print") == 0) {
2244                         unsigned int error = 0;
2245                         unsigned int step_mask = 0;
2246                         unsigned int ctlr_mask = 0;
2247                         unsigned int dimm_mask = 0;
2248                         unsigned int dimm_number_required = 0;
2249
2250                         if (argc == 1) {
2251                                 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2252                                   "[commonparms] [opts] [addresses] [regs]\n");
2253                                 continue;
2254                         }
2255
2256                         error = fsl_ddr_parse_interactive_cmd(
2257                                 argv, argc,
2258                                 &step_mask,
2259                                 &ctlr_mask,
2260                                 &dimm_mask,
2261                                 &dimm_number_required
2262                         );
2263
2264                         if (error)
2265                                 continue;
2266
2267                         /* If no particular controller was found, print all */
2268                         if (ctlr_mask == 0)
2269                                 ctlr_mask = 0xFF;
2270
2271                         /* If no particular dimm was found, print all dimms. */
2272                         if (dimm_mask == 0)
2273                                 dimm_mask = 0xFF;
2274
2275                         /* If no steps were found, print all steps. */
2276                         if (step_mask == 0)
2277                                 step_mask = STEP_ALL;
2278
2279                         fsl_ddr_printinfo(pinfo, ctlr_mask,
2280                                                 dimm_mask, step_mask);
2281                         continue;
2282                 }
2283
2284                 if (strcmp(argv[0], "go") == 0) {
2285                         if (next_step)
2286                                 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2287                         break;
2288                 }
2289
2290                 printf("unknown command %s\n", argv[0]);
2291         }
2292
2293         debug("end of memory = %llu\n", (u64)ddrsize);
2294
2295         return ddrsize;
2296 }