drivers/ddr/fsl/fsl_ddr_gen4.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2020 Freescale Semiconductor, Inc.
   4  * Copyright 2021 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <log.h>
  10 #include <asm/io.h>
  11 #include <fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13 #include <fsl_immap.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_errata.h>
  16 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  17         defined(CONFIG_ARM)
  18 #include <asm/arch/clock.h>
  19 #endif
  20 #include <linux/delay.h>
  21
  22 #define CTLR_INTLV_MASK 0x20000000
  23
  24 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  25         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  26 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  27 {
  28         int timeout = 1000;
  29
  30         ddr_out32(ptr, value);
  31
  32         while (ddr_in32(ptr) & bits) {
  33                 udelay(100);
  34                 timeout--;
  35         }
  36         if (timeout <= 0)
  37                 puts("Error: wait for clear timeout.\n");
  38 }
  39 #endif
  40
  41 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  42 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  43 #endif
  44
  45 /*
  46  * regs has the to-be-set values for DDR controller registers
  47  * ctrl_num is the DDR controller number
  48  * step: 0 goes through the initialization in one pass
  49  *       1 sets registers and returns before enabling controller
  50  *       2 resumes from step 1 and continues to initialize
  51  * Dividing the initialization to two steps to deassert DDR reset signal
  52  * to comply with JEDEC specs for RDIMMs.
  53  */
  54 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  55                              unsigned int ctrl_num, int step)
  56 {
  57         unsigned int i, bus_width;
  58         struct ccsr_ddr __iomem *ddr;
  59         u32 temp32;
  60         u32 total_gb_size_per_controller;
  61         int timeout = 0;
  62         int ddr_freq_for_timeout = 0;
  63         int mod_bnds = 0;
  64
  65 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  66         u32 mr6;
  67         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  68         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  69         u32 *vref_seq = vref_seq1;
  70 #endif
  71 #ifdef CONFIG_FSL_DDR_BIST
  72         u32 mtcr, err_detect, err_sbe;
  73         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  74 #endif
  75 #ifdef CONFIG_FSL_DDR_BIST
  76         char buffer[CONFIG_SYS_CBSIZE];
  77 #endif
  78 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
  79         (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
  80         defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
  81         defined(CONFIG_SYS_FSL_ERRATUM_A008109)
  82         u32 val32;
  83 #endif
  84 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  85         unsigned int ddr_freq;
  86 #endif
  87         switch (ctrl_num) {
  88         case 0:
  89                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  90                 break;
  91 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
  92         case 1:
  93                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  94                 break;
  95 #endif
  96 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
  97         case 2:
  98                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  99                 break;
 100 #endif
 101 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
 102         case 3:
 103                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
 104                 break;
 105 #endif
 106         default:
 107                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
 108                 return;
 109         }
 110         mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
 111
 112         if (step == 2)
 113                 goto step2;
 114
 115         /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
 116         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 117
 118         if (regs->ddr_eor)
 119                 ddr_out32(&ddr->eor, regs->ddr_eor);
 120
 121         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 122         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 123                 if (i == 0) {
 124                         if (mod_bnds) {
 125                                 debug("modified bnds\n");
 126                                 ddr_out32(&ddr->cs0_bnds,
 127                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 128                                 ddr_out32(&ddr->cs0_config,
 129                                           (regs->cs[i].config &
 130                                            ~CTLR_INTLV_MASK));
 131                         } else {
 132                                 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 133                                 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 134                         }
 135                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 136
 137                 } else if (i == 1) {
 138                         if (mod_bnds) {
 139                                 ddr_out32(&ddr->cs1_bnds,
 140                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 141                         } else {
 142                                 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 143                         }
 144                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 145                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 146
 147                 } else if (i == 2) {
 148                         if (mod_bnds) {
 149                                 ddr_out32(&ddr->cs2_bnds,
 150                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 151                         } else {
 152                                 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 153                         }
 154                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 155                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 156
 157                 } else if (i == 3) {
 158                         if (mod_bnds) {
 159                                 ddr_out32(&ddr->cs3_bnds,
 160                                           (regs->cs[i].bnds & 0xfffefffe) >> 1);
 161                         } else {
 162                                 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 163                         }
 164                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 165                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 166                 }
 167         }
 168
 169         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 170         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 171         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 172         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 173         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 174         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 175         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 176         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 177         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 178         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 179         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 180         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 181         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 182         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 183         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 184         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 185         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 186         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 187         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 188         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 189         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 190         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 191         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 192         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 193         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 194         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 195         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 196         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 197         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 198         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 199         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 200         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 201         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 202 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 203         ddr_out32(&ddr->sdram_interval,
 204                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 205 #else
 206         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 207 #endif
 208         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 209         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 210 #ifndef CONFIG_SYS_FSL_DDR_EMU
 211         /*
 212          * Skip these two registers if running on emulator
 213          * because emulator doesn't have skew between bytes.
 214          */
 215
 216         if (regs->ddr_wrlvl_cntl_2)
 217                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 218         if (regs->ddr_wrlvl_cntl_3)
 219                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 220 #endif
 221
 222         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 223         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 224         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 225         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 226         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 227         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 228         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 229 #ifdef CONFIG_DEEP_SLEEP
 230         if (is_warm_boot()) {
 231                 ddr_out32(&ddr->sdram_cfg_2,
 232                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 233                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 234                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 235
 236                 /* DRAM VRef will not be trained */
 237                 ddr_out32(&ddr->ddr_cdr2,
 238                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 239         } else
 240 #endif
 241         {
 242                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 243                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 244                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 245                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 246         }
 247
 248 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 249         /* part 1 of 2 */
 250         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 251                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 252                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 253                                   regs->ddr_sdram_rcw_2 & ~0xf0);
 254                 }
 255                 ddr_out32(&ddr->err_disable, regs->err_disable |
 256                           DDR_ERR_DISABLE_APED);
 257         }
 258 #else
 259         ddr_out32(&ddr->err_disable, regs->err_disable);
 260 #endif
 261         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 262         for (i = 0; i < 64; i++) {
 263                 if (regs->debug[i]) {
 264                         debug("Write to debug_%d as %08x\n",
 265                               i+1, regs->debug[i]);
 266                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 267                 }
 268         }
 269
 270 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 271         /* Part 1 of 2 */
 272         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 273                 /* Disable DRAM VRef training */
 274                 ddr_out32(&ddr->ddr_cdr2,
 275                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 276                 /* disable transmit bit deskew */
 277                 temp32 = ddr_in32(&ddr->debug[28]);
 278                 temp32 |= DDR_TX_BD_DIS;
 279                 ddr_out32(&ddr->debug[28], temp32);
 280                 ddr_out32(&ddr->debug[25], 0x9000);
 281         } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
 282                 /* Output enable forced off */
 283                 ddr_out32(&ddr->debug[37], 1 << 31);
 284                 /* Enable Vref training */
 285                 ddr_out32(&ddr->ddr_cdr2,
 286                           regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
 287         } else {
 288                 debug("Erratum A008511 doesn't apply.\n");
 289         }
 290 #endif
 291
 292 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
 293         defined(CONFIG_SYS_FSL_ERRATUM_A008511)
 294         /* Disable D_INIT */
 295         ddr_out32(&ddr->sdram_cfg_2,
 296                   regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 297 #endif
 298
 299 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 300         temp32 = ddr_in32(&ddr->debug[25]);
 301         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 302         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 303         ddr_out32(&ddr->debug[25], temp32);
 304 #endif
 305
 306 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 307         temp32 = get_ddr_freq(ctrl_num) / 1000000;
 308         if ((temp32 > 1900) && (temp32 < 2300)) {
 309                 temp32 = ddr_in32(&ddr->debug[28]);
 310                 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
 311         }
 312 #endif
 313         /*
 314          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 315          * deasserted. Clocks start when any chip select is enabled and clock
 316          * control register is set. Because all DDR components are connected to
 317          * one reset signal, this needs to be done in two steps. Step 1 is to
 318          * get the clocks started. Step 2 resumes after reset signal is
 319          * deasserted.
 320          */
 321         if (step == 1) {
 322                 udelay(200);
 323                 return;
 324         }
 325
 326 step2:
 327         /* Set, but do not enable the memory */
 328         temp32 = regs->ddr_sdram_cfg;
 329         temp32 &= ~(SDRAM_CFG_MEM_EN);
 330         ddr_out32(&ddr->sdram_cfg, temp32);
 331
 332         /*
 333          * 500 painful micro-seconds must elapse between
 334          * the DDR clock setup and the DDR config enable.
 335          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 336          * we choose the max, that is 500 us for all of case.
 337          */
 338         udelay(500);
 339         mb();
 340         isb();
 341
 342 #ifdef CONFIG_DEEP_SLEEP
 343         if (is_warm_boot()) {
 344                 /* enter self-refresh */
 345                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 346                 temp32 |= SDRAM_CFG2_FRC_SR;
 347                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 348                 /* do board specific memory setup */
 349                 board_mem_sleep_setup();
 350
 351                 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 352         } else
 353 #endif
 354                 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 355         /* Let the controller go */
 356         ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
 357         mb();
 358         isb();
 359
 360 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 361         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 362         /* Part 2 of 2 */
 363         timeout = 40;
 364         /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
 365         while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 366                (timeout > 0)) {
 367                 udelay(1000);
 368                 timeout--;
 369         }
 370         if (timeout <= 0) {
 371                 printf("Controler %d timeout, debug_2 = %x\n",
 372                        ctrl_num, ddr_in32(&ddr->debug[1]));
 373         }
 374
 375 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 376         /* This erraum only applies to verion 5.2.0 */
 377         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 378                 /* The vref setting sequence is different for range 2 */
 379                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 380                         vref_seq = vref_seq2;
 381
 382                 /* Set VREF */
 383                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 384                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 385                                 continue;
 386
 387                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 388                                  MD_CNTL_MD_EN                          |
 389                                  MD_CNTL_CS_SEL(i)                      |
 390                                  MD_CNTL_MD_SEL(6)                      |
 391                                  0x00200000;
 392                         temp32 = mr6 | vref_seq[0];
 393                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 394                                                 temp32, MD_CNTL_MD_EN);
 395                         udelay(1);
 396                         debug("MR6 = 0x%08x\n", temp32);
 397                         temp32 = mr6 | vref_seq[1];
 398                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 399                                                 temp32, MD_CNTL_MD_EN);
 400                         udelay(1);
 401                         debug("MR6 = 0x%08x\n", temp32);
 402                         temp32 = mr6 | vref_seq[2];
 403                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 404                                                 temp32, MD_CNTL_MD_EN);
 405                         udelay(1);
 406                         debug("MR6 = 0x%08x\n", temp32);
 407                 }
 408                 ddr_out32(&ddr->sdram_md_cntl, 0);
 409                 temp32 = ddr_in32(&ddr->debug[28]);
 410                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 411                 ddr_out32(&ddr->debug[28], temp32);
 412                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 413                 /* wait for idle */
 414                 timeout = 40;
 415                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 416                        (timeout > 0)) {
 417                         udelay(1000);
 418                         timeout--;
 419                 }
 420                 if (timeout <= 0) {
 421                         printf("Controler %d timeout, debug_2 = %x\n",
 422                                ctrl_num, ddr_in32(&ddr->debug[1]));
 423                 }
 424         }
 425 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 426
 427 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 428         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 429                 /* if it's RDIMM */
 430                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 431                         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 432                                 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 433                                         continue;
 434                                 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 435                                                         MD_CNTL_MD_EN |
 436                                                         MD_CNTL_CS_SEL(i) |
 437                                                         0x070000ed,
 438                                                         MD_CNTL_MD_EN);
 439                                 udelay(1);
 440                         }
 441                 }
 442
 443                 ddr_out32(&ddr->err_disable,
 444                           regs->err_disable & ~DDR_ERR_DISABLE_APED);
 445         }
 446 #endif
 447         /* Restore D_INIT */
 448         ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 449 #endif
 450
 451 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
 452         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 453 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 454 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 455         if (has_erratum_a008378()) {
 456                 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 457                     IS_DBI(regs->ddr_sdram_cfg_3)) {
 458                         val32 = ddr_in32(&ddr->debug[28]);
 459                         val32 |= (0x9 << 20);
 460                         ddr_out32(&ddr->debug[28], val32);
 461                 }
 462                 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
 463         }
 464 #endif
 465
 466 #if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
 467         val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
 468         ddr_out32(&ddr->sdram_cfg_2, val32);
 469
 470         val32 = ddr_in32(&ddr->debug[18]) | 0x2;
 471         ddr_out32(&ddr->debug[18], val32);
 472
 473         ddr_out32(&ddr->debug[28], 0x30000000);
 474         debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
 475 #endif
 476
 477 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 478         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 479         val32 = ddr_in32(&ddr->debug[28]);
 480         val32 &= 0xff0fff00;
 481         if (ddr_freq <= 1333)
 482                 val32 |= 0x0080006a;
 483         else if (ddr_freq <= 1600)
 484                 val32 |= 0x0070006f;
 485         else if (ddr_freq <= 1867)
 486                 val32 |= 0x00700076;
 487         else if (ddr_freq <= 2133)
 488                 val32 |= 0x0060007b;
 489
 490         ddr_out32(&ddr->debug[28], val32);
 491         debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
 492 #endif
 493
 494         total_gb_size_per_controller = 0;
 495         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 496                 if (!(regs->cs[i].config & 0x80000000))
 497                         continue;
 498                 total_gb_size_per_controller += 1 << (
 499                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 500                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 501                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 502                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 503                         ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
 504                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 505                         26);                    /* minus 26 (count of 64M) */
 506         }
 507         /*
 508          * total memory / bus width = transactions needed
 509          * transactions needed / data rate = seconds
 510          * to add plenty of buffer, double the time
 511          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 512          * Let's wait for 800ms
 513          */
 514         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 515                         >> SDRAM_CFG_DBW_SHIFT);
 516         ddr_freq_for_timeout = (get_ddr_freq(ctrl_num) >> 20) << 2;
 517         if (ddr_freq_for_timeout) {
 518                 timeout = ((total_gb_size_per_controller <<
 519                                        (6 - bus_width)) * 100 /
 520                                 ddr_freq_for_timeout);
 521         } else {
 522                 debug("Error in getting timeout.\n");
 523         }
 524         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 525         debug("total %d GB\n", total_gb_size_per_controller);
 526         debug("Need to wait up to %d * 10ms\n", timeout);
 527
 528         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 529         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 530                 (timeout >= 0)) {
 531                 udelay(10000);          /* throttle polling rate */
 532                 timeout--;
 533         }
 534
 535         if (timeout <= 0)
 536                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 537
 538         if (mod_bnds) {
 539                 debug("Reset to original bnds\n");
 540                 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
 541 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
 542                 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
 543 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
 544                 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
 545 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
 546                 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
 547 #endif
 548 #endif
 549 #endif
 550                 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
 551         }
 552
 553 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 554         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 555 #endif
 556
 557 #ifdef CONFIG_DEEP_SLEEP
 558         if (is_warm_boot()) {
 559                 /* exit self-refresh */
 560                 temp32 = ddr_in32(&ddr->sdram_cfg_2);
 561                 temp32 &= ~SDRAM_CFG2_FRC_SR;
 562                 ddr_out32(&ddr->sdram_cfg_2, temp32);
 563         }
 564 #endif
 565
 566 #ifdef CONFIG_FSL_DDR_BIST
 567 #define BIST_PATTERN1   0xFFFFFFFF
 568 #define BIST_PATTERN2   0x0
 569 #define BIST_CR         0x80010000
 570 #define BIST_CR_EN      0x80000000
 571 #define BIST_CR_STAT    0x00000001
 572         /* Perform build-in test on memory. Three-way interleaving is not yet
 573          * supported by this code. */
 574         if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 575                 puts("Running BIST test. This will take a while...");
 576                 cs0_config = ddr_in32(&ddr->cs0_config);
 577                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 578                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 579                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 580                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 581                 if (cs0_config & CTLR_INTLV_MASK) {
 582                         /* set bnds to non-interleaving */
 583                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 584                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 585                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 586                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 587                 }
 588                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 589                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 590                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 591                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 592                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 593                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 594                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 595                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 596                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 597                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 598                 mtcr = BIST_CR;
 599                 ddr_out32(&ddr->mtcr, mtcr);
 600                 timeout = 100;
 601                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 602                         mdelay(1000);
 603                         timeout--;
 604                         mtcr = ddr_in32(&ddr->mtcr);
 605                 }
 606                 if (timeout <= 0)
 607                         puts("Timeout\n");
 608                 else
 609                         puts("Done\n");
 610                 err_detect = ddr_in32(&ddr->err_detect);
 611                 err_sbe = ddr_in32(&ddr->err_sbe);
 612                 if (mtcr & BIST_CR_STAT) {
 613                         printf("BIST test failed on controller %d.\n",
 614                                ctrl_num);
 615                 }
 616                 if (err_detect || (err_sbe & 0xffff)) {
 617                         printf("ECC error detected on controller %d.\n",
 618                                ctrl_num);
 619                 }
 620
 621                 if (cs0_config & CTLR_INTLV_MASK) {
 622                         /* restore bnds registers */
 623                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 624                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 625                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 626                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 627                 }
 628         }
 629 #endif
 630 }