drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_errata.h>
  14
  15 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
  16         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
  17 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  18 {
  19         int timeout = 1000;
  20
  21         ddr_out32(ptr, value);
  22
  23         while (ddr_in32(ptr) & bits) {
  24                 udelay(100);
  25                 timeout--;
  26         }
  27         if (timeout <= 0)
  28                 puts("Error: wait for clear timeout.\n");
  29 }
  30 #endif
  31
  32 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  33 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  34 #endif
  35
  36 /*
  37  * regs has the to-be-set values for DDR controller registers
  38  * ctrl_num is the DDR controller number
  39  * step: 0 goes through the initialization in one pass
  40  *       1 sets registers and returns before enabling controller
  41  *       2 resumes from step 1 and continues to initialize
  42  * Dividing the initialization to two steps to deassert DDR reset signal
  43  * to comply with JEDEC specs for RDIMMs.
  44  */
  45 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  46                              unsigned int ctrl_num, int step)
  47 {
  48         unsigned int i, bus_width;
  49         struct ccsr_ddr __iomem *ddr;
  50         u32 temp_sdram_cfg;
  51         u32 total_gb_size_per_controller;
  52         int timeout;
  53 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  54         u32 temp32, mr6;
  55         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  56         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  57         u32 *vref_seq = vref_seq1;
  58 #endif
  59 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
  60         defined(CONFIG_SYS_FSL_ERRATUM_A010165)
  61         ulong ddr_freq;
  62         u32 tmp;
  63 #endif
  64 #ifdef CONFIG_FSL_DDR_BIST
  65         u32 mtcr, err_detect, err_sbe;
  66         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  67 #endif
  68 #ifdef CONFIG_FSL_DDR_BIST
  69         char buffer[CONFIG_SYS_CBSIZE];
  70 #endif
  71
  72         switch (ctrl_num) {
  73         case 0:
  74                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  75                 break;
  76 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  77         case 1:
  78                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  79                 break;
  80 #endif
  81 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  82         case 2:
  83                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  84                 break;
  85 #endif
  86 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  87         case 3:
  88                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  89                 break;
  90 #endif
  91         default:
  92                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  93                 return;
  94         }
  95
  96         if (step == 2)
  97                 goto step2;
  98
  99         if (regs->ddr_eor)
 100                 ddr_out32(&ddr->eor, regs->ddr_eor);
 101
 102         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 103
 104         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 105                 if (i == 0) {
 106                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 107                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 108                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 109
 110                 } else if (i == 1) {
 111                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 112                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 113                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 114
 115                 } else if (i == 2) {
 116                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 117                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 118                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 119
 120                 } else if (i == 3) {
 121                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 122                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 123                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 124                 }
 125         }
 126
 127         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 128         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 129         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 130         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 131         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 132         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 133         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 134         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 135         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 136         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 137         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 138         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 139         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 140         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 141         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 142         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 143         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 144         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 145         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 146         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 147         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 148         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 149         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 150         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 151         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 152         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 153         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 154         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 155         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 156         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 157         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 158         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 159         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 160 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 161         ddr_out32(&ddr->sdram_interval,
 162                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 163 #else
 164         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 165 #endif
 166         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 167         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 168 #ifndef CONFIG_SYS_FSL_DDR_EMU
 169         /*
 170          * Skip these two registers if running on emulator
 171          * because emulator doesn't have skew between bytes.
 172          */
 173
 174         if (regs->ddr_wrlvl_cntl_2)
 175                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 176         if (regs->ddr_wrlvl_cntl_3)
 177                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 178 #endif
 179
 180         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 181         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 182         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 183         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 184         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 185         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 186         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 187         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 188 #ifdef CONFIG_DEEP_SLEEP
 189         if (is_warm_boot()) {
 190                 ddr_out32(&ddr->sdram_cfg_2,
 191                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 192                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 193                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 194
 195                 /* DRAM VRef will not be trained */
 196                 ddr_out32(&ddr->ddr_cdr2,
 197                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 198         } else
 199 #endif
 200         {
 201                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 202                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 203                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 204                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 205         }
 206
 207 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 208         /* part 1 of 2 */
 209         if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 210                 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
 211                         ddr_out32(&ddr->ddr_sdram_rcw_2,
 212                                   regs->ddr_sdram_rcw_2 & ~0x0f000000);
 213                 }
 214                 ddr_out32(&ddr->err_disable, regs->err_disable |
 215                           DDR_ERR_DISABLE_APED);
 216         }
 217 #else
 218         ddr_out32(&ddr->err_disable, regs->err_disable);
 219 #endif
 220         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 221         for (i = 0; i < 32; i++) {
 222                 if (regs->debug[i]) {
 223                         debug("Write to debug_%d as %08x\n",
 224                               i+1, regs->debug[i]);
 225                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 226                 }
 227         }
 228 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 229         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 230 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 231 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 232         if (has_erratum_a008378()) {
 233                 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 234                     IS_DBI(regs->ddr_sdram_cfg_3))
 235                         ddr_setbits32(&ddr->debug[28], 0x9 << 20);
 236         }
 237 #endif
 238
 239 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 240         /* Part 1 of 2 */
 241         /* This erraum only applies to verion 5.2.0 */
 242         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 243                 /* Disable DRAM VRef training */
 244                 ddr_out32(&ddr->ddr_cdr2,
 245                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 246                 /* disable transmit bit deskew */
 247                 temp32 = ddr_in32(&ddr->debug[28]);
 248                 temp32 |= DDR_TX_BD_DIS;
 249                 ddr_out32(&ddr->debug[28], temp32);
 250                 /* Disable D_INIT */
 251                 ddr_out32(&ddr->sdram_cfg_2,
 252                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 253                 ddr_out32(&ddr->debug[25], 0x9000);
 254         }
 255 #endif
 256
 257 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
 258         temp32 = ddr_in32(&ddr->debug[25]);
 259         temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
 260         temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
 261         ddr_out32(&ddr->debug[25], temp32);
 262 #endif
 263
 264 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 265         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 266         tmp = ddr_in32(&ddr->debug[28]);
 267         if (ddr_freq <= 1333)
 268                 ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
 269         else if (ddr_freq <= 1600)
 270                 ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
 271         else if (ddr_freq <= 1867)
 272                 ddr_out32(&ddr->debug[28], tmp | 0x00700076);
 273         else if (ddr_freq <= 2133)
 274                 ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 275 #endif
 276
 277 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
 278         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 279         if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
 280                 tmp = ddr_in32(&ddr->debug[28]);
 281                 ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
 282         }
 283 #endif
 284         /*
 285          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 286          * deasserted. Clocks start when any chip select is enabled and clock
 287          * control register is set. Because all DDR components are connected to
 288          * one reset signal, this needs to be done in two steps. Step 1 is to
 289          * get the clocks started. Step 2 resumes after reset signal is
 290          * deasserted.
 291          */
 292         if (step == 1) {
 293                 udelay(200);
 294                 return;
 295         }
 296
 297 step2:
 298         /* Set, but do not enable the memory */
 299         temp_sdram_cfg = regs->ddr_sdram_cfg;
 300         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 301         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 302
 303         /*
 304          * 500 painful micro-seconds must elapse between
 305          * the DDR clock setup and the DDR config enable.
 306          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 307          * we choose the max, that is 500 us for all of case.
 308          */
 309         udelay(500);
 310         mb();
 311         isb();
 312
 313 #ifdef CONFIG_DEEP_SLEEP
 314         if (is_warm_boot()) {
 315                 /* enter self-refresh */
 316                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 317                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 318                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 319                 /* do board specific memory setup */
 320                 board_mem_sleep_setup();
 321
 322                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 323         } else
 324 #endif
 325                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 326         /* Let the controller go */
 327         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 328         mb();
 329         isb();
 330
 331 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
 332         defined(CONFIG_SYS_FSL_ERRATUM_A009803)
 333         /* Part 2 of 2 */
 334         /* This erraum only applies to verion 5.2.0 */
 335         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 336                 /* Wait for idle */
 337                 timeout = 40;
 338                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 339                        (timeout > 0)) {
 340                         udelay(1000);
 341                         timeout--;
 342                 }
 343                 if (timeout <= 0) {
 344                         printf("Controler %d timeout, debug_2 = %x\n",
 345                                ctrl_num, ddr_in32(&ddr->debug[1]));
 346                 }
 347
 348 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 349                 /* The vref setting sequence is different for range 2 */
 350                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 351                         vref_seq = vref_seq2;
 352
 353                 /* Set VREF */
 354                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 355                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 356                                 continue;
 357
 358                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 359                                  MD_CNTL_MD_EN                          |
 360                                  MD_CNTL_CS_SEL(i)                      |
 361                                  MD_CNTL_MD_SEL(6)                      |
 362                                  0x00200000;
 363                         temp32 = mr6 | vref_seq[0];
 364                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 365                                                 temp32, MD_CNTL_MD_EN);
 366                         udelay(1);
 367                         debug("MR6 = 0x%08x\n", temp32);
 368                         temp32 = mr6 | vref_seq[1];
 369                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 370                                                 temp32, MD_CNTL_MD_EN);
 371                         udelay(1);
 372                         debug("MR6 = 0x%08x\n", temp32);
 373                         temp32 = mr6 | vref_seq[2];
 374                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 375                                                 temp32, MD_CNTL_MD_EN);
 376                         udelay(1);
 377                         debug("MR6 = 0x%08x\n", temp32);
 378                 }
 379                 ddr_out32(&ddr->sdram_md_cntl, 0);
 380                 temp32 = ddr_in32(&ddr->debug[28]);
 381                 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
 382                 ddr_out32(&ddr->debug[28], temp32);
 383                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 384                 /* wait for idle */
 385                 timeout = 40;
 386                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 387                        (timeout > 0)) {
 388                         udelay(1000);
 389                         timeout--;
 390                 }
 391                 if (timeout <= 0) {
 392                         printf("Controler %d timeout, debug_2 = %x\n",
 393                                ctrl_num, ddr_in32(&ddr->debug[1]));
 394                 }
 395                 /* Restore D_INIT */
 396                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 397 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 398
 399 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 400                 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
 401                         /* if it's RDIMM */
 402                         if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
 403                                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 404                                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 405                                                 continue;
 406                                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 407                                                                 MD_CNTL_MD_EN |
 408                                                                 MD_CNTL_CS_SEL(i) |
 409                                                                 0x070000ed,
 410                                                                 MD_CNTL_MD_EN);
 411                                         udelay(1);
 412                                 }
 413                         }
 414
 415                         ddr_out32(&ddr->err_disable,
 416                                   regs->err_disable & ~DDR_ERR_DISABLE_APED);
 417                 }
 418 #endif
 419         }
 420 #endif
 421
 422         total_gb_size_per_controller = 0;
 423         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 424                 if (!(regs->cs[i].config & 0x80000000))
 425                         continue;
 426                 total_gb_size_per_controller += 1 << (
 427                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 428                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 429                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 430                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 431                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 432                         26);                    /* minus 26 (count of 64M) */
 433         }
 434         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 435                 total_gb_size_per_controller *= 3;
 436         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 437                 total_gb_size_per_controller <<= 1;
 438         /*
 439          * total memory / bus width = transactions needed
 440          * transactions needed / data rate = seconds
 441          * to add plenty of buffer, double the time
 442          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 443          * Let's wait for 800ms
 444          */
 445         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 446                         >> SDRAM_CFG_DBW_SHIFT);
 447         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 448                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 449         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 450         debug("total %d GB\n", total_gb_size_per_controller);
 451         debug("Need to wait up to %d * 10ms\n", timeout);
 452
 453         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 454         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 455                 (timeout >= 0)) {
 456                 udelay(10000);          /* throttle polling rate */
 457                 timeout--;
 458         }
 459
 460         if (timeout <= 0)
 461                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 462
 463 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 464         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 465 #endif
 466
 467 #ifdef CONFIG_DEEP_SLEEP
 468         if (is_warm_boot()) {
 469                 /* exit self-refresh */
 470                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 471                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 472                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 473         }
 474 #endif
 475
 476 #ifdef CONFIG_FSL_DDR_BIST
 477 #define BIST_PATTERN1   0xFFFFFFFF
 478 #define BIST_PATTERN2   0x0
 479 #define BIST_CR         0x80010000
 480 #define BIST_CR_EN      0x80000000
 481 #define BIST_CR_STAT    0x00000001
 482 #define CTLR_INTLV_MASK 0x20000000
 483         /* Perform build-in test on memory. Three-way interleaving is not yet
 484          * supported by this code. */
 485         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 486                 puts("Running BIST test. This will take a while...");
 487                 cs0_config = ddr_in32(&ddr->cs0_config);
 488                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 489                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 490                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 491                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 492                 if (cs0_config & CTLR_INTLV_MASK) {
 493                         /* set bnds to non-interleaving */
 494                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 495                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 496                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 497                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 498                 }
 499                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 500                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 501                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 502                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 503                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 504                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 505                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 506                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 507                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 508                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 509                 mtcr = BIST_CR;
 510                 ddr_out32(&ddr->mtcr, mtcr);
 511                 timeout = 100;
 512                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 513                         mdelay(1000);
 514                         timeout--;
 515                         mtcr = ddr_in32(&ddr->mtcr);
 516                 }
 517                 if (timeout <= 0)
 518                         puts("Timeout\n");
 519                 else
 520                         puts("Done\n");
 521                 err_detect = ddr_in32(&ddr->err_detect);
 522                 err_sbe = ddr_in32(&ddr->err_sbe);
 523                 if (mtcr & BIST_CR_STAT) {
 524                         printf("BIST test failed on controller %d.\n",
 525                                ctrl_num);
 526                 }
 527                 if (err_detect || (err_sbe & 0xffff)) {
 528                         printf("ECC error detected on controller %d.\n",
 529                                ctrl_num);
 530                 }
 531
 532                 if (cs0_config & CTLR_INTLV_MASK) {
 533                         /* restore bnds registers */
 534                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 535                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 536                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 537                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 538                 }
 539         }
 540 #endif
 541 }