drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_errata.h>
  14
  15 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  16 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  17 {
  18         int timeout = 1000;
  19
  20         ddr_out32(ptr, value);
  21
  22         while (ddr_in32(ptr) & bits) {
  23                 udelay(100);
  24                 timeout--;
  25         }
  26         if (timeout <= 0)
  27                 puts("Error: A007865 wait for clear timeout.\n");
  28 }
  29 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
  30
  31 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  32 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  33 #endif
  34
  35 /*
  36  * regs has the to-be-set values for DDR controller registers
  37  * ctrl_num is the DDR controller number
  38  * step: 0 goes through the initialization in one pass
  39  *       1 sets registers and returns before enabling controller
  40  *       2 resumes from step 1 and continues to initialize
  41  * Dividing the initialization to two steps to deassert DDR reset signal
  42  * to comply with JEDEC specs for RDIMMs.
  43  */
  44 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  45                              unsigned int ctrl_num, int step)
  46 {
  47         unsigned int i, bus_width;
  48         struct ccsr_ddr __iomem *ddr;
  49         u32 temp_sdram_cfg;
  50         u32 total_gb_size_per_controller;
  51         int timeout;
  52 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  53         u32 temp32, mr6;
  54         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  55         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  56         u32 *vref_seq = vref_seq1;
  57 #endif
  58 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  59         ulong ddr_freq;
  60         u32 tmp;
  61 #endif
  62 #ifdef CONFIG_FSL_DDR_BIST
  63         u32 mtcr, err_detect, err_sbe;
  64         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  65 #endif
  66 #ifdef CONFIG_FSL_DDR_BIST
  67         char buffer[CONFIG_SYS_CBSIZE];
  68 #endif
  69
  70         switch (ctrl_num) {
  71         case 0:
  72                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  73                 break;
  74 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  75         case 1:
  76                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  77                 break;
  78 #endif
  79 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  80         case 2:
  81                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  82                 break;
  83 #endif
  84 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  85         case 3:
  86                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  87                 break;
  88 #endif
  89         default:
  90                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
  91                 return;
  92         }
  93
  94         if (step == 2)
  95                 goto step2;
  96
  97         if (regs->ddr_eor)
  98                 ddr_out32(&ddr->eor, regs->ddr_eor);
  99
 100         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 101
 102         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 103                 if (i == 0) {
 104                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 105                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 106                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 107
 108                 } else if (i == 1) {
 109                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 110                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 111                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 112
 113                 } else if (i == 2) {
 114                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 115                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 116                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 117
 118                 } else if (i == 3) {
 119                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 120                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 121                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 122                 }
 123         }
 124
 125         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 126         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 127         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 128         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 129         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 130         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 131         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 132         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 133         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 134         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 135         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 136         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 137         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 138         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 139         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 140         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 141         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 142         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 143         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 144         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 145         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 146         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 147         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 148         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 149         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 150         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 151         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 152         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 153         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 154         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 155         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 156         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 157         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 158 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 159         ddr_out32(&ddr->sdram_interval,
 160                   regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
 161 #else
 162         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 163 #endif
 164         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 165         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 166 #ifndef CONFIG_SYS_FSL_DDR_EMU
 167         /*
 168          * Skip these two registers if running on emulator
 169          * because emulator doesn't have skew between bytes.
 170          */
 171
 172         if (regs->ddr_wrlvl_cntl_2)
 173                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 174         if (regs->ddr_wrlvl_cntl_3)
 175                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 176 #endif
 177
 178         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 179         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 180         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 181         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 182         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 183         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 184         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 185         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 186 #ifdef CONFIG_DEEP_SLEEP
 187         if (is_warm_boot()) {
 188                 ddr_out32(&ddr->sdram_cfg_2,
 189                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 190                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 191                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 192
 193                 /* DRAM VRef will not be trained */
 194                 ddr_out32(&ddr->ddr_cdr2,
 195                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 196         } else
 197 #endif
 198         {
 199                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 200                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 201                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 202                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 203         }
 204         ddr_out32(&ddr->err_disable, regs->err_disable);
 205         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 206         for (i = 0; i < 32; i++) {
 207                 if (regs->debug[i]) {
 208                         debug("Write to debug_%d as %08x\n",
 209                               i+1, regs->debug[i]);
 210                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 211                 }
 212         }
 213 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 214         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 215 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 216 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 217         if (has_erratum_a008378()) {
 218                 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 219                     IS_DBI(regs->ddr_sdram_cfg_3))
 220                         ddr_setbits32(&ddr->debug[28], 0x9 << 20);
 221         }
 222 #endif
 223
 224 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 225         /* Part 1 of 2 */
 226         /* This erraum only applies to verion 5.2.0 */
 227         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 228                 /* Disable DRAM VRef training */
 229                 ddr_out32(&ddr->ddr_cdr2,
 230                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 231                 /* Disable deskew */
 232                 ddr_out32(&ddr->debug[28], 0x400);
 233                 /* Disable D_INIT */
 234                 ddr_out32(&ddr->sdram_cfg_2,
 235                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 236                 ddr_out32(&ddr->debug[25], 0x9000);
 237         }
 238 #endif
 239
 240 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 241         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 242         tmp = ddr_in32(&ddr->debug[28]);
 243         if (ddr_freq <= 1333)
 244                 ddr_out32(&ddr->debug[28], tmp | 0x0080006a);
 245         else if (ddr_freq <= 1600)
 246                 ddr_out32(&ddr->debug[28], tmp | 0x0070006f);
 247         else if (ddr_freq <= 1867)
 248                 ddr_out32(&ddr->debug[28], tmp | 0x00700076);
 249         else if (ddr_freq <= 2133)
 250                 ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 251 #endif
 252
 253         /*
 254          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 255          * deasserted. Clocks start when any chip select is enabled and clock
 256          * control register is set. Because all DDR components are connected to
 257          * one reset signal, this needs to be done in two steps. Step 1 is to
 258          * get the clocks started. Step 2 resumes after reset signal is
 259          * deasserted.
 260          */
 261         if (step == 1) {
 262                 udelay(200);
 263                 return;
 264         }
 265
 266 step2:
 267         /* Set, but do not enable the memory */
 268         temp_sdram_cfg = regs->ddr_sdram_cfg;
 269         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 270         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 271
 272         /*
 273          * 500 painful micro-seconds must elapse between
 274          * the DDR clock setup and the DDR config enable.
 275          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 276          * we choose the max, that is 500 us for all of case.
 277          */
 278         udelay(500);
 279         mb();
 280         isb();
 281
 282 #ifdef CONFIG_DEEP_SLEEP
 283         if (is_warm_boot()) {
 284                 /* enter self-refresh */
 285                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 286                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 287                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 288                 /* do board specific memory setup */
 289                 board_mem_sleep_setup();
 290
 291                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 292         } else
 293 #endif
 294                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 295         /* Let the controller go */
 296         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 297         mb();
 298         isb();
 299
 300 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 301         /* Part 2 of 2 */
 302         /* This erraum only applies to verion 5.2.0 */
 303         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 304                 /* Wait for idle */
 305                 timeout = 40;
 306                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 307                        (timeout > 0)) {
 308                         udelay(1000);
 309                         timeout--;
 310                 }
 311                 if (timeout <= 0) {
 312                         printf("Controler %d timeout, debug_2 = %x\n",
 313                                ctrl_num, ddr_in32(&ddr->debug[1]));
 314                 }
 315
 316                 /* The vref setting sequence is different for range 2 */
 317                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 318                         vref_seq = vref_seq2;
 319
 320                 /* Set VREF */
 321                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 322                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 323                                 continue;
 324
 325                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 326                                  MD_CNTL_MD_EN                          |
 327                                  MD_CNTL_CS_SEL(i)                      |
 328                                  MD_CNTL_MD_SEL(6)                      |
 329                                  0x00200000;
 330                         temp32 = mr6 | vref_seq[0];
 331                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 332                                                 temp32, MD_CNTL_MD_EN);
 333                         udelay(1);
 334                         debug("MR6 = 0x%08x\n", temp32);
 335                         temp32 = mr6 | vref_seq[1];
 336                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 337                                                 temp32, MD_CNTL_MD_EN);
 338                         udelay(1);
 339                         debug("MR6 = 0x%08x\n", temp32);
 340                         temp32 = mr6 | vref_seq[2];
 341                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 342                                                 temp32, MD_CNTL_MD_EN);
 343                         udelay(1);
 344                         debug("MR6 = 0x%08x\n", temp32);
 345                 }
 346                 ddr_out32(&ddr->sdram_md_cntl, 0);
 347                 ddr_out32(&ddr->debug[28], 0);          /* Enable deskew */
 348                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 349                 /* wait for idle */
 350                 timeout = 40;
 351                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 352                        (timeout > 0)) {
 353                         udelay(1000);
 354                         timeout--;
 355                 }
 356                 if (timeout <= 0) {
 357                         printf("Controler %d timeout, debug_2 = %x\n",
 358                                ctrl_num, ddr_in32(&ddr->debug[1]));
 359                 }
 360                 /* Restore D_INIT */
 361                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 362         }
 363 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 364
 365         total_gb_size_per_controller = 0;
 366         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 367                 if (!(regs->cs[i].config & 0x80000000))
 368                         continue;
 369                 total_gb_size_per_controller += 1 << (
 370                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 371                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 372                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 373                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 374                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 375                         26);                    /* minus 26 (count of 64M) */
 376         }
 377         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 378                 total_gb_size_per_controller *= 3;
 379         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 380                 total_gb_size_per_controller <<= 1;
 381         /*
 382          * total memory / bus width = transactions needed
 383          * transactions needed / data rate = seconds
 384          * to add plenty of buffer, double the time
 385          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 386          * Let's wait for 800ms
 387          */
 388         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 389                         >> SDRAM_CFG_DBW_SHIFT);
 390         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 391                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 392         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 393         debug("total %d GB\n", total_gb_size_per_controller);
 394         debug("Need to wait up to %d * 10ms\n", timeout);
 395
 396         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 397         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 398                 (timeout >= 0)) {
 399                 udelay(10000);          /* throttle polling rate */
 400                 timeout--;
 401         }
 402
 403         if (timeout <= 0)
 404                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 405
 406 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 407         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 408 #endif
 409
 410 #ifdef CONFIG_DEEP_SLEEP
 411         if (is_warm_boot()) {
 412                 /* exit self-refresh */
 413                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 414                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 415                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 416         }
 417 #endif
 418
 419 #ifdef CONFIG_FSL_DDR_BIST
 420 #define BIST_PATTERN1   0xFFFFFFFF
 421 #define BIST_PATTERN2   0x0
 422 #define BIST_CR         0x80010000
 423 #define BIST_CR_EN      0x80000000
 424 #define BIST_CR_STAT    0x00000001
 425 #define CTLR_INTLV_MASK 0x20000000
 426         /* Perform build-in test on memory. Three-way interleaving is not yet
 427          * supported by this code. */
 428         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 429                 puts("Running BIST test. This will take a while...");
 430                 cs0_config = ddr_in32(&ddr->cs0_config);
 431                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 432                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 433                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 434                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 435                 if (cs0_config & CTLR_INTLV_MASK) {
 436                         /* set bnds to non-interleaving */
 437                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 438                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 439                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 440                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 441                 }
 442                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 443                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 444                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 445                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 446                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 447                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 448                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 449                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 450                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 451                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 452                 mtcr = BIST_CR;
 453                 ddr_out32(&ddr->mtcr, mtcr);
 454                 timeout = 100;
 455                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 456                         mdelay(1000);
 457                         timeout--;
 458                         mtcr = ddr_in32(&ddr->mtcr);
 459                 }
 460                 if (timeout <= 0)
 461                         puts("Timeout\n");
 462                 else
 463                         puts("Done\n");
 464                 err_detect = ddr_in32(&ddr->err_detect);
 465                 err_sbe = ddr_in32(&ddr->err_sbe);
 466                 if (mtcr & BIST_CR_STAT) {
 467                         printf("BIST test failed on controller %d.\n",
 468                                ctrl_num);
 469                 }
 470                 if (err_detect || (err_sbe & 0xffff)) {
 471                         printf("ECC error detected on controller %d.\n",
 472                                ctrl_num);
 473                 }
 474
 475                 if (cs0_config & CTLR_INTLV_MASK) {
 476                         /* restore bnds registers */
 477                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 478                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 479                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 480                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 481                 }
 482         }
 483 #endif
 484 }