drivers/ddr/fsl/fsl_ddr_gen4.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/processor.h>
  11 #include <fsl_immap.h>
  12 #include <fsl_ddr.h>
  13
  14 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  15 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  16 {
  17         int timeout = 1000;
  18
  19         ddr_out32(ptr, value);
  20
  21         while (ddr_in32(ptr) & bits) {
  22                 udelay(100);
  23                 timeout--;
  24         }
  25         if (timeout <= 0)
  26                 puts("Error: A007865 wait for clear timeout.\n");
  27 }
  28 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
  29
  30 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  31 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  32 #endif
  33
  34 /*
  35  * regs has the to-be-set values for DDR controller registers
  36  * ctrl_num is the DDR controller number
  37  * step: 0 goes through the initialization in one pass
  38  *       1 sets registers and returns before enabling controller
  39  *       2 resumes from step 1 and continues to initialize
  40  * Dividing the initialization to two steps to deassert DDR reset signal
  41  * to comply with JEDEC specs for RDIMMs.
  42  */
  43 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  44                              unsigned int ctrl_num, int step)
  45 {
  46         unsigned int i, bus_width;
  47         struct ccsr_ddr __iomem *ddr;
  48         u32 temp_sdram_cfg;
  49         u32 total_gb_size_per_controller;
  50         int timeout;
  51 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  52         defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  53         u32 *eddrtqcr1;
  54 #endif
  55 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
  56         u32 temp32, mr6;
  57         u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
  58         u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
  59         u32 *vref_seq = vref_seq1;
  60 #endif
  61 #ifdef CONFIG_FSL_DDR_BIST
  62         u32 mtcr, err_detect, err_sbe;
  63         u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
  64 #endif
  65 #ifdef CONFIG_FSL_DDR_BIST
  66         char buffer[CONFIG_SYS_CBSIZE];
  67 #endif
  68
  69         switch (ctrl_num) {
  70         case 0:
  71                 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
  72 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  73         defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  74                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
  75 #endif
  76                 break;
  77 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
  78         case 1:
  79                 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
  80 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  81         defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  82                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
  83 #endif
  84                 break;
  85 #endif
  86 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
  87         case 2:
  88                 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
  89 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  90         defined(CONFIG_SYS_FSL_ERRATUM_A008514)
  91                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
  92 #endif
  93                 break;
  94 #endif
  95 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
  96         case 3:
  97                 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
  98 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
  99         defined(CONFIG_SYS_FSL_ERRATUM_A008514)
 100                 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
 101 #endif
 102                 break;
 103 #endif
 104         default:
 105                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
 106                 return;
 107         }
 108
 109         if (step == 2)
 110                 goto step2;
 111
 112 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 113 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 114         /* A008336 only applies to general DDR controllers */
 115         if ((ctrl_num == 0) || (ctrl_num == 1))
 116 #endif
 117                 ddr_out32(eddrtqcr1, 0x63b30002);
 118 #endif
 119 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
 120 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 121         /* A008514 only applies to DP-DDR controler */
 122         if (ctrl_num == 2)
 123 #endif
 124                 ddr_out32(eddrtqcr1, 0x63b20002);
 125 #endif
 126         if (regs->ddr_eor)
 127                 ddr_out32(&ddr->eor, regs->ddr_eor);
 128
 129         ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
 130
 131         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 132                 if (i == 0) {
 133                         ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
 134                         ddr_out32(&ddr->cs0_config, regs->cs[i].config);
 135                         ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
 136
 137                 } else if (i == 1) {
 138                         ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
 139                         ddr_out32(&ddr->cs1_config, regs->cs[i].config);
 140                         ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
 141
 142                 } else if (i == 2) {
 143                         ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
 144                         ddr_out32(&ddr->cs2_config, regs->cs[i].config);
 145                         ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
 146
 147                 } else if (i == 3) {
 148                         ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
 149                         ddr_out32(&ddr->cs3_config, regs->cs[i].config);
 150                         ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
 151                 }
 152         }
 153
 154         ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
 155         ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
 156         ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
 157         ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 158         ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
 159         ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 160         ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
 161         ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
 162         ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
 163         ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
 164         ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 165         ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
 166         ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
 167         ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
 168         ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
 169         ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
 170         ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
 171         ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
 172         ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
 173         ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
 174         ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
 175         ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
 176         ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
 177         ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
 178         ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
 179         ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
 180         ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
 181         ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
 182         ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
 183         ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
 184         ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
 185         ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
 186         ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
 187         ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 188         ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
 189         ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 190 #ifndef CONFIG_SYS_FSL_DDR_EMU
 191         /*
 192          * Skip these two registers if running on emulator
 193          * because emulator doesn't have skew between bytes.
 194          */
 195
 196         if (regs->ddr_wrlvl_cntl_2)
 197                 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
 198         if (regs->ddr_wrlvl_cntl_3)
 199                 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
 200 #endif
 201
 202         ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 203         ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 204         ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 205         ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
 206         ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
 207         ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
 208         ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
 209         ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
 210 #ifdef CONFIG_DEEP_SLEEP
 211         if (is_warm_boot()) {
 212                 ddr_out32(&ddr->sdram_cfg_2,
 213                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 214                 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 215                 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
 216
 217                 /* DRAM VRef will not be trained */
 218                 ddr_out32(&ddr->ddr_cdr2,
 219                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 220         } else
 221 #endif
 222         {
 223                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 224                 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
 225                 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
 226                 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
 227         }
 228         ddr_out32(&ddr->err_disable, regs->err_disable);
 229         ddr_out32(&ddr->err_int_en, regs->err_int_en);
 230         for (i = 0; i < 32; i++) {
 231                 if (regs->debug[i]) {
 232                         debug("Write to debug_%d as %08x\n",
 233                               i+1, regs->debug[i]);
 234                         ddr_out32(&ddr->debug[i], regs->debug[i]);
 235                 }
 236         }
 237 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
 238         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
 239 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
 240 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
 241         if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
 242             IS_DBI(regs->ddr_sdram_cfg_3))
 243                 ddr_setbits32(ddr->debug[28], 0x9 << 20);
 244 #endif
 245
 246 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 247         /* Part 1 of 2 */
 248         /* This erraum only applies to verion 5.2.0 */
 249         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 250                 /* Disable DRAM VRef training */
 251                 ddr_out32(&ddr->ddr_cdr2,
 252                           regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
 253                 /* Disable deskew */
 254                 ddr_out32(&ddr->debug[28], 0x400);
 255                 /* Disable D_INIT */
 256                 ddr_out32(&ddr->sdram_cfg_2,
 257                           regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
 258                 ddr_out32(&ddr->debug[25], 0x9000);
 259         }
 260 #endif
 261         /*
 262          * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 263          * deasserted. Clocks start when any chip select is enabled and clock
 264          * control register is set. Because all DDR components are connected to
 265          * one reset signal, this needs to be done in two steps. Step 1 is to
 266          * get the clocks started. Step 2 resumes after reset signal is
 267          * deasserted.
 268          */
 269         if (step == 1) {
 270                 udelay(200);
 271                 return;
 272         }
 273
 274 step2:
 275         /* Set, but do not enable the memory */
 276         temp_sdram_cfg = regs->ddr_sdram_cfg;
 277         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 278         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
 279
 280         /*
 281          * 500 painful micro-seconds must elapse between
 282          * the DDR clock setup and the DDR config enable.
 283          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 284          * we choose the max, that is 500 us for all of case.
 285          */
 286         udelay(500);
 287         mb();
 288         isb();
 289
 290 #ifdef CONFIG_DEEP_SLEEP
 291         if (is_warm_boot()) {
 292                 /* enter self-refresh */
 293                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 294                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 295                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 296                 /* do board specific memory setup */
 297                 board_mem_sleep_setup();
 298
 299                 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
 300         } else
 301 #endif
 302                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 303         /* Let the controller go */
 304         ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 305         mb();
 306         isb();
 307
 308 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
 309         /* Part 2 of 2 */
 310         /* This erraum only applies to verion 5.2.0 */
 311         if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
 312                 /* Wait for idle */
 313                 timeout = 40;
 314                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 315                        (timeout > 0)) {
 316                         udelay(1000);
 317                         timeout--;
 318                 }
 319                 if (timeout <= 0) {
 320                         printf("Controler %d timeout, debug_2 = %x\n",
 321                                ctrl_num, ddr_in32(&ddr->debug[1]));
 322                 }
 323
 324                 /* The vref setting sequence is different for range 2 */
 325                 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
 326                         vref_seq = vref_seq2;
 327
 328                 /* Set VREF */
 329                 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 330                         if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
 331                                 continue;
 332
 333                         mr6 = (regs->ddr_sdram_mode_10 >> 16)           |
 334                                  MD_CNTL_MD_EN                          |
 335                                  MD_CNTL_CS_SEL(i)                      |
 336                                  MD_CNTL_MD_SEL(6)                      |
 337                                  0x00200000;
 338                         temp32 = mr6 | vref_seq[0];
 339                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 340                                                 temp32, MD_CNTL_MD_EN);
 341                         udelay(1);
 342                         debug("MR6 = 0x%08x\n", temp32);
 343                         temp32 = mr6 | vref_seq[1];
 344                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 345                                                 temp32, MD_CNTL_MD_EN);
 346                         udelay(1);
 347                         debug("MR6 = 0x%08x\n", temp32);
 348                         temp32 = mr6 | vref_seq[2];
 349                         set_wait_for_bits_clear(&ddr->sdram_md_cntl,
 350                                                 temp32, MD_CNTL_MD_EN);
 351                         udelay(1);
 352                         debug("MR6 = 0x%08x\n", temp32);
 353                 }
 354                 ddr_out32(&ddr->sdram_md_cntl, 0);
 355                 ddr_out32(&ddr->debug[28], 0);          /* Enable deskew */
 356                 ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
 357                 /* wait for idle */
 358                 timeout = 40;
 359                 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
 360                        (timeout > 0)) {
 361                         udelay(1000);
 362                         timeout--;
 363                 }
 364                 if (timeout <= 0) {
 365                         printf("Controler %d timeout, debug_2 = %x\n",
 366                                ctrl_num, ddr_in32(&ddr->debug[1]));
 367                 }
 368                 /* Restore D_INIT */
 369                 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 370         }
 371 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 372
 373         total_gb_size_per_controller = 0;
 374         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 375                 if (!(regs->cs[i].config & 0x80000000))
 376                         continue;
 377                 total_gb_size_per_controller += 1 << (
 378                         ((regs->cs[i].config >> 14) & 0x3) + 2 +
 379                         ((regs->cs[i].config >> 8) & 0x7) + 12 +
 380                         ((regs->cs[i].config >> 4) & 0x3) + 0 +
 381                         ((regs->cs[i].config >> 0) & 0x7) + 8 +
 382                         3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
 383                         26);                    /* minus 26 (count of 64M) */
 384         }
 385         if (fsl_ddr_get_intl3r() & 0x80000000)  /* 3-way interleaving */
 386                 total_gb_size_per_controller *= 3;
 387         else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
 388                 total_gb_size_per_controller <<= 1;
 389         /*
 390          * total memory / bus width = transactions needed
 391          * transactions needed / data rate = seconds
 392          * to add plenty of buffer, double the time
 393          * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 394          * Let's wait for 800ms
 395          */
 396         bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
 397                         >> SDRAM_CFG_DBW_SHIFT);
 398         timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
 399                 (get_ddr_freq(ctrl_num) >> 20)) << 2;
 400         total_gb_size_per_controller >>= 4;     /* shift down to gb size */
 401         debug("total %d GB\n", total_gb_size_per_controller);
 402         debug("Need to wait up to %d * 10ms\n", timeout);
 403
 404         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 405         while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
 406                 (timeout >= 0)) {
 407                 udelay(10000);          /* throttle polling rate */
 408                 timeout--;
 409         }
 410
 411         if (timeout <= 0)
 412                 printf("Waiting for D_INIT timeout. Memory may not work.\n");
 413 #ifdef CONFIG_DEEP_SLEEP
 414         if (is_warm_boot()) {
 415                 /* exit self-refresh */
 416                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 417                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 418                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 419         }
 420 #endif
 421
 422 #ifdef CONFIG_FSL_DDR_BIST
 423 #define BIST_PATTERN1   0xFFFFFFFF
 424 #define BIST_PATTERN2   0x0
 425 #define BIST_CR         0x80010000
 426 #define BIST_CR_EN      0x80000000
 427 #define BIST_CR_STAT    0x00000001
 428 #define CTLR_INTLV_MASK 0x20000000
 429         /* Perform build-in test on memory. Three-way interleaving is not yet
 430          * supported by this code. */
 431         if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
 432                 puts("Running BIST test. This will take a while...");
 433                 cs0_config = ddr_in32(&ddr->cs0_config);
 434                 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
 435                 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
 436                 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
 437                 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
 438                 if (cs0_config & CTLR_INTLV_MASK) {
 439                         /* set bnds to non-interleaving */
 440                         ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
 441                         ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
 442                         ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
 443                         ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
 444                 }
 445                 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
 446                 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
 447                 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
 448                 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
 449                 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
 450                 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
 451                 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
 452                 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
 453                 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
 454                 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
 455                 mtcr = BIST_CR;
 456                 ddr_out32(&ddr->mtcr, mtcr);
 457                 timeout = 100;
 458                 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
 459                         mdelay(1000);
 460                         timeout--;
 461                         mtcr = ddr_in32(&ddr->mtcr);
 462                 }
 463                 if (timeout <= 0)
 464                         puts("Timeout\n");
 465                 else
 466                         puts("Done\n");
 467                 err_detect = ddr_in32(&ddr->err_detect);
 468                 err_sbe = ddr_in32(&ddr->err_sbe);
 469                 if (mtcr & BIST_CR_STAT) {
 470                         printf("BIST test failed on controller %d.\n",
 471                                ctrl_num);
 472                 }
 473                 if (err_detect || (err_sbe & 0xffff)) {
 474                         printf("ECC error detected on controller %d.\n",
 475                                ctrl_num);
 476                 }
 477
 478                 if (cs0_config & CTLR_INTLV_MASK) {
 479                         /* restore bnds registers */
 480                         ddr_out32(&ddr->cs0_bnds, cs0_bnds);
 481                         ddr_out32(&ddr->cs1_bnds, cs1_bnds);
 482                         ddr_out32(&ddr->cs2_bnds, cs2_bnds);
 483                         ddr_out32(&ddr->cs3_bnds, cs3_bnds);
 484                 }
 485         }
 486 #endif
 487 }